powerpc/85xx: Adding DCSR node to dtsi device trees
Adding new device tree binding file for the DCSR node. Modifying device tree dtsi files to add DCSR node for P2041, P3041, P4080, & P5020. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Stephen George
Kumar Gala
Родитель
499ccb27a8
Коммит
b9df022319
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@ -0,0 +1,395 @@
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===================================================================
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Debug Control and Status Register (DCSR) Binding
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Copyright 2011 Freescale Semiconductor Inc.
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NOTE: The bindings described in this document are preliminary and subject
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to change. Some of the compatible strings that contain only generic names
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may turn out to be inappropriate, or need additional properties to describe
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the integration of the block with the rest of the chip.
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=====================================================================
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Debug Control and Status Register Memory Map
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Description
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This node defines the base address and range for the
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defined DCSR Memory Map. Child nodes will describe the individual
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debug blocks defined within this memory space.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,dcsr" and "simple-bus".
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The DCSR space exists in the memory-mapped bus.
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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or representing physical addresses in child nodes.
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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or representing the size of physical addresses in
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child nodes.
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- ranges
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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range of the DCSR space.
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EXAMPLE
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dcsr: dcsr@f00000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,dcsr", "simple-bus";
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ranges = <0x00000000 0xf 0x00000000 0x01008000>;
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};
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=====================================================================
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Event Processing Unit
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This node represents the region of DCSR space allocated to the EPU
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,dcsr-epu"
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- interrupts
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Usage: required
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Value type: <prop_encoded-array>
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Definition: Specifies the interrupts generated by the EPU.
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The value of the interrupts property consists of three
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interrupt specifiers. The format of the specifier is defined
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by the binding document describing the node's interrupt parent.
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The EPU counters can be configured to assert the performance
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monitor interrupt signal based on either counter overflow or value
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match. Which counter asserted the interrupt is captured in an EPU
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Counter Interrupt Status Register (EPCPUISR).
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The EPU unit can also be configured to assert either or both of
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two interrupt signals based on debug event sources within the SoC.
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The interrupt signals are epu_xt_int0 and epu_xt_int1.
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Which event source asserted the interrupt is captured in an EPU
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Interrupt Status Register (EPISR0,EPISR1).
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Interrupt numbers are lised in order (perfmon, event0, event1).
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- interrupt-parent
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Usage: required
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Value type: <phandle>
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Definition: A single <phandle> value that points
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to the interrupt parent to which the child domain
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is being mapped. Value must be "&mpic"
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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EXAMPLE
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dcsr-epu@0 {
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compatible = "fsl,dcsr-epu";
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interrupts = <52 2 0 0
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84 2 0 0
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85 2 0 0>;
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interrupt-parent = <&mpic>;
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reg = <0x0 0x1000>;
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};
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=======================================================================
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Nexus Port Controller
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This node represents the region of DCSR space allocated to the NPC
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,dcsr-npc"
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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The Nexus Port controller occupies two regions in the DCSR space
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with distinct functionality.
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The first register range describes the Nexus Port Controller
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control and status registers.
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The second register range describes the Nexus Port Controller
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internal trace buffer. The NPC trace buffer is a small memory buffer
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which stages the nexus trace data for transmission via the Aurora port
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or to a DDR based trace buffer. In some configurations the NPC trace
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buffer can be the only trace buffer used.
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EXAMPLE
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dcsr-npc {
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compatible = "fsl,dcsr-npc";
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reg = <0x1000 0x1000 0x1000000 0x8000>;
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};
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=======================================================================
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Nexus Concentrator
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This node represents the region of DCSR space allocated to the NXC
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,dcsr-nxc"
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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EXAMPLE
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dcsr-nxc@2000 {
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compatible = "fsl,dcsr-nxc";
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reg = <0x2000 0x1000>;
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};
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=======================================================================
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CoreNet Debug Controller
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This node represents the region of DCSR space allocated to
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the CoreNet Debug controller.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,dcsr-corenet"
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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The CoreNet Debug controller occupies two regions in the DCSR space
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with distinct functionality.
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The first register range describes the CoreNet Debug Controller
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functionalty to perform transaction and transaction attribute matches.
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The second register range describes the CoreNet Debug Controller
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functionalty to trigger event notifications and debug traces.
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EXAMPLE
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dcsr-corenet {
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compatible = "fsl,dcsr-corenet";
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reg = <0x8000 0x1000 0xB0000 0x1000>;
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};
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=======================================================================
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Data Path Debug controller
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This node represents the region of DCSR space allocated to
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the DPAA Debug Controller. This controller controls debug configuration
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for the QMAN and FMAN blocks.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include both an identifier specific to the SoC
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or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
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generic compatible string "fsl,dcsr-dpaa".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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EXAMPLE
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dcsr-dpaa@9000 {
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compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
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reg = <0x9000 0x1000>;
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};
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=======================================================================
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OCeaN Debug controller
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This node represents the region of DCSR space allocated to
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the OCN Debug Controller.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include both an identifier specific to the SoC
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or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
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generic compatible string "fsl,dcsr-ocn".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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EXAMPLE
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dcsr-ocn@11000 {
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compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
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reg = <0x11000 0x1000>;
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};
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=======================================================================
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DDR Controller Debug controller
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This node represents the region of DCSR space allocated to
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the OCN Debug Controller.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,dcsr-ddr"
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- dev-handle
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Usage: required
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Definition: A phandle to associate this debug node with its
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component controller.
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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EXAMPLE
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dcsr-ddr@12000 {
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compatible = "fsl,dcsr-ddr";
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dev-handle = <&ddr1>;
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reg = <0x12000 0x1000>;
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};
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=======================================================================
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Nexus Aurora Link Controller
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This node represents the region of DCSR space allocated to
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the NAL Controller.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include both an identifier specific to the SoC
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or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
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generic compatible string "fsl,dcsr-nal".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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EXAMPLE
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dcsr-nal@18000 {
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compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
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reg = <0x18000 0x1000>;
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};
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=======================================================================
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Run Control and Power Management
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This node represents the region of DCSR space allocated to
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the RCPM Debug Controller. This functionlity is limited to the
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control the debug operations of the SoC and cores.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include both an identifier specific to the SoC
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or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
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generic compatible string "fsl,dcsr-rcpm".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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EXAMPLE
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dcsr-rcpm@22000 {
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compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
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reg = <0x22000 0x1000>;
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};
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=======================================================================
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Core Service Bridge Proxy
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This node represents the region of DCSR space allocated to
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the Core Service Bridge Proxies.
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There is one Core Service Bridge Proxy device for each CPU in the system.
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This functionlity provides access to the debug operations of the CPU.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include both an identifier specific to the cpu
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of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
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generic compatible string "fsl,dcsr-cpu-sb-proxy".
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- cpu-handle
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Usage: required
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Definition: A phandle to associate this debug node with its cpu.
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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offset and length of the DCSR space registers of the device
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configuration block.
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EXAMPLE
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dcsr-cpu-sb-proxy@40000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy",
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"fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu0>;
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reg = <0x40000 0x1000>;
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};
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dcsr-cpu-sb-proxy@41000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy",
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"fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu1>;
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reg = <0x41000 0x1000>;
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};
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=======================================================================
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@ -45,6 +45,10 @@
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device_type = "memory";
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};
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dcsr: dcsr@f00000000 {
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ranges = <0x00000000 0xf 0x00000000 0x01008000>;
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};
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soc: soc@ffe000000 {
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spi@110000 {
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flash@0 {
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@ -42,6 +42,7 @@
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aliases {
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ccsr = &soc;
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dcsr = &dcsr;
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serial0 = &serial0;
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serial1 = &serial1;
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@ -109,6 +110,74 @@
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};
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};
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dcsr: dcsr@f00000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,dcsr", "simple-bus";
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dcsr-epu@0 {
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compatible = "fsl,dcsr-epu";
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interrupts = <52 2 0 0
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84 2 0 0
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85 2 0 0>;
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interrupt-parent = <&mpic>;
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reg = <0x0 0x1000>;
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};
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dcsr-npc {
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compatible = "fsl,dcsr-npc";
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reg = <0x1000 0x1000 0x1000000 0x8000>;
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};
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dcsr-nxc@2000 {
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compatible = "fsl,dcsr-nxc";
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reg = <0x2000 0x1000>;
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};
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dcsr-corenet {
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compatible = "fsl,dcsr-corenet";
|
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reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
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dcsr-dpaa@9000 {
|
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compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
|
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reg = <0x9000 0x1000>;
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};
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dcsr-ocn@11000 {
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compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
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reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
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compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
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||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
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dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
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||||
reg = <0x40000 0x1000>;
|
||||
};
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||||
dcsr-cpu-sb-proxy@41000 {
|
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu1>;
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reg = <0x41000 0x1000>;
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};
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dcsr-cpu-sb-proxy@42000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu2>;
|
||||
reg = <0x42000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@43000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x43000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -128,7 +197,7 @@
|
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fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
memory-controller@8000 {
|
||||
ddr: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
|
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|
|||
|
|
@ -45,6 +45,10 @@
|
|||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
|
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|
|||
|
|
@ -42,6 +42,7 @@
|
|||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
|
|
@ -114,6 +115,74 @@
|
|||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,dcsr-npc";
|
||||
reg = <0x1000 0x1000 0x1000000 0x8000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,p43041-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,p43041-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p43041-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p43041-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x40000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@41000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x41000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@42000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x42000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@43000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x43000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -133,7 +202,7 @@
|
|||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
memory-controller@8000 {
|
||||
ddr: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@
|
|||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@
|
|||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
|
|
@ -143,6 +144,99 @@
|
|||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,dcsr-npc";
|
||||
reg = <0x1000 0x1000 0x1000000 0x8000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@13000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr2>;
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x40000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@41000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x41000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@42000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x42000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@43000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x43000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@44000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu4>;
|
||||
reg = <0x44000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@45000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu5>;
|
||||
reg = <0x45000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@46000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu6>;
|
||||
reg = <0x46000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@47000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu7>;
|
||||
reg = <0x47000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -162,13 +256,13 @@
|
|||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
memory-controller@8000 {
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
memory-controller@9000 {
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 22>;
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@
|
|||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@
|
|||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
|
|
@ -98,6 +99,69 @@
|
|||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,dcsr-npc";
|
||||
reg = <0x1000 0x1000 0x1000000 0x8000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@13000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr2>;
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x40000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@41000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x41000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -117,13 +181,13 @@
|
|||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
memory-controller@8000 {
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
memory-controller@9000 {
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 22>;
|
||||
|
|
|
|||
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