sparc: move the duplication in dma-mapping_{32|64}.h to dma-mapping.h
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Tested-by: Robert Reif <reif@earthlink.net> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
FUJITA Tomonori
David S. Miller
Родитель
0d76cb2606
Коммит
b9f69f4f4a
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@ -5,4 +5,46 @@
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#else
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#include <asm/dma-mapping_32.h>
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#endif
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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extern int dma_supported(struct device *dev, u64 mask);
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extern int dma_set_mask(struct device *dev, u64 dma_mask);
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static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return (dma_addr == DMA_ERROR_CODE);
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}
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static inline int dma_get_cache_alignment(void)
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{
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/*
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* no easy way to get cache size on all processors, so return
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* the maximum possible, to be safe
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*/
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return (1 << INTERNODE_CACHE_SHIFT);
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define dma_is_consistent(d, h) (1)
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static inline void dma_sync_single_range_for_cpu(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single_for_cpu(dev, dma_handle+offset, size, dir);
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}
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static inline void dma_sync_single_range_for_device(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single_for_device(dev, dma_handle+offset, size, dir);
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}
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#endif
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@ -7,10 +7,6 @@ struct device;
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struct scatterlist;
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struct page;
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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extern int dma_supported(struct device *dev, u64 mask);
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extern int dma_set_mask(struct device *dev, u64 dma_mask);
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extern void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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extern void dma_free_coherent(struct device *dev, size_t size,
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@ -37,24 +33,10 @@ extern void dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle,
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size_t size,
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enum dma_data_direction direction);
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extern void dma_sync_single_range_for_cpu(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction direction);
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extern void dma_sync_single_range_for_device(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction);
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extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
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int nelems, enum dma_data_direction direction);
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extern void dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction direction);
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extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
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extern int dma_get_cache_alignment(void);
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#define dma_alloc_noncoherent dma_alloc_coherent
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#define dma_free_noncoherent dma_free_coherent
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#endif /* _ASM_SPARC_DMA_MAPPING_H */
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@ -4,8 +4,6 @@
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#include <linux/scatterlist.h>
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#include <linux/mm.h>
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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struct dma_ops {
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void *(*alloc_coherent)(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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@ -31,9 +29,6 @@ struct dma_ops {
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};
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extern const struct dma_ops *dma_ops;
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extern int dma_supported(struct device *dev, u64 mask);
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extern int dma_set_mask(struct device *dev, u64 dma_mask);
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static inline void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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{
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@ -102,25 +97,6 @@ static inline void dma_sync_single_for_device(struct device *dev,
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/* No flushing needed to sync cpu writes to the device. */
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}
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static inline void dma_sync_single_range_for_cpu(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction direction)
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{
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dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
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}
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static inline void dma_sync_single_range_for_device(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction direction)
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{
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/* No flushing needed to sync cpu writes to the device. */
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}
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static inline void dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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@ -135,20 +111,4 @@ static inline void dma_sync_sg_for_device(struct device *dev,
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/* No flushing needed to sync cpu writes to the device. */
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}
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static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return (dma_addr == DMA_ERROR_CODE);
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}
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static inline int dma_get_cache_alignment(void)
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{
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/* no easy way to get cache size on all processors, so return
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* the maximum possible, to be safe */
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return (1 << INTERNODE_CACHE_SHIFT);
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define dma_is_consistent(d, h) (1)
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#endif /* _ASM_SPARC64_DMA_MAPPING_H */
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@ -167,24 +167,6 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
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}
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EXPORT_SYMBOL(dma_sync_single_for_device);
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void dma_sync_single_range_for_cpu(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction direction)
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{
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dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
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void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_range_for_device);
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void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
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int nelems, enum dma_data_direction direction)
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{
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@ -213,15 +195,3 @@ void dma_sync_sg_for_device(struct device *dev,
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BUG();
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}
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EXPORT_SYMBOL(dma_sync_sg_for_device);
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int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return (dma_addr == DMA_ERROR_CODE);
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}
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EXPORT_SYMBOL(dma_mapping_error);
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int dma_get_cache_alignment(void)
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{
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return 32;
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}
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EXPORT_SYMBOL(dma_get_cache_alignment);
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