Intel IOMMU: Intel IOMMU driver
Actual intel IOMMU driver. Hardware spec can be found at: http://www.intel.com/technology/virtualization This driver sets X86_64 'dma_ops', so hook into standard DMA APIs. In this way, PCI driver will get virtual DMA address. This change is transparent to PCI drivers. [akpm@linux-foundation.org: remove unneeded cast] [akpm@linux-foundation.org: build fix] [bunk@stusta.de: fix duplicate CONFIG_DMAR Makefile line] Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Keshavamurthy, Anil S
Linus Torvalds
Родитель
f8de50eb6b
Коммит
ba39592764
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Linux IOMMU Support
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===================
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The architecture spec can be obtained from the below location.
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http://www.intel.com/technology/virtualization/
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This guide gives a quick cheat sheet for some basic understanding.
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Some Keywords
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DMAR - DMA remapping
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DRHD - DMA Engine Reporting Structure
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RMRR - Reserved memory Region Reporting Structure
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ZLR - Zero length reads from PCI devices
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IOVA - IO Virtual address.
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Basic stuff
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-----------
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ACPI enumerates and lists the different DMA engines in the platform, and
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device scope relationships between PCI devices and which DMA engine controls
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them.
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What is RMRR?
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-------------
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There are some devices the BIOS controls, for e.g USB devices to perform
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PS2 emulation. The regions of memory used for these devices are marked
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reserved in the e820 map. When we turn on DMA translation, DMA to those
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regions will fail. Hence BIOS uses RMRR to specify these regions along with
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devices that need to access these regions. OS is expected to setup
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unity mappings for these regions for these devices to access these regions.
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How is IOVA generated?
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---------------------
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Well behaved drivers call pci_map_*() calls before sending command to device
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that needs to perform DMA. Once DMA is completed and mapping is no longer
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required, device performs a pci_unmap_*() calls to unmap the region.
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The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
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device has its own domain (hence protection). Devices under p2p bridges
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share the virtual address with all devices under the p2p bridge due to
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transaction id aliasing for p2p bridges.
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IOVA generation is pretty generic. We used the same technique as vmalloc()
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but these are not global address spaces, but separate for each domain.
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Different DMA engines may support different number of domains.
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We also allocate gaurd pages with each mapping, so we can attempt to catch
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any overflow that might happen.
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Graphics Problems?
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------------------
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If you encounter issues with graphics devices, you can try adding
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option intel_iommu=igfx_off to turn off the integrated graphics engine.
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Some exceptions to IOVA
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-----------------------
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Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
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The same is true for peer to peer transactions. Hence we reserve the
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address from PCI MMIO ranges so they are not allocated for IOVA addresses.
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Boot Message Sample
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-------------------
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Something like this gets printed indicating presence of DMAR tables
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in ACPI.
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ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
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When DMAR is being processed and initialized by ACPI, prints DMAR locations
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and any RMRR's processed.
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ACPI DMAR:Host address width 36
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ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
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ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
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ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
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ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
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ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
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When DMAR is enabled for use, you will notice..
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PCI-DMA: Using DMAR IOMMU
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TBD
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----
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- For compatibility testing, could use unity map domain for all devices, just
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provide a 1-1 for all useful memory under a single domain for all devices.
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- API for paravirt ops for abstracting functionlity for VMM folks.
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@ -772,6 +772,16 @@ and is between 256 and 4096 characters. It is defined in the file
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inttest= [IA64]
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intel_iommu= [DMAR] Intel IOMMU driver (DMAR) option
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off
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Disable intel iommu driver.
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igfx_off [Default Off]
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By default, gfx is mapped as normal device. If a gfx
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device has a dedicated DMAR unit, the DMAR unit is
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bypassed by not enabling DMAR with this option. In
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this case, gfx device will use physical address for
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DMA.
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io7= [HW] IO7 for Marvel based alpha systems
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See comment before marvel_specify_io7 in
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arch/alpha/kernel/core_marvel.c.
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@ -7,6 +7,7 @@
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/dmar.h>
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#include <asm/io.h>
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#include <asm/iommu.h>
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#include <asm/calgary.h>
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@ -305,6 +306,8 @@ void __init pci_iommu_alloc(void)
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detect_calgary();
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#endif
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detect_intel_iommu();
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#ifdef CONFIG_SWIOTLB
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pci_swiotlb_init();
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#endif
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@ -316,6 +319,8 @@ static int __init pci_iommu_init(void)
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calgary_iommu_init();
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#endif
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intel_iommu_init();
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#ifdef CONFIG_IOMMU
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gart_iommu_init();
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#endif
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@ -21,7 +21,7 @@ obj-$(CONFIG_PCI_MSI) += msi.o
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obj-$(CONFIG_HT_IRQ) += htirq.o
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# Build Intel IOMMU support
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obj-$(CONFIG_DMAR) += dmar.o
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obj-$(CONFIG_DMAR) += dmar.o iova.o intel-iommu.o
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#
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# Some architectures use the generic PCI setup functions
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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/*
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* Copyright (c) 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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* Copyright (C) Ashok Raj <ashok.raj@intel.com>
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* Copyright (C) Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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*/
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#ifndef _INTEL_IOMMU_H_
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#define _INTEL_IOMMU_H_
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#include <linux/types.h>
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#include <linux/msi.h>
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#include "iova.h"
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#include <linux/io.h>
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/*
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* Intel IOMMU register specification per version 1.0 public spec.
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*/
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#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
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#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
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#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
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#define DMAR_GCMD_REG 0x18 /* Global command register */
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#define DMAR_GSTS_REG 0x1c /* Global status register */
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#define DMAR_RTADDR_REG 0x20 /* Root entry table */
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#define DMAR_CCMD_REG 0x28 /* Context command reg */
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#define DMAR_FSTS_REG 0x34 /* Fault Status register */
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#define DMAR_FECTL_REG 0x38 /* Fault control register */
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#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
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#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
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#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
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#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
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#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
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#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
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#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
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#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
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#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
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#define OFFSET_STRIDE (9)
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/*
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#define dmar_readl(dmar, reg) readl(dmar + reg)
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#define dmar_readq(dmar, reg) ({ \
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u32 lo, hi; \
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lo = readl(dmar + reg); \
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hi = readl(dmar + reg + 4); \
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(((u64) hi) << 32) + lo; })
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*/
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static inline u64 dmar_readq(void *addr)
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{
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u32 lo, hi;
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lo = readl(addr);
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hi = readl(addr + 4);
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return (((u64) hi) << 32) + lo;
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}
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static inline void dmar_writeq(void __iomem *addr, u64 val)
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{
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writel((u32)val, addr);
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writel((u32)(val >> 32), addr + 4);
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}
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#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
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#define DMAR_VER_MINOR(v) ((v) & 0x0f)
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/*
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* Decoding Capability Register
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*/
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#define cap_read_drain(c) (((c) >> 55) & 1)
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#define cap_write_drain(c) (((c) >> 54) & 1)
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#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
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#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
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#define cap_pgsel_inv(c) (((c) >> 39) & 1)
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#define cap_super_page_val(c) (((c) >> 34) & 0xf)
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#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
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* OFFSET_STRIDE) + 21)
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#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
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#define cap_max_fault_reg_offset(c) \
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(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
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#define cap_zlr(c) (((c) >> 22) & 1)
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#define cap_isoch(c) (((c) >> 23) & 1)
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#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
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#define cap_sagaw(c) (((c) >> 8) & 0x1f)
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#define cap_caching_mode(c) (((c) >> 7) & 1)
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#define cap_phmr(c) (((c) >> 6) & 1)
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#define cap_plmr(c) (((c) >> 5) & 1)
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#define cap_rwbf(c) (((c) >> 4) & 1)
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#define cap_afl(c) (((c) >> 3) & 1)
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#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
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/*
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* Extended Capability Register
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*/
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#define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
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#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
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#define ecap_max_iotlb_offset(e) \
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(ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
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#define ecap_coherent(e) ((e) & 0x1)
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/* IOTLB_REG */
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#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
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#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
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#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
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#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
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#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
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#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
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#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
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#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
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#define DMA_TLB_IVT (((u64)1) << 63)
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#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
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#define DMA_TLB_MAX_SIZE (0x3f)
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/* GCMD_REG */
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#define DMA_GCMD_TE (((u32)1) << 31)
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#define DMA_GCMD_SRTP (((u32)1) << 30)
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#define DMA_GCMD_SFL (((u32)1) << 29)
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#define DMA_GCMD_EAFL (((u32)1) << 28)
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#define DMA_GCMD_WBF (((u32)1) << 27)
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/* GSTS_REG */
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#define DMA_GSTS_TES (((u32)1) << 31)
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#define DMA_GSTS_RTPS (((u32)1) << 30)
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#define DMA_GSTS_FLS (((u32)1) << 29)
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#define DMA_GSTS_AFLS (((u32)1) << 28)
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#define DMA_GSTS_WBFS (((u32)1) << 27)
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/* CCMD_REG */
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#define DMA_CCMD_ICC (((u64)1) << 63)
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#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
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#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
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#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
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#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
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#define DMA_CCMD_MASK_NOBIT 0
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#define DMA_CCMD_MASK_1BIT 1
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#define DMA_CCMD_MASK_2BIT 2
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#define DMA_CCMD_MASK_3BIT 3
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#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
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#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
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/* FECTL_REG */
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#define DMA_FECTL_IM (((u32)1) << 31)
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/* FSTS_REG */
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#define DMA_FSTS_PPF ((u32)2)
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#define DMA_FSTS_PFO ((u32)1)
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#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
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/* FRCD_REG, 32 bits access */
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#define DMA_FRCD_F (((u32)1) << 31)
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#define dma_frcd_type(d) ((d >> 30) & 1)
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#define dma_frcd_fault_reason(c) (c & 0xff)
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#define dma_frcd_source_id(c) (c & 0xffff)
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#define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */
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/*
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* 0: Present
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* 1-11: Reserved
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* 12-63: Context Ptr (12 - (haw-1))
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* 64-127: Reserved
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*/
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struct root_entry {
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u64 val;
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u64 rsvd1;
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};
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#define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry))
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static inline bool root_present(struct root_entry *root)
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{
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return (root->val & 1);
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}
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static inline void set_root_present(struct root_entry *root)
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{
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root->val |= 1;
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}
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static inline void set_root_value(struct root_entry *root, unsigned long value)
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{
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root->val |= value & PAGE_MASK_4K;
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}
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struct context_entry;
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static inline struct context_entry *
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get_context_addr_from_root(struct root_entry *root)
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{
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return (struct context_entry *)
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(root_present(root)?phys_to_virt(
|
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root->val & PAGE_MASK_4K):
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NULL);
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}
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/*
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* low 64 bits:
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* 0: present
|
||||
* 1: fault processing disable
|
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* 2-3: translation type
|
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* 12-63: address space root
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* high 64 bits:
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* 0-2: address width
|
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* 3-6: aval
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* 8-23: domain id
|
||||
*/
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struct context_entry {
|
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u64 lo;
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u64 hi;
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};
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#define context_present(c) ((c).lo & 1)
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#define context_fault_disable(c) (((c).lo >> 1) & 1)
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#define context_translation_type(c) (((c).lo >> 2) & 3)
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#define context_address_root(c) ((c).lo & PAGE_MASK_4K)
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#define context_address_width(c) ((c).hi & 7)
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#define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
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#define context_set_present(c) do {(c).lo |= 1;} while (0)
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#define context_set_fault_enable(c) \
|
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do {(c).lo &= (((u64)-1) << 2) | 1;} while (0)
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#define context_set_translation_type(c, val) \
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do { \
|
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(c).lo &= (((u64)-1) << 4) | 3; \
|
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(c).lo |= ((val) & 3) << 2; \
|
||||
} while (0)
|
||||
#define CONTEXT_TT_MULTI_LEVEL 0
|
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#define context_set_address_root(c, val) \
|
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do {(c).lo |= (val) & PAGE_MASK_4K;} while (0)
|
||||
#define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0)
|
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#define context_set_domain_id(c, val) \
|
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do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
|
||||
#define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
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||||
|
||||
/*
|
||||
* 0: readable
|
||||
* 1: writable
|
||||
* 2-6: reserved
|
||||
* 7: super page
|
||||
* 8-11: available
|
||||
* 12-63: Host physcial address
|
||||
*/
|
||||
struct dma_pte {
|
||||
u64 val;
|
||||
};
|
||||
#define dma_clear_pte(p) do {(p).val = 0;} while (0)
|
||||
|
||||
#define DMA_PTE_READ (1)
|
||||
#define DMA_PTE_WRITE (2)
|
||||
|
||||
#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
|
||||
#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
|
||||
#define dma_set_pte_prot(p, prot) \
|
||||
do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
|
||||
#define dma_pte_addr(p) ((p).val & PAGE_MASK_4K)
|
||||
#define dma_set_pte_addr(p, addr) do {\
|
||||
(p).val |= ((addr) & PAGE_MASK_4K); } while (0)
|
||||
#define dma_pte_present(p) (((p).val & 3) != 0)
|
||||
|
||||
struct intel_iommu;
|
||||
|
||||
struct dmar_domain {
|
||||
int id; /* domain id */
|
||||
struct intel_iommu *iommu; /* back pointer to owning iommu */
|
||||
|
||||
struct list_head devices; /* all devices' list */
|
||||
struct iova_domain iovad; /* iova's that belong to this domain */
|
||||
|
||||
struct dma_pte *pgd; /* virtual address */
|
||||
spinlock_t mapping_lock; /* page table lock */
|
||||
int gaw; /* max guest address width */
|
||||
|
||||
/* adjusted guest address width, 0 is level 2 30-bit */
|
||||
int agaw;
|
||||
|
||||
#define DOMAIN_FLAG_MULTIPLE_DEVICES 1
|
||||
int flags;
|
||||
};
|
||||
|
||||
/* PCI domain-device relationship */
|
||||
struct device_domain_info {
|
||||
struct list_head link; /* link to domain siblings */
|
||||
struct list_head global; /* link to global list */
|
||||
u8 bus; /* PCI bus numer */
|
||||
u8 devfn; /* PCI devfn number */
|
||||
struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
|
||||
struct dmar_domain *domain; /* pointer to domain */
|
||||
};
|
||||
|
||||
extern int init_dmars(void);
|
||||
|
||||
struct intel_iommu {
|
||||
void __iomem *reg; /* Pointer to hardware regs, virtual addr */
|
||||
u64 cap;
|
||||
u64 ecap;
|
||||
unsigned long *domain_ids; /* bitmap of domains */
|
||||
struct dmar_domain **domains; /* ptr to domains */
|
||||
int seg;
|
||||
u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
|
||||
spinlock_t lock; /* protect context, domain ids */
|
||||
spinlock_t register_lock; /* protect register handling */
|
||||
struct root_entry *root_entry; /* virtual address */
|
||||
|
||||
unsigned int irq;
|
||||
unsigned char name[7]; /* Device Name */
|
||||
struct msi_msg saved_msg;
|
||||
struct sys_device sysdev;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -23,7 +23,14 @@
|
|||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/msi.h>
|
||||
|
||||
#ifdef CONFIG_DMAR
|
||||
struct intel_iommu;
|
||||
|
||||
/* Intel IOMMU detection and initialization functions */
|
||||
extern void detect_intel_iommu(void);
|
||||
extern int intel_iommu_init(void);
|
||||
|
||||
extern int dmar_table_init(void);
|
||||
extern int early_dmar_detect(void);
|
||||
|
|
@ -49,4 +56,19 @@ struct dmar_rmrr_unit {
|
|||
int devices_cnt; /* target device count */
|
||||
};
|
||||
|
||||
#define for_each_drhd_unit(drhd) \
|
||||
list_for_each_entry(drhd, &dmar_drhd_units, list)
|
||||
#define for_each_rmrr_units(rmrr) \
|
||||
list_for_each_entry(rmrr, &dmar_rmrr_units, list)
|
||||
#else
|
||||
static inline void detect_intel_iommu(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
static inline int intel_iommu_init(void)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_DMAR */
|
||||
#endif /* __DMAR_H__ */
|
||||
|
|
|
|||
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