RISC-V: KVM: Support firmware events
SBI PMU extension defines a set of firmware events which can provide useful information to guests about the number of SBI calls. As hypervisor implements the SBI PMU extension, these firmware events correspond to ecall invocations between VS->HS mode. All other firmware events will always report zero if monitored as KVM doesn't implement them. This patch adds all the infrastructure required to support firmware events. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Atish Patra
Anup Patel
Родитель
0cb74b65d2
Коммит
badc386869
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@ -18,6 +18,14 @@
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#define RISCV_KVM_MAX_COUNTERS (RISCV_KVM_MAX_HW_CTRS + RISCV_KVM_MAX_FW_CTRS)
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static_assert(RISCV_KVM_MAX_COUNTERS <= 64);
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struct kvm_fw_event {
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/* Current value of the event */
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unsigned long value;
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/* Event monitoring status */
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bool started;
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};
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/* Per virtual pmu counter data */
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struct kvm_pmc {
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u8 idx;
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@ -26,11 +34,14 @@ struct kvm_pmc {
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union sbi_pmu_ctr_info cinfo;
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/* Event monitoring status */
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bool started;
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/* Monitoring event ID */
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unsigned long event_idx;
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};
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/* PMU data structure per vcpu */
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struct kvm_pmu {
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struct kvm_pmc pmc[RISCV_KVM_MAX_COUNTERS];
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struct kvm_fw_event fw_event[RISCV_KVM_MAX_FW_CTRS];
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/* Number of the virtual firmware counters available */
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int num_fw_ctrs;
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/* Number of the virtual hardware counters available */
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@ -53,6 +64,7 @@ struct kvm_pmu {
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{.base = CSR_CYCLE, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm },
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#endif
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int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid);
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int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_num,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask);
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@ -84,6 +96,11 @@ struct kvm_pmu {
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{.base = 0, .count = 0, .func = NULL },
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static inline void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) {}
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static inline int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid)
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{
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return 0;
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}
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static inline void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) {}
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static inline void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) {}
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#endif /* CONFIG_RISCV_PMU_SBI */
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@ -202,12 +202,18 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *pmc;
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u64 enabled, running;
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int fevent_code;
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pmc = &kvpmu->pmc[cidx];
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if (!pmc->perf_event)
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return -EINVAL;
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pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
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if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
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fevent_code = get_event_code(pmc->event_idx);
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pmc->counter_val = kvpmu->fw_event[fevent_code].value;
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} else if (pmc->perf_event) {
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pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
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} else {
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return -EINVAL;
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}
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*out_val = pmc->counter_val;
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return 0;
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@ -223,6 +229,52 @@ static int kvm_pmu_validate_counter_mask(struct kvm_pmu *kvpmu, unsigned long ct
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return 0;
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}
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static int kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_event_attr *attr,
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unsigned long flags, unsigned long eidx, unsigned long evtdata)
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{
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struct perf_event *event;
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kvm_pmu_release_perf_event(pmc);
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attr->config = kvm_pmu_get_perf_event_config(eidx, evtdata);
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if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) {
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//TODO: Do we really want to clear the value in hardware counter
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pmc->counter_val = 0;
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}
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/*
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* Set the default sample_period for now. The guest specified value
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* will be updated in the start call.
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*/
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attr->sample_period = kvm_pmu_get_sample_period(pmc);
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event = perf_event_create_kernel_counter(attr, -1, current, NULL, pmc);
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if (IS_ERR(event)) {
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pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ERR(event));
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return PTR_ERR(event);
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}
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pmc->perf_event = event;
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if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
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perf_event_enable(pmc->perf_event);
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return 0;
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}
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int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid)
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{
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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struct kvm_fw_event *fevent;
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if (!kvpmu || fid >= SBI_PMU_FW_MAX)
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return -EINVAL;
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fevent = &kvpmu->fw_event[fid];
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if (fevent->started)
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fevent->value++;
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return 0;
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}
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int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_num,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask)
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@ -290,6 +342,7 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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int i, pmc_index, sbiret = 0;
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struct kvm_pmc *pmc;
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int fevent_code;
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if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) {
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sbiret = SBI_ERR_INVALID_PARAM;
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@ -304,7 +357,22 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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pmc = &kvpmu->pmc[pmc_index];
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if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE)
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pmc->counter_val = ival;
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if (pmc->perf_event) {
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if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
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fevent_code = get_event_code(pmc->event_idx);
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if (fevent_code >= SBI_PMU_FW_MAX) {
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sbiret = SBI_ERR_INVALID_PARAM;
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goto out;
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}
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/* Check if the counter was already started for some reason */
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if (kvpmu->fw_event[fevent_code].started) {
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sbiret = SBI_ERR_ALREADY_STARTED;
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continue;
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}
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kvpmu->fw_event[fevent_code].started = true;
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kvpmu->fw_event[fevent_code].value = pmc->counter_val;
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} else if (pmc->perf_event) {
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if (unlikely(pmc->started)) {
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sbiret = SBI_ERR_ALREADY_STARTED;
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continue;
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@ -331,6 +399,7 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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int i, pmc_index, sbiret = 0;
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u64 enabled, running;
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struct kvm_pmc *pmc;
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int fevent_code;
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if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) {
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sbiret = SBI_ERR_INVALID_PARAM;
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@ -343,7 +412,18 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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if (!test_bit(pmc_index, kvpmu->pmc_in_use))
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continue;
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pmc = &kvpmu->pmc[pmc_index];
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if (pmc->perf_event) {
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if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
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fevent_code = get_event_code(pmc->event_idx);
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if (fevent_code >= SBI_PMU_FW_MAX) {
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sbiret = SBI_ERR_INVALID_PARAM;
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goto out;
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}
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if (!kvpmu->fw_event[fevent_code].started)
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sbiret = SBI_ERR_ALREADY_STOPPED;
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kvpmu->fw_event[fevent_code].started = false;
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} else if (pmc->perf_event) {
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if (pmc->started) {
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/* Stop counting the counter */
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perf_event_disable(pmc->perf_event);
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@ -357,11 +437,14 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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pmc->counter_val += perf_event_read_value(pmc->perf_event,
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&enabled, &running);
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kvm_pmu_release_perf_event(pmc);
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clear_bit(pmc_index, kvpmu->pmc_in_use);
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}
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} else {
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sbiret = SBI_ERR_INVALID_PARAM;
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}
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if (flags & SBI_PMU_STOP_FLAG_RESET) {
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pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID;
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clear_bit(pmc_index, kvpmu->pmc_in_use);
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}
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}
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out:
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@ -375,12 +458,12 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba
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unsigned long eidx, u64 evtdata,
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struct kvm_vcpu_sbi_return *retdata)
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{
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int ctr_idx, sbiret = 0;
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u64 config;
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int ctr_idx, ret, sbiret = 0;
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bool is_fevent;
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unsigned long event_code;
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u32 etype = kvm_pmu_get_perf_event_type(eidx);
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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struct perf_event *event;
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struct kvm_pmc *pmc;
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struct kvm_pmc *pmc = NULL;
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struct perf_event_attr attr = {
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.type = etype,
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.size = sizeof(struct perf_event_attr),
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@ -401,7 +484,9 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba
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goto out;
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}
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if (kvm_pmu_is_fw_event(eidx)) {
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event_code = get_event_code(eidx);
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is_fevent = kvm_pmu_is_fw_event(eidx);
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if (is_fevent && event_code >= SBI_PMU_FW_MAX) {
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sbiret = SBI_ERR_NOT_SUPPORTED;
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goto out;
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}
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@ -425,33 +510,19 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba
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}
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pmc = &kvpmu->pmc[ctr_idx];
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kvm_pmu_release_perf_event(pmc);
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pmc->idx = ctr_idx;
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config = kvm_pmu_get_perf_event_config(eidx, evtdata);
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attr.config = config;
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if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) {
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//TODO: Do we really want to clear the value in hardware counter
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pmc->counter_val = 0;
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}
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/*
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* Set the default sample_period for now. The guest specified value
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* will be updated in the start call.
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*/
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attr.sample_period = kvm_pmu_get_sample_period(pmc);
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event = perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc);
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if (IS_ERR(event)) {
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pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ERR(event));
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return PTR_ERR(event);
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if (is_fevent) {
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if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
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kvpmu->fw_event[event_code].started = true;
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} else {
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ret = kvm_pmu_create_perf_event(pmc, &attr, flags, eidx, evtdata);
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if (ret)
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return ret;
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}
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set_bit(ctr_idx, kvpmu->pmc_in_use);
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pmc->perf_event = event;
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if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
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perf_event_enable(pmc->perf_event);
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pmc->event_idx = eidx;
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retdata->out_val = ctr_idx;
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out:
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retdata->err_val = sbiret;
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@ -494,6 +565,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu)
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*/
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kvpmu->num_hw_ctrs = num_hw_ctrs + 1;
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kvpmu->num_fw_ctrs = SBI_PMU_FW_MAX;
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memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event));
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if (kvpmu->num_hw_ctrs > RISCV_KVM_MAX_HW_CTRS) {
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pr_warn_once("Limiting the hardware counters to 32 as specified by the ISA");
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@ -512,6 +584,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu)
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continue;
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pmc = &kvpmu->pmc[i];
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pmc->idx = i;
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pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID;
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if (i < kvpmu->num_hw_ctrs) {
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pmc->cinfo.type = SBI_PMU_CTR_TYPE_HW;
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if (i < 3)
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@ -548,8 +621,10 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu)
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pmc = &kvpmu->pmc[i];
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pmc->counter_val = 0;
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kvm_pmu_release_perf_event(pmc);
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pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID;
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}
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bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS);
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memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event));
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}
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void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu)
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