ARM: dts: qcom: Add SDX65 platform and MTP board support
Add basic devicetree support for SDX65 platform and MTP board from Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. This commit adds basic devicetree support that includes GCC, RPMh clock, INTC and Debug UART. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
This commit is contained in:
Vamsi krishna Lanka
Bjorn Andersson
Родитель
3b338c9a6a
Коммит
bae2f5979c
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@ -987,7 +987,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-mdm9615-wp8548-mangoh-green.dtb \
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qcom-sdx55-mtp.dtb \
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qcom-sdx55-t55.dtb \
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qcom-sdx55-telit-fn980-tlb.dtb
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qcom-sdx55-telit-fn980-tlb.dtb \
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qcom-sdx65-mtp.dtb
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dtb-$(CONFIG_ARCH_RDA) += \
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rda8810pl-orangepi-2g-iot.dtb \
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rda8810pl-orangepi-i96.dtb
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@ -0,0 +1,25 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "qcom-sdx65.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDX65 MTP";
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compatible = "qcom,sdx65-mtp", "qcom,sdx65";
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qcom,board-id = <0x2010008 0x302>;
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aliases {
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serial0 = &blsp1_uart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&blsp1_uart3 {
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status = "ok";
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};
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@ -0,0 +1,210 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* SDX65 SoC device tree source
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*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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*/
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#include <dt-bindings/clock/qcom,gcc-sdx65.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
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interrupt-parent = <&intc>;
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memory {
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device_type = "memory";
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reg = <0 0>;
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32764>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved_memory: reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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cmd_db: reserved-memory@8fee0000 {
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compatible = "qcom,cmd-db";
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reg = <0x8fee0000 0x20000>;
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no-map;
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sdx65";
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reg = <0x00100000 0x001f7400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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blsp1_uart3: serial@831000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x00831000 0x200>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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pdc: interrupt-controller@b210000 {
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compatible = "qcom,sdx65-pdc", "qcom,pdc";
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reg = <0xb210000 0x10000>;
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qcom,pdc-ranges = <0 147 52>, <52 266 32>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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intc: interrupt-controller@17800000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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interrupt-parent = <&intc>;
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#interrupt-cells = <3>;
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reg = <0x17800000 0x1000>,
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<0x17802000 0x1000>;
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};
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timer@17820000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17820000 0x1000>;
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clock-frequency = <19200000>;
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frame@17821000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 7 0x4>,
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<GIC_SPI 6 0x4>;
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reg = <0x17821000 0x1000>,
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<0x17822000 0x1000>;
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};
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frame@17823000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 8 0x4>;
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reg = <0x17823000 0x1000>;
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status = "disabled";
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};
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frame@17824000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 9 0x4>;
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reg = <0x17824000 0x1000>;
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status = "disabled";
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};
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frame@17825000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 10 0x4>;
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reg = <0x17825000 0x1000>;
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status = "disabled";
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};
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frame@17826000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 11 0x4>;
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reg = <0x17826000 0x1000>;
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status = "disabled";
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};
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frame@17827000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 12 0x4>;
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reg = <0x17827000 0x1000>;
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status = "disabled";
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};
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frame@17828000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 13 0x4>;
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reg = <0x17828000 0x1000>;
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status = "disabled";
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};
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frame@17829000 {
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frame-number = <7>;
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interrupts = <GIC_SPI 14 0x4>;
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reg = <0x17829000 0x1000>;
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status = "disabled";
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};
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};
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apps_rsc: rsc@17830000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x17830000 0x10000>,
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<0x17840000 0x10000>;
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reg-names = "drv-0", "drv-1";
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <1>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 2>,
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<WAKE_TCS 2>,
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<CONTROL_TCS 1>;
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rpmhcc: clock-controller@1 {
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compatible = "qcom,sdx65-rpmh-clk";
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#clock-cells = <1>;
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clock-names = "xo";
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clocks = <&xo_board>;
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 12 0xf08>,
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<1 10 0xf08>,
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<1 11 0xf08>;
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clock-frequency = <19200000>;
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};
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};
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