mips: dts: ralink: mt7621: add port@5 as CPU port
On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is connected to the second MAC of the SoC as a CPU port. Add the port and set up the second MAC on the bindings. Revert PHY muxing on GB-PC1. There's an external PHY connected to the second MAC of the SoC on GB-PC2, therefore, disable port@5 for this device. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -91,22 +91,16 @@
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status = "okay";
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};
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&gmac1 {
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status = "okay";
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phy-handle = <ðphy4>;
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};
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&mdio {
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ethphy4: ethernet-phy@4 {
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reg = <4>;
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};
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};
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&switch0 {
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ports {
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port@0 {
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status = "okay";
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label = "ethblack";
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};
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port@4 {
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status = "okay";
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label = "ethblue";
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};
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};
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};
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@ -112,9 +112,12 @@
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};
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii-rxid";
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phy-handle = <ðphy5>;
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fixed-link {
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status = "disabled";
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};
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};
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&mdio {
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@ -134,5 +137,9 @@
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status = "okay";
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label = "ethblue";
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};
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port@5 {
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status = "disabled";
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};
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};
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};
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@ -332,8 +332,13 @@
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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status = "disabled";
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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mdio: mdio-bus {
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@ -384,6 +389,18 @@
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label = "swp4";
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};
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port@5 {
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reg = <5>;
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ethernet = <&gmac1>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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