tg3: Add RSS support
This patch adds code needed to enable RSS. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
Родитель
b6080e1260
Коммит
baf8a94a57
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@ -102,6 +102,7 @@
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#define TG3_DEF_RX_RING_PENDING 200
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#define TG3_RX_JUMBO_RING_SIZE 256
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#define TG3_DEF_RX_JUMBO_RING_PENDING 100
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#define TG3_RSS_INDIR_TBL_SIZE 128
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/* Do not place this n-ring entries value into the tp struct itself,
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* we really want to expose these constants to GCC so that modulo et
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@ -7497,6 +7498,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
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udelay(100);
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
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val = tr32(MSGINT_MODE);
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val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
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tw32(MSGINT_MODE, val);
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}
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
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udelay(40);
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@ -7565,7 +7572,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
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tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
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tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
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val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
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val |= SNDBDI_MODE_MULTI_TXQ_EN;
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tw32(SNDBDI_MODE, val);
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tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
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@ -7584,10 +7594,46 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32_f(MAC_TX_MODE, tp->tx_mode);
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udelay(100);
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if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
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u32 reg = MAC_RSS_INDIR_TBL_0;
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u8 *ent = (u8 *)&val;
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/* Setup the indirection table */
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for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
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int idx = i % sizeof(val);
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ent[idx] = i % (tp->irq_cnt - 1);
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if (idx == sizeof(val) - 1) {
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tw32(reg, val);
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reg += 4;
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}
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}
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/* Setup the "secret" hash key. */
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tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
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tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
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tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
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tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
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tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
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tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
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tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
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tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
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tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
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tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
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}
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tp->rx_mode = RX_MODE_ENABLE;
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if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
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tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
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if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
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tp->rx_mode |= RX_MODE_RSS_ENABLE |
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RX_MODE_RSS_ITBL_HASH_BITS_7 |
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RX_MODE_RSS_IPV6_HASH_EN |
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RX_MODE_RSS_TCP_IPV6_HASH_EN |
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RX_MODE_RSS_IPV4_HASH_EN |
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RX_MODE_RSS_TCP_IPV4_HASH_EN;
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tw32_f(MAC_RX_MODE, tp->rx_mode);
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udelay(10);
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@ -8112,6 +8158,8 @@ static bool tg3_enable_msix(struct tg3 *tp)
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tp->irq_cnt = rc;
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}
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tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
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for (i = 0; i < tp->irq_max; i++)
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tp->napi[i].irq_vec = msix_ent[i].vector;
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@ -8140,6 +8188,8 @@ static void tg3_ints_init(struct tg3 *tp)
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
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u32 msi_mode = tr32(MSGINT_MODE);
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
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msi_mode |= MSGINT_MODE_MULTIVEC_EN;
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tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
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}
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defcfg:
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@ -8157,6 +8207,7 @@ static void tg3_ints_fini(struct tg3 *tp)
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else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
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pci_disable_msi(tp->pdev);
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tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
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tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
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}
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static int tg3_open(struct net_device *dev)
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@ -446,6 +446,12 @@
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#define RX_MODE_PROMISC 0x00000100
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#define RX_MODE_NO_CRC_CHECK 0x00000200
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#define RX_MODE_KEEP_VLAN_TAG 0x00000400
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#define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
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#define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
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#define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
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#define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
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#define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
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#define RX_MODE_RSS_ENABLE 0x00800000
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#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
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#define MAC_RX_STATUS 0x0000046c
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#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
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@ -690,7 +696,22 @@
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/* 0x5b8 --> 0x600 unused */
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#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
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#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
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/* 0x624 --> 0x800 unused */
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/* 0x624 --> 0x670 unused */
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#define MAC_RSS_INDIR_TBL_0 0x00000630
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#define MAC_RSS_HASH_KEY_0 0x00000670
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#define MAC_RSS_HASH_KEY_1 0x00000674
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#define MAC_RSS_HASH_KEY_2 0x00000678
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#define MAC_RSS_HASH_KEY_3 0x0000067c
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#define MAC_RSS_HASH_KEY_4 0x00000680
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#define MAC_RSS_HASH_KEY_5 0x00000684
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#define MAC_RSS_HASH_KEY_6 0x00000688
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#define MAC_RSS_HASH_KEY_7 0x0000068c
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#define MAC_RSS_HASH_KEY_8 0x00000690
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#define MAC_RSS_HASH_KEY_9 0x00000694
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/* 0x698 --> 0x800 unused */
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#define MAC_TX_STATS_OCTETS 0x00000800
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#define MAC_TX_STATS_RESV1 0x00000804
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#define MAC_TX_STATS_COLLISIONS 0x00000808
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@ -1465,6 +1486,7 @@
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#define MSGINT_MODE 0x00006000
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#define MSGINT_MODE_RESET 0x00000001
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#define MSGINT_MODE_ENABLE 0x00000002
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#define MSGINT_MODE_MULTIVEC_EN 0x00000080
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#define MSGINT_STATUS 0x00006004
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#define MSGINT_FIFO 0x00006008
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/* 0x600c --> 0x6400 unused */
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@ -2704,6 +2726,7 @@ struct tg3 {
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#define TG3_FLG3_NO_NVRAM 0x00004000
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#define TG3_FLG3_TOGGLE_10_100_L1PLLPD 0x00008000
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#define TG3_FLG3_PHY_IS_FET 0x00010000
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#define TG3_FLG3_ENABLE_RSS 0x00020000
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struct timer_list timer;
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u16 timer_counter;
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