drm/i915/xelpd: Add VRR guardband for VRR CTL
On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield replacing the pipeline full and deprecating the pipeline override bit. This patch adds this corresponding bitfield in the register defs, crtc state vrr structure and populates this in vrr compute config and vrr enable functions. It also adds the corresponding HW state readout for this field. Bspec: 50508 Cc: Aditya Swarup <aditya.swarup@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Aditya Swarup <aditya.swarup@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210526000656.3060314-3-matthew.d.roper@intel.com
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@ -7654,10 +7654,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
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intel_hdmi_infoframe_enable(DP_SDP_VSC))
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intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
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drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
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drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
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yesno(pipe_config->vrr.enable),
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pipe_config->vrr.vmin, pipe_config->vrr.vmax,
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pipe_config->vrr.pipeline_full, pipe_config->vrr.flipline,
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pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
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pipe_config->vrr.flipline,
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intel_vrr_vmin_vblank_start(pipe_config),
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intel_vrr_vmax_vblank_start(pipe_config));
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@ -8663,6 +8664,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
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PIPE_CONF_CHECK_I(vrr.vmax);
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PIPE_CONF_CHECK_I(vrr.flipline);
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PIPE_CONF_CHECK_I(vrr.pipeline_full);
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PIPE_CONF_CHECK_I(vrr.guardband);
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PIPE_CONF_CHECK_BOOL(has_psr);
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PIPE_CONF_CHECK_BOOL(has_psr2);
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@ -12256,6 +12258,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
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i915->framestart_delay = 1; /* 1-4 */
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i915->window2_delay = 0; /* No DSB so no window2 delay */
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intel_mode_config_init(i915);
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ret = intel_cdclk_init(i915);
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@ -1202,7 +1202,7 @@ struct intel_crtc_state {
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struct {
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bool enable;
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u8 pipeline_full;
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u16 flipline, vmin, vmax;
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u16 flipline, vmin, vmax, guardband;
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} vrr;
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/* Stream Splitter for eDP MSO */
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@ -68,6 +68,9 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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/* The hw imposes the extra scanline before frame start */
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if (DISPLAY_VER(i915) >= 13)
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return crtc_state->vrr.guardband + i915->framestart_delay + 1;
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else
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return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
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}
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@ -86,6 +89,8 @@ void
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intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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struct intel_connector *connector =
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to_intel_connector(conn_state->connector);
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struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
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@ -123,6 +128,15 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
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crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
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/*
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* For XE_LPD+, we use guardband and pipeline override
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* is deprecated.
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*/
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if (DISPLAY_VER(i915) >= 13)
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crtc_state->vrr.guardband =
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crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
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i915->window2_delay;
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else
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/*
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* FIXME: s/4/framestart_delay+1/ to get consistent
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* earliest/latest points for register latching regardless
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@ -149,6 +163,11 @@ void intel_vrr_enable(struct intel_encoder *encoder,
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if (!crtc_state->vrr.enable)
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return;
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if (DISPLAY_VER(dev_priv) >= 13)
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trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
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VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
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XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
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else
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trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
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VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
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VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
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@ -199,8 +218,13 @@ void intel_vrr_get_config(struct intel_crtc *crtc,
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if (!crtc_state->vrr.enable)
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return;
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if (DISPLAY_VER(dev_priv) >= 13)
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crtc_state->vrr.guardband =
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REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
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else
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if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
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crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
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crtc_state->vrr.pipeline_full =
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REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
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if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
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crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
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crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
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@ -1133,6 +1133,9 @@ struct drm_i915_private {
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u8 framestart_delay;
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/* Window2 specifies time required to program DSB (Window2) in number of scan lines */
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u8 window2_delay;
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u8 pch_ssc_use;
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/* For i915gm/i945gm vblank irq workaround */
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@ -4379,6 +4379,8 @@ enum {
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#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
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#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
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#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
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#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
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#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
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#define _TRANS_VRR_VMAX_A 0x60424
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#define _TRANS_VRR_VMAX_B 0x61424
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