OMAPDSS: move blocking mgr enable/disable to compat layer
dispc_mgr_enable_sync and dispc_mgr_disable_sync are only used with the compat mode. Non-compat will use the simpler enable and disable functions. This patch moves the synchronous enable/disable code to the compat layer. A new file is created, dispc-compat.c, which contains low level dispc compat code (versus apply.c, which contains slightly higher level compat code). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen
Родитель
1550202d4a
Коммит
bb39813413
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@ -1,7 +1,7 @@
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obj-$(CONFIG_OMAP2_DSS) += omapdss.o
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omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \
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manager.o manager-sysfs.o overlay.o overlay-sysfs.o output.o apply.o \
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display-sysfs.o
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display-sysfs.o dispc-compat.o
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omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o
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omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
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omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o venc_panel.o
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@ -27,6 +27,7 @@
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#include "dss.h"
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#include "dss_features.h"
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#include "dispc-compat.h"
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/*
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* We have 4 levels of cache for the dispc settings. First two are in SW and
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@ -0,0 +1,207 @@
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/*
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* Copyright (C) 2012 Texas Instruments
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "APPLY"
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/jiffies.h>
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#include <linux/delay.h>
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#include <video/omapdss.h>
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#include "dss.h"
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#include "dss_features.h"
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#include "dispc-compat.h"
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static void dispc_mgr_disable_isr(void *data, u32 mask)
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{
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struct completion *compl = data;
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complete(compl);
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}
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static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
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{
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dispc_mgr_enable(channel, true);
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}
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static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
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{
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DECLARE_COMPLETION_ONSTACK(framedone_compl);
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int r;
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u32 irq;
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if (dispc_mgr_is_enabled(channel) == false)
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return;
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/*
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* When we disable LCD output, we need to wait for FRAMEDONE to know
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* that DISPC has finished with the LCD output.
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*/
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irq = dispc_mgr_get_framedone_irq(channel);
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r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq);
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if (r)
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DSSERR("failed to register FRAMEDONE isr\n");
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dispc_mgr_enable(channel, false);
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/* if we couldn't register for framedone, just sleep and exit */
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if (r) {
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msleep(100);
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return;
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}
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if (!wait_for_completion_timeout(&framedone_compl,
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msecs_to_jiffies(100)))
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DSSERR("timeout waiting for FRAME DONE\n");
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r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq);
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if (r)
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DSSERR("failed to unregister FRAMEDONE isr\n");
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}
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static void dispc_digit_out_enable_isr(void *data, u32 mask)
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{
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struct completion *compl = data;
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/* ignore any sync lost interrupts */
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if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
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complete(compl);
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}
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static void dispc_mgr_enable_digit_out(void)
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{
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DECLARE_COMPLETION_ONSTACK(vsync_compl);
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int r;
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u32 irq_mask;
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if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == true)
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return;
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/*
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* Digit output produces some sync lost interrupts during the first
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* frame when enabling. Those need to be ignored, so we register for the
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* sync lost irq to prevent the error handler from triggering.
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*/
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irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
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dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
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r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
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irq_mask);
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if (r) {
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DSSERR("failed to register %x isr\n", irq_mask);
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return;
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}
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dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, true);
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/* wait for the first evsync */
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if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
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DSSERR("timeout waiting for digit out to start\n");
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r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
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irq_mask);
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if (r)
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DSSERR("failed to unregister %x isr\n", irq_mask);
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}
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static void dispc_mgr_disable_digit_out(void)
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{
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DECLARE_COMPLETION_ONSTACK(framedone_compl);
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int r, i;
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u32 irq_mask;
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int num_irqs;
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if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == false)
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return;
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/*
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* When we disable the digit output, we need to wait for FRAMEDONE to
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* know that DISPC has finished with the output.
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*/
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irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
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num_irqs = 1;
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if (!irq_mask) {
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/*
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* omap 2/3 don't have framedone irq for TV, so we need to use
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* vsyncs for this.
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*/
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irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
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/*
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* We need to wait for both even and odd vsyncs. Note that this
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* is not totally reliable, as we could get a vsync interrupt
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* before we disable the output, which leads to timeout in the
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* wait_for_completion.
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*/
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num_irqs = 2;
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}
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r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq_mask);
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if (r)
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DSSERR("failed to register %x isr\n", irq_mask);
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dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, false);
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/* if we couldn't register the irq, just sleep and exit */
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if (r) {
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msleep(100);
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return;
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}
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for (i = 0; i < num_irqs; ++i) {
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if (!wait_for_completion_timeout(&framedone_compl,
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msecs_to_jiffies(100)))
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DSSERR("timeout waiting for digit out to stop\n");
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}
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r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq_mask);
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if (r)
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DSSERR("failed to unregister %x isr\n", irq_mask);
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}
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void dispc_mgr_enable_sync(enum omap_channel channel)
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{
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if (dss_mgr_is_lcd(channel))
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dispc_mgr_enable_lcd_out(channel);
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else if (channel == OMAP_DSS_CHANNEL_DIGIT)
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dispc_mgr_enable_digit_out();
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else
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WARN_ON(1);
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}
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void dispc_mgr_disable_sync(enum omap_channel channel)
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{
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if (dss_mgr_is_lcd(channel))
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dispc_mgr_disable_lcd_out(channel);
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else if (channel == OMAP_DSS_CHANNEL_DIGIT)
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dispc_mgr_disable_digit_out();
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else
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WARN_ON(1);
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}
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@ -0,0 +1,24 @@
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/*
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* Copyright (C) 2012 Texas Instruments
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __OMAP2_DSS_DISPC_COMPAT_H
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#define __OMAP2_DSS_DISPC_COMPAT_H
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void dispc_mgr_enable_sync(enum omap_channel channel);
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void dispc_mgr_disable_sync(enum omap_channel channel);
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#endif
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@ -2599,12 +2599,6 @@ bool dispc_ovl_enabled(enum omap_plane plane)
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return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
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}
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static void dispc_mgr_disable_isr(void *data, u32 mask)
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{
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struct completion *compl = data;
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complete(compl);
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}
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void dispc_mgr_enable(enum omap_channel channel, bool enable)
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{
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mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
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@ -2617,175 +2611,6 @@ bool dispc_mgr_is_enabled(enum omap_channel channel)
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return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
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}
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static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
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{
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dispc_mgr_enable(channel, true);
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}
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static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
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{
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DECLARE_COMPLETION_ONSTACK(framedone_compl);
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int r;
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u32 irq;
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if (dispc_mgr_is_enabled(channel) == false)
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return;
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/*
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* When we disable LCD output, we need to wait for FRAMEDONE to know
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* that DISPC has finished with the LCD output.
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*/
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irq = dispc_mgr_get_framedone_irq(channel);
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r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq);
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if (r)
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DSSERR("failed to register FRAMEDONE isr\n");
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dispc_mgr_enable(channel, false);
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/* if we couldn't register for framedone, just sleep and exit */
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if (r) {
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msleep(100);
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return;
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}
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if (!wait_for_completion_timeout(&framedone_compl,
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msecs_to_jiffies(100)))
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DSSERR("timeout waiting for FRAME DONE\n");
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r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq);
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if (r)
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DSSERR("failed to unregister FRAMEDONE isr\n");
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}
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static void dispc_digit_out_enable_isr(void *data, u32 mask)
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{
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struct completion *compl = data;
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/* ignore any sync lost interrupts */
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if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
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complete(compl);
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}
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static void dispc_mgr_enable_digit_out(void)
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{
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DECLARE_COMPLETION_ONSTACK(vsync_compl);
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int r;
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u32 irq_mask;
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if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == true)
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return;
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/*
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* Digit output produces some sync lost interrupts during the first
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* frame when enabling. Those need to be ignored, so we register for the
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* sync lost irq to prevent the error handler from triggering.
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*/
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irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
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dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
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r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
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irq_mask);
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if (r) {
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DSSERR("failed to register %x isr\n", irq_mask);
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return;
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}
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dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, true);
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/* wait for the first evsync */
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if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
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DSSERR("timeout waiting for digit out to start\n");
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r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
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irq_mask);
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if (r)
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DSSERR("failed to unregister %x isr\n", irq_mask);
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}
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static void dispc_mgr_disable_digit_out(void)
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{
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DECLARE_COMPLETION_ONSTACK(framedone_compl);
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int r, i;
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u32 irq_mask;
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int num_irqs;
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if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == false)
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return;
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/*
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* When we disable the digit output, we need to wait for FRAMEDONE to
|
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* know that DISPC has finished with the output.
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*/
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irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
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num_irqs = 1;
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if (!irq_mask) {
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/*
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* omap 2/3 don't have framedone irq for TV, so we need to use
|
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* vsyncs for this.
|
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*/
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irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
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/*
|
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* We need to wait for both even and odd vsyncs. Note that this
|
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* is not totally reliable, as we could get a vsync interrupt
|
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* before we disable the output, which leads to timeout in the
|
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* wait_for_completion.
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*/
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num_irqs = 2;
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}
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r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq_mask);
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if (r)
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DSSERR("failed to register %x isr\n", irq_mask);
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dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, false);
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/* if we couldn't register the irq, just sleep and exit */
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if (r) {
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msleep(100);
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return;
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}
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for (i = 0; i < num_irqs; ++i) {
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if (!wait_for_completion_timeout(&framedone_compl,
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msecs_to_jiffies(100)))
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DSSERR("timeout waiting for digit out to stop\n");
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}
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r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq_mask);
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if (r)
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DSSERR("failed to unregister %x isr\n", irq_mask);
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}
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void dispc_mgr_enable_sync(enum omap_channel channel)
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{
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if (dss_mgr_is_lcd(channel))
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dispc_mgr_enable_lcd_out(channel);
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else if (channel == OMAP_DSS_CHANNEL_DIGIT)
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dispc_mgr_enable_digit_out();
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else
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WARN_ON(1);
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}
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void dispc_mgr_disable_sync(enum omap_channel channel)
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{
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if (dss_mgr_is_lcd(channel))
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dispc_mgr_disable_lcd_out(channel);
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else if (channel == OMAP_DSS_CHANNEL_DIGIT)
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dispc_mgr_disable_digit_out();
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else
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WARN_ON(1);
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}
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void dispc_wb_enable(bool enable)
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{
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dispc_ovl_enable(OMAP_DSS_WB, enable);
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|
|
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|
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@ -426,8 +426,6 @@ bool dispc_mgr_go_busy(enum omap_channel channel);
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void dispc_mgr_go(enum omap_channel channel);
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void dispc_mgr_enable(enum omap_channel channel, bool enable);
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bool dispc_mgr_is_enabled(enum omap_channel channel);
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void dispc_mgr_enable_sync(enum omap_channel channel);
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void dispc_mgr_disable_sync(enum omap_channel channel);
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void dispc_mgr_set_lcd_config(enum omap_channel channel,
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const struct dss_lcd_mgr_config *config);
|
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void dispc_mgr_set_timings(enum omap_channel channel,
|
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|
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Загрузка…
Ссылка в новой задаче