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drm/nv84-/fence: abstract class emit/sync functions to virt+sequence 

Now can be used to operate on any buffer mapped into the GPU virtual
address and not just the main inter-channel sync buffer.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2013-02-14 09:37:35 +10:00
Родитель a34caf78f2
Коммит bba9852fee
3 изменённых файлов: 53 добавлений и 50 удалений
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5
drivers/gpu/drm/nouveau/nouveau_fence.h
Просмотреть файл

@ -39,7 +39,9 @@ struct nouveau_fence_priv {
void (*resume)(struct nouveau_drm *); void (*resume)(struct nouveau_drm *);
int (*context_new)(struct nouveau_channel *); int (*context_new)(struct nouveau_channel *);
void (*context_del)(struct nouveau_channel *); void (*context_del)(struct nouveau_channel *);
int (*emit32)(struct nouveau_channel *, u64, u32);
int (*emit)(struct nouveau_fence *); int (*emit)(struct nouveau_fence *);
int (*sync32)(struct nouveau_channel *, u64, u32);
int (*sync)(struct nouveau_fence *, struct nouveau_channel *, int (*sync)(struct nouveau_fence *, struct nouveau_channel *,
struct nouveau_channel *); struct nouveau_channel *);
u32 (*read)(struct nouveau_channel *); u32 (*read)(struct nouveau_channel *);
@ -84,6 +86,9 @@ struct nv84_fence_priv {
}; };
u64 nv84_fence_crtc(struct nouveau_channel *, int); u64 nv84_fence_crtc(struct nouveau_channel *, int);
int nv84_fence_emit(struct nouveau_fence *);
int nv84_fence_sync(struct nouveau_fence *, struct nouveau_channel *,
struct nouveau_channel *);
u32 nv84_fence_read(struct nouveau_channel *); u32 nv84_fence_read(struct nouveau_channel *);
int nv84_fence_context_new(struct nouveau_channel *); int nv84_fence_context_new(struct nouveau_channel *);
void nv84_fence_context_del(struct nouveau_channel *); void nv84_fence_context_del(struct nouveau_channel *);

58
drivers/gpu/drm/nouveau/nv84_fence.c
Просмотреть файл

@ -42,54 +42,62 @@ nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
} }
static int static int
nv84_fence_emit(struct nouveau_fence *fence) nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{ {
struct nouveau_channel *chan = fence->channel; int ret = RING_SPACE(chan, 8);
struct nv84_fence_chan *fctx = chan->fence;
struct nouveau_fifo_chan *fifo = (void *)chan->object;
u64 addr = fctx->vma.offset + fifo->chid * 16;
int ret;
ret = RING_SPACE(chan, 8);
if (ret == 0) { if (ret == 0) {
BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
OUT_RING (chan, chan->vram); OUT_RING (chan, chan->vram);
BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
OUT_RING (chan, upper_32_bits(addr)); OUT_RING (chan, upper_32_bits(virtual));
OUT_RING (chan, lower_32_bits(addr)); OUT_RING (chan, lower_32_bits(virtual));
OUT_RING (chan, fence->sequence); OUT_RING (chan, sequence);
OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
OUT_RING (chan, 0x00000000); OUT_RING (chan, 0x00000000);
FIRE_RING (chan); FIRE_RING (chan);
} }
return ret; return ret;
} }
static int static int
nv84_fence_sync(struct nouveau_fence *fence, nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
struct nouveau_channel *prev, struct nouveau_channel *chan)
{ {
struct nv84_fence_chan *fctx = chan->fence; int ret = RING_SPACE(chan, 7);
struct nouveau_fifo_chan *fifo = (void *)prev->object;
u64 addr = fctx->vma.offset + fifo->chid * 16;
int ret;
ret = RING_SPACE(chan, 7);
if (ret == 0) { if (ret == 0) {
BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
OUT_RING (chan, chan->vram); OUT_RING (chan, chan->vram);
BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
OUT_RING (chan, upper_32_bits(addr)); OUT_RING (chan, upper_32_bits(virtual));
OUT_RING (chan, lower_32_bits(addr)); OUT_RING (chan, lower_32_bits(virtual));
OUT_RING (chan, fence->sequence); OUT_RING (chan, sequence);
OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
FIRE_RING (chan); FIRE_RING (chan);
} }
return ret; return ret;
} }
int
nv84_fence_emit(struct nouveau_fence *fence)
{
struct nouveau_channel *chan = fence->channel;
struct nv84_fence_priv *priv = chan->drm->fence;
struct nv84_fence_chan *fctx = chan->fence;
struct nouveau_fifo_chan *fifo = (void *)chan->object;
u64 addr = fctx->vma.offset + fifo->chid * 16;
return priv->base.emit32(chan, addr, fence->sequence);
}
int
nv84_fence_sync(struct nouveau_fence *fence,
struct nouveau_channel *prev, struct nouveau_channel *chan)
{
struct nv84_fence_priv *priv = chan->drm->fence;
struct nv84_fence_chan *fctx = chan->fence;
struct nouveau_fifo_chan *fifo = (void *)prev->object;
u64 addr = fctx->vma.offset + fifo->chid * 16;
return priv->base.sync32(chan, addr, fence->sequence);
}
u32 u32
nv84_fence_read(struct nouveau_channel *chan) nv84_fence_read(struct nouveau_channel *chan)
{ {
@ -205,7 +213,9 @@ nv84_fence_create(struct nouveau_drm *drm)
priv->base.resume = nv84_fence_resume; priv->base.resume = nv84_fence_resume;
priv->base.context_new = nv84_fence_context_new; priv->base.context_new = nv84_fence_context_new;
priv->base.context_del = nv84_fence_context_del; priv->base.context_del = nv84_fence_context_del;
priv->base.emit32 = nv84_fence_emit32;
priv->base.emit = nv84_fence_emit; priv->base.emit = nv84_fence_emit;
priv->base.sync32 = nv84_fence_sync32;
priv->base.sync = nv84_fence_sync; priv->base.sync = nv84_fence_sync;
priv->base.read = nv84_fence_read; priv->base.read = nv84_fence_read;

40
drivers/gpu/drm/nouveau/nvc0_fence.c
Просмотреть файл

@ -35,48 +35,34 @@
#include "nv50_display.h" #include "nv50_display.h"
static int static int
nvc0_fence_emit(struct nouveau_fence *fence) nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{ {
struct nouveau_channel *chan = fence->channel; int ret = RING_SPACE(chan, 6);
struct nv84_fence_chan *fctx = chan->fence;
struct nouveau_fifo_chan *fifo = (void *)chan->object;
u64 addr = fctx->vma.offset + fifo->chid * 16;
int ret;
ret = RING_SPACE(chan, 6);
if (ret == 0) { if (ret == 0) {
BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
OUT_RING (chan, upper_32_bits(addr)); OUT_RING (chan, upper_32_bits(virtual));
OUT_RING (chan, lower_32_bits(addr)); OUT_RING (chan, lower_32_bits(virtual));
OUT_RING (chan, fence->sequence); OUT_RING (chan, sequence);
OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
OUT_RING (chan, 0x00000000); OUT_RING (chan, 0x00000000);
FIRE_RING (chan); FIRE_RING (chan);
} }
return ret; return ret;
} }
static int static int
nvc0_fence_sync(struct nouveau_fence *fence, nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
struct nouveau_channel *prev, struct nouveau_channel *chan)
{ {
struct nv84_fence_chan *fctx = chan->fence; int ret = RING_SPACE(chan, 5);
struct nouveau_fifo_chan *fifo = (void *)prev->object;
u64 addr = fctx->vma.offset + fifo->chid * 16;
int ret;
ret = RING_SPACE(chan, 5);
if (ret == 0) { if (ret == 0) {
BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
OUT_RING (chan, upper_32_bits(addr)); OUT_RING (chan, upper_32_bits(virtual));
OUT_RING (chan, lower_32_bits(addr)); OUT_RING (chan, lower_32_bits(virtual));
OUT_RING (chan, fence->sequence); OUT_RING (chan, sequence);
OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
FIRE_RING (chan); FIRE_RING (chan);
} }
return ret; return ret;
} }
@ -96,8 +82,10 @@ nvc0_fence_create(struct nouveau_drm *drm)
priv->base.resume = nv84_fence_resume; priv->base.resume = nv84_fence_resume;
priv->base.context_new = nv84_fence_context_new; priv->base.context_new = nv84_fence_context_new;
priv->base.context_del = nv84_fence_context_del; priv->base.context_del = nv84_fence_context_del;
priv->base.emit = nvc0_fence_emit; priv->base.emit32 = nvc0_fence_emit32;
priv->base.sync = nvc0_fence_sync; priv->base.emit = nv84_fence_emit;
priv->base.sync32 = nvc0_fence_sync32;
priv->base.sync = nv84_fence_sync;
priv->base.read = nv84_fence_read; priv->base.read = nv84_fence_read;
init_waitqueue_head(&priv->base.waiting); init_waitqueue_head(&priv->base.waiting);