media: camss: Use optimal clock frequency rates
Use standard V4L2 control to get pixel clock rate from a sensor linked in the media controller pipeline. Then calculate clock rates on CSIPHY, CSID and VFE to use the lowest possible. If the currnet pixel clock rate of the sensor cannot be read then use the highest possible. This case covers also the CSID test generator usage. If VFE is already powered on by another pipeline, check that the current VFE clock rate is high enough for the new pipeline. If not return busy error code as VFE clock rate cannot be changed while VFE is running. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Todor Tomov
Mauro Carvalho Chehab
Родитель
474a53d645
Коммит
bbde310474
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@ -69,6 +69,7 @@ struct csid_fmts {
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u8 data_type;
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u8 decode_format;
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u8 bpp;
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u8 spp; /* bus samples per pixel */
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};
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static const struct csid_fmts csid_input_fmts[] = {
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@ -76,97 +77,113 @@ static const struct csid_fmts csid_input_fmts[] = {
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MEDIA_BUS_FMT_UYVY8_2X8,
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DATA_TYPE_YUV422_8BIT,
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DECODE_FORMAT_UNCOMPRESSED_8_BIT,
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16,
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8,
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2,
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},
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{
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MEDIA_BUS_FMT_VYUY8_2X8,
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DATA_TYPE_YUV422_8BIT,
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DECODE_FORMAT_UNCOMPRESSED_8_BIT,
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16,
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8,
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2,
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},
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{
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MEDIA_BUS_FMT_YUYV8_2X8,
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DATA_TYPE_YUV422_8BIT,
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DECODE_FORMAT_UNCOMPRESSED_8_BIT,
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16,
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8,
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2,
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},
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{
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MEDIA_BUS_FMT_YVYU8_2X8,
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DATA_TYPE_YUV422_8BIT,
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DECODE_FORMAT_UNCOMPRESSED_8_BIT,
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16,
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8,
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2,
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},
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{
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MEDIA_BUS_FMT_SBGGR8_1X8,
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DATA_TYPE_RAW_8BIT,
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DECODE_FORMAT_UNCOMPRESSED_8_BIT,
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8,
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1,
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},
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{
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MEDIA_BUS_FMT_SGBRG8_1X8,
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DATA_TYPE_RAW_8BIT,
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DECODE_FORMAT_UNCOMPRESSED_8_BIT,
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8,
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1,
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},
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{
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MEDIA_BUS_FMT_SGRBG8_1X8,
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DATA_TYPE_RAW_8BIT,
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DECODE_FORMAT_UNCOMPRESSED_8_BIT,
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8,
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1,
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},
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{
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MEDIA_BUS_FMT_SRGGB8_1X8,
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DATA_TYPE_RAW_8BIT,
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DECODE_FORMAT_UNCOMPRESSED_8_BIT,
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8,
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1,
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},
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{
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MEDIA_BUS_FMT_SBGGR10_1X10,
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DATA_TYPE_RAW_10BIT,
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DECODE_FORMAT_UNCOMPRESSED_10_BIT,
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10,
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1,
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},
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{
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MEDIA_BUS_FMT_SGBRG10_1X10,
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DATA_TYPE_RAW_10BIT,
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DECODE_FORMAT_UNCOMPRESSED_10_BIT,
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10,
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1,
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},
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{
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MEDIA_BUS_FMT_SGRBG10_1X10,
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DATA_TYPE_RAW_10BIT,
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DECODE_FORMAT_UNCOMPRESSED_10_BIT,
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10,
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1,
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},
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{
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MEDIA_BUS_FMT_SRGGB10_1X10,
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DATA_TYPE_RAW_10BIT,
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DECODE_FORMAT_UNCOMPRESSED_10_BIT,
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10,
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1,
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},
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{
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MEDIA_BUS_FMT_SBGGR12_1X12,
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DATA_TYPE_RAW_12BIT,
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DECODE_FORMAT_UNCOMPRESSED_12_BIT,
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12,
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1,
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},
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{
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MEDIA_BUS_FMT_SGBRG12_1X12,
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DATA_TYPE_RAW_12BIT,
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DECODE_FORMAT_UNCOMPRESSED_12_BIT,
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12,
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1,
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},
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{
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MEDIA_BUS_FMT_SGRBG12_1X12,
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DATA_TYPE_RAW_12BIT,
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DECODE_FORMAT_UNCOMPRESSED_12_BIT,
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12,
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1,
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},
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{
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MEDIA_BUS_FMT_SRGGB12_1X12,
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DATA_TYPE_RAW_12BIT,
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DECODE_FORMAT_UNCOMPRESSED_12_BIT,
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12,
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1,
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}
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};
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@ -204,6 +221,67 @@ static irqreturn_t csid_isr(int irq, void *dev)
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return IRQ_HANDLED;
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}
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/*
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* csid_set_clock_rates - Calculate and set clock rates on CSID module
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* @csiphy: CSID device
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*/
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static int csid_set_clock_rates(struct csid_device *csid)
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{
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struct device *dev = to_device_index(csid, csid->id);
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u32 pixel_clock;
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int i, j;
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int ret;
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ret = camss_get_pixel_clock(&csid->subdev.entity, &pixel_clock);
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if (ret)
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pixel_clock = 0;
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for (i = 0; i < csid->nclocks; i++) {
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struct camss_clock *clock = &csid->clock[i];
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if (!strcmp(clock->name, "csi0") ||
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!strcmp(clock->name, "csi1")) {
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u8 bpp = csid_get_fmt_entry(
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csid->fmt[MSM_CSIPHY_PAD_SINK].code)->bpp;
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u8 num_lanes = csid->phy.lane_cnt;
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u64 min_rate = pixel_clock * bpp / (2 * num_lanes * 4);
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long rate;
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camss_add_clock_margin(&min_rate);
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for (j = 0; j < clock->nfreqs; j++)
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if (min_rate < clock->freq[j])
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break;
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if (j == clock->nfreqs) {
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dev_err(dev,
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"Pixel clock is too high for CSID\n");
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return -EINVAL;
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}
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/* if sensor pixel clock is not available */
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/* set highest possible CSID clock rate */
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if (min_rate == 0)
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j = clock->nfreqs - 1;
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rate = clk_round_rate(clock->clk, clock->freq[j]);
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if (rate < 0) {
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dev_err(dev, "clk round rate failed: %ld\n",
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rate);
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return -EINVAL;
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}
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ret = clk_set_rate(clock->clk, rate);
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if (ret < 0) {
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dev_err(dev, "clk set rate failed: %d\n", ret);
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return ret;
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}
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}
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}
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return 0;
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}
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/*
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* csid_reset - Trigger reset on CSID module and wait to complete
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* @csid: CSID device
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@ -249,6 +327,12 @@ static int csid_set_power(struct v4l2_subdev *sd, int on)
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if (ret < 0)
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return ret;
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ret = csid_set_clock_rates(csid);
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if (ret < 0) {
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regulator_disable(csid->vdda);
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return ret;
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}
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ret = camss_enable_clocks(csid->nclocks, csid->clock, dev);
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if (ret < 0) {
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regulator_disable(csid->vdda);
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@ -316,7 +400,8 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable)
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struct v4l2_mbus_framefmt *f =
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&csid->fmt[MSM_CSID_PAD_SRC];
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u8 bpp = csid_get_fmt_entry(f->code)->bpp;
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u32 num_bytes_per_line = f->width * bpp / 8;
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u8 spp = csid_get_fmt_entry(f->code)->spp;
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u32 num_bytes_per_line = f->width * bpp * spp / 8;
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u32 num_lines = f->height;
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/* 31:24 V blank, 23:13 H blank, 3:2 num of active DT */
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@ -719,7 +804,7 @@ int msm_csid_subdev_init(struct csid_device *csid,
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struct device *dev = to_device_index(csid, id);
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *r;
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int i;
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int i, j;
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int ret;
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csid->id = id;
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@ -766,26 +851,30 @@ int msm_csid_subdev_init(struct csid_device *csid,
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return -ENOMEM;
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for (i = 0; i < csid->nclocks; i++) {
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csid->clock[i] = devm_clk_get(dev, res->clock[i]);
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if (IS_ERR(csid->clock[i]))
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return PTR_ERR(csid->clock[i]);
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struct camss_clock *clock = &csid->clock[i];
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if (res->clock_rate[i]) {
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long clk_rate = clk_round_rate(csid->clock[i],
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res->clock_rate[i]);
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if (clk_rate < 0) {
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dev_err(to_device_index(csid, csid->id),
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"clk round rate failed: %ld\n",
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clk_rate);
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return -EINVAL;
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}
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ret = clk_set_rate(csid->clock[i], clk_rate);
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if (ret < 0) {
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dev_err(to_device_index(csid, csid->id),
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"clk set rate failed: %d\n", ret);
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return ret;
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}
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clock->clk = devm_clk_get(dev, res->clock[i]);
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if (IS_ERR(clock->clk))
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return PTR_ERR(clock->clk);
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clock->name = res->clock[i];
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clock->nfreqs = 0;
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while (res->clock_rate[i][clock->nfreqs])
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clock->nfreqs++;
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if (!clock->nfreqs) {
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clock->freq = NULL;
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continue;
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}
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clock->freq = devm_kzalloc(dev, clock->nfreqs *
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sizeof(*clock->freq), GFP_KERNEL);
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if (!clock->freq)
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return -ENOMEM;
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for (j = 0; j < clock->nfreqs; j++)
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clock->freq[j] = res->clock_rate[i][j];
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}
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/* Regulator */
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@ -56,7 +56,7 @@ struct csid_device {
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void __iomem *base;
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u32 irq;
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char irq_name[30];
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struct clk **clock;
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struct camss_clock *clock;
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int nclocks;
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struct regulator *vdda;
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struct completion reset_complete;
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@ -157,6 +157,69 @@ static irqreturn_t csiphy_isr(int irq, void *dev)
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return IRQ_HANDLED;
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}
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/*
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* csiphy_set_clock_rates - Calculate and set clock rates on CSIPHY module
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* @csiphy: CSIPHY device
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*/
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static int csiphy_set_clock_rates(struct csiphy_device *csiphy)
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{
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struct device *dev = to_device_index(csiphy, csiphy->id);
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u32 pixel_clock;
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int i, j;
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int ret;
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ret = camss_get_pixel_clock(&csiphy->subdev.entity, &pixel_clock);
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if (ret)
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pixel_clock = 0;
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for (i = 0; i < csiphy->nclocks; i++) {
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struct camss_clock *clock = &csiphy->clock[i];
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if (!strcmp(clock->name, "csiphy0_timer") ||
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!strcmp(clock->name, "csiphy1_timer")) {
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u8 bpp = csiphy_get_bpp(
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csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
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u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
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u64 min_rate = pixel_clock * bpp / (2 * num_lanes * 4);
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long round_rate;
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camss_add_clock_margin(&min_rate);
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for (j = 0; j < clock->nfreqs; j++)
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if (min_rate < clock->freq[j])
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break;
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if (j == clock->nfreqs) {
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dev_err(dev,
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"Pixel clock is too high for CSIPHY\n");
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return -EINVAL;
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}
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/* if sensor pixel clock is not available */
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/* set highest possible CSIPHY clock rate */
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if (min_rate == 0)
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j = clock->nfreqs - 1;
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round_rate = clk_round_rate(clock->clk, clock->freq[j]);
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if (round_rate < 0) {
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dev_err(dev, "clk round rate failed: %ld\n",
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round_rate);
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return -EINVAL;
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}
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csiphy->timer_clk_rate = round_rate;
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ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate);
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if (ret < 0) {
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dev_err(dev, "clk set rate failed: %d\n", ret);
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return ret;
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}
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}
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}
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return 0;
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}
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/*
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* csiphy_reset - Perform software reset on CSIPHY module
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* @csiphy: CSIPHY device
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@ -184,6 +247,10 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on)
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u8 hw_version;
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int ret;
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ret = csiphy_set_clock_rates(csiphy);
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if (ret < 0)
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return ret;
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ret = camss_enable_clocks(csiphy->nclocks, csiphy->clock, dev);
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if (ret < 0)
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return ret;
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@ -616,7 +683,7 @@ int msm_csiphy_subdev_init(struct csiphy_device *csiphy,
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struct device *dev = to_device_index(csiphy, id);
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *r;
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int i;
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int i, j;
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int ret;
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csiphy->id = id;
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@ -671,30 +738,30 @@ int msm_csiphy_subdev_init(struct csiphy_device *csiphy,
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return -ENOMEM;
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for (i = 0; i < csiphy->nclocks; i++) {
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csiphy->clock[i] = devm_clk_get(dev, res->clock[i]);
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if (IS_ERR(csiphy->clock[i]))
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return PTR_ERR(csiphy->clock[i]);
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struct camss_clock *clock = &csiphy->clock[i];
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if (res->clock_rate[i]) {
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long clk_rate = clk_round_rate(csiphy->clock[i],
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res->clock_rate[i]);
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if (clk_rate < 0) {
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dev_err(to_device_index(csiphy, csiphy->id),
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"clk round rate failed: %ld\n",
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clk_rate);
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return -EINVAL;
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}
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ret = clk_set_rate(csiphy->clock[i], clk_rate);
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if (ret < 0) {
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dev_err(to_device_index(csiphy, csiphy->id),
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"clk set rate failed: %d\n", ret);
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return ret;
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}
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clock->clk = devm_clk_get(dev, res->clock[i]);
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if (IS_ERR(clock->clk))
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return PTR_ERR(clock->clk);
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if (!strcmp(res->clock[i], "csiphy0_timer") ||
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!strcmp(res->clock[i], "csiphy1_timer"))
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csiphy->timer_clk_rate = clk_rate;
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clock->name = res->clock[i];
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clock->nfreqs = 0;
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while (res->clock_rate[i][clock->nfreqs])
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clock->nfreqs++;
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if (!clock->nfreqs) {
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clock->freq = NULL;
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continue;
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}
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clock->freq = devm_kzalloc(dev, clock->nfreqs *
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sizeof(*clock->freq), GFP_KERNEL);
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if (!clock->freq)
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return -ENOMEM;
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for (j = 0; j < clock->nfreqs; j++)
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clock->freq[j] = res->clock_rate[i][j];
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}
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return 0;
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@ -57,7 +57,7 @@ struct csiphy_device {
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void __iomem *base_clk_mux;
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u32 irq;
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char irq_name[30];
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struct clk **clock;
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struct camss_clock *clock;
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int nclocks;
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u32 timer_clk_rate;
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struct csiphy_config cfg;
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@ -954,9 +954,14 @@ int msm_ispif_subdev_init(struct ispif_device *ispif,
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return -ENOMEM;
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for (i = 0; i < ispif->nclocks; i++) {
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ispif->clock[i] = devm_clk_get(dev, res->clock[i]);
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if (IS_ERR(ispif->clock[i]))
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return PTR_ERR(ispif->clock[i]);
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struct camss_clock *clock = &ispif->clock[i];
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clock->clk = devm_clk_get(dev, res->clock[i]);
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if (IS_ERR(clock->clk))
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return PTR_ERR(clock->clk);
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clock->freq = NULL;
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clock->nfreqs = 0;
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}
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ispif->nclocks_for_reset = 0;
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|
|
@ -969,10 +974,14 @@ int msm_ispif_subdev_init(struct ispif_device *ispif,
|
|||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ispif->nclocks_for_reset; i++) {
|
||||
ispif->clock_for_reset[i] = devm_clk_get(dev,
|
||||
res->clock_for_reset[i]);
|
||||
if (IS_ERR(ispif->clock_for_reset[i]))
|
||||
return PTR_ERR(ispif->clock_for_reset[i]);
|
||||
struct camss_clock *clock = &ispif->clock_for_reset[i];
|
||||
|
||||
clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);
|
||||
if (IS_ERR(clock->clk))
|
||||
return PTR_ERR(clock->clk);
|
||||
|
||||
clock->freq = NULL;
|
||||
clock->nfreqs = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ispif->line); i++)
|
||||
|
|
|
|||
|
|
@ -60,9 +60,9 @@ struct ispif_device {
|
|||
void __iomem *base_clk_mux;
|
||||
u32 irq;
|
||||
char irq_name[30];
|
||||
struct clk **clock;
|
||||
struct camss_clock *clock;
|
||||
int nclocks;
|
||||
struct clk **clock_for_reset;
|
||||
struct camss_clock *clock_for_reset;
|
||||
int nclocks_for_reset;
|
||||
struct completion reset_complete;
|
||||
int power_count;
|
||||
|
|
|
|||
|
|
@ -243,25 +243,95 @@
|
|||
|
||||
#define SCALER_RATIO_MAX 16
|
||||
|
||||
static const u32 vfe_formats[] = {
|
||||
MEDIA_BUS_FMT_UYVY8_2X8,
|
||||
MEDIA_BUS_FMT_VYUY8_2X8,
|
||||
MEDIA_BUS_FMT_YUYV8_2X8,
|
||||
MEDIA_BUS_FMT_YVYU8_2X8,
|
||||
MEDIA_BUS_FMT_SBGGR8_1X8,
|
||||
MEDIA_BUS_FMT_SGBRG8_1X8,
|
||||
MEDIA_BUS_FMT_SGRBG8_1X8,
|
||||
MEDIA_BUS_FMT_SRGGB8_1X8,
|
||||
MEDIA_BUS_FMT_SBGGR10_1X10,
|
||||
MEDIA_BUS_FMT_SGBRG10_1X10,
|
||||
MEDIA_BUS_FMT_SGRBG10_1X10,
|
||||
MEDIA_BUS_FMT_SRGGB10_1X10,
|
||||
MEDIA_BUS_FMT_SBGGR12_1X12,
|
||||
MEDIA_BUS_FMT_SGBRG12_1X12,
|
||||
MEDIA_BUS_FMT_SGRBG12_1X12,
|
||||
MEDIA_BUS_FMT_SRGGB12_1X12,
|
||||
static const struct {
|
||||
u32 code;
|
||||
u8 bpp;
|
||||
} vfe_formats[] = {
|
||||
{
|
||||
MEDIA_BUS_FMT_UYVY8_2X8,
|
||||
8,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_VYUY8_2X8,
|
||||
8,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_YUYV8_2X8,
|
||||
8,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_YVYU8_2X8,
|
||||
8,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SBGGR8_1X8,
|
||||
8,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SGBRG8_1X8,
|
||||
8,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SGRBG8_1X8,
|
||||
8,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SRGGB8_1X8,
|
||||
8,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SBGGR10_1X10,
|
||||
10,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SGBRG10_1X10,
|
||||
10,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SGRBG10_1X10,
|
||||
10,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SRGGB10_1X10,
|
||||
10,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SBGGR12_1X12,
|
||||
12,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SGBRG12_1X12,
|
||||
12,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SGRBG12_1X12,
|
||||
12,
|
||||
},
|
||||
{
|
||||
MEDIA_BUS_FMT_SRGGB12_1X12,
|
||||
12,
|
||||
}
|
||||
};
|
||||
|
||||
/*
|
||||
* vfe_get_bpp - map media bus format to bits per pixel
|
||||
* @code: media bus format code
|
||||
*
|
||||
* Return number of bits per pixel
|
||||
*/
|
||||
static u8 vfe_get_bpp(u32 code)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(vfe_formats); i++)
|
||||
if (code == vfe_formats[i].code)
|
||||
return vfe_formats[i].bpp;
|
||||
|
||||
WARN(1, "Unknown format\n");
|
||||
|
||||
return vfe_formats[0].bpp;
|
||||
}
|
||||
|
||||
static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits)
|
||||
{
|
||||
u32 bits = readl_relaxed(vfe->base + reg);
|
||||
|
|
@ -1766,6 +1836,138 @@ static irqreturn_t vfe_isr(int irq, void *dev)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/*
|
||||
* vfe_set_clock_rates - Calculate and set clock rates on VFE module
|
||||
* @vfe: VFE device
|
||||
*
|
||||
* Return 0 on success or a negative error code otherwise
|
||||
*/
|
||||
static int vfe_set_clock_rates(struct vfe_device *vfe)
|
||||
{
|
||||
struct device *dev = to_device(vfe);
|
||||
u32 pixel_clock[MSM_VFE_LINE_NUM];
|
||||
int i, j;
|
||||
int ret;
|
||||
|
||||
for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) {
|
||||
ret = camss_get_pixel_clock(&vfe->line[i].subdev.entity,
|
||||
&pixel_clock[i]);
|
||||
if (ret)
|
||||
pixel_clock[i] = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < vfe->nclocks; i++) {
|
||||
struct camss_clock *clock = &vfe->clock[i];
|
||||
|
||||
if (!strcmp(clock->name, "camss_vfe_vfe")) {
|
||||
u64 min_rate = 0;
|
||||
long rate;
|
||||
|
||||
for (j = VFE_LINE_RDI0; j <= VFE_LINE_PIX; j++) {
|
||||
u32 tmp;
|
||||
u8 bpp;
|
||||
|
||||
if (j == VFE_LINE_PIX) {
|
||||
tmp = pixel_clock[j];
|
||||
} else {
|
||||
bpp = vfe_get_bpp(vfe->line[j].
|
||||
fmt[MSM_VFE_PAD_SINK].code);
|
||||
tmp = pixel_clock[j] * bpp / 64;
|
||||
}
|
||||
|
||||
if (min_rate < tmp)
|
||||
min_rate = tmp;
|
||||
}
|
||||
|
||||
camss_add_clock_margin(&min_rate);
|
||||
|
||||
for (j = 0; j < clock->nfreqs; j++)
|
||||
if (min_rate < clock->freq[j])
|
||||
break;
|
||||
|
||||
if (j == clock->nfreqs) {
|
||||
dev_err(dev,
|
||||
"Pixel clock is too high for VFE");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* if sensor pixel clock is not available */
|
||||
/* set highest possible VFE clock rate */
|
||||
if (min_rate == 0)
|
||||
j = clock->nfreqs - 1;
|
||||
|
||||
rate = clk_round_rate(clock->clk, clock->freq[j]);
|
||||
if (rate < 0) {
|
||||
dev_err(dev, "clk round rate failed: %ld\n",
|
||||
rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = clk_set_rate(clock->clk, rate);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "clk set rate failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* vfe_check_clock_rates - Check current clock rates on VFE module
|
||||
* @vfe: VFE device
|
||||
*
|
||||
* Return 0 if current clock rates are suitable for a new pipeline
|
||||
* or a negative error code otherwise
|
||||
*/
|
||||
static int vfe_check_clock_rates(struct vfe_device *vfe)
|
||||
{
|
||||
u32 pixel_clock[MSM_VFE_LINE_NUM];
|
||||
int i, j;
|
||||
int ret;
|
||||
|
||||
for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) {
|
||||
ret = camss_get_pixel_clock(&vfe->line[i].subdev.entity,
|
||||
&pixel_clock[i]);
|
||||
if (ret)
|
||||
pixel_clock[i] = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < vfe->nclocks; i++) {
|
||||
struct camss_clock *clock = &vfe->clock[i];
|
||||
|
||||
if (!strcmp(clock->name, "camss_vfe_vfe")) {
|
||||
u64 min_rate = 0;
|
||||
unsigned long rate;
|
||||
|
||||
for (j = VFE_LINE_RDI0; j <= VFE_LINE_PIX; j++) {
|
||||
u32 tmp;
|
||||
u8 bpp;
|
||||
|
||||
if (j == VFE_LINE_PIX) {
|
||||
tmp = pixel_clock[j];
|
||||
} else {
|
||||
bpp = vfe_get_bpp(vfe->line[j].
|
||||
fmt[MSM_VFE_PAD_SINK].code);
|
||||
tmp = pixel_clock[j] * bpp / 64;
|
||||
}
|
||||
|
||||
if (min_rate < tmp)
|
||||
min_rate = tmp;
|
||||
}
|
||||
|
||||
camss_add_clock_margin(&min_rate);
|
||||
|
||||
rate = clk_get_rate(clock->clk);
|
||||
if (rate < min_rate)
|
||||
return -EBUSY;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* vfe_get - Power up and reset VFE module
|
||||
* @vfe: VFE Device
|
||||
|
|
@ -1779,6 +1981,10 @@ static int vfe_get(struct vfe_device *vfe)
|
|||
mutex_lock(&vfe->power_lock);
|
||||
|
||||
if (vfe->power_count == 0) {
|
||||
ret = vfe_set_clock_rates(vfe);
|
||||
if (ret < 0)
|
||||
goto error_clocks;
|
||||
|
||||
ret = camss_enable_clocks(vfe->nclocks, vfe->clock,
|
||||
to_device(vfe));
|
||||
if (ret < 0)
|
||||
|
|
@ -1791,6 +1997,10 @@ static int vfe_get(struct vfe_device *vfe)
|
|||
vfe_reset_output_maps(vfe);
|
||||
|
||||
vfe_init_outputs(vfe);
|
||||
} else {
|
||||
ret = vfe_check_clock_rates(vfe);
|
||||
if (ret < 0)
|
||||
goto error_clocks;
|
||||
}
|
||||
vfe->power_count++;
|
||||
|
||||
|
|
@ -2074,7 +2284,7 @@ static void vfe_try_format(struct vfe_line *line,
|
|||
/* Set format on sink pad */
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(vfe_formats); i++)
|
||||
if (fmt->code == vfe_formats[i])
|
||||
if (fmt->code == vfe_formats[i].code)
|
||||
break;
|
||||
|
||||
/* If not found, use UYVY as default */
|
||||
|
|
@ -2241,7 +2451,7 @@ static int vfe_enum_mbus_code(struct v4l2_subdev *sd,
|
|||
if (code->index >= ARRAY_SIZE(vfe_formats))
|
||||
return -EINVAL;
|
||||
|
||||
code->code = vfe_formats[code->index];
|
||||
code->code = vfe_formats[code->index].code;
|
||||
} else {
|
||||
if (code->index > 0)
|
||||
return -EINVAL;
|
||||
|
|
@ -2544,7 +2754,7 @@ int msm_vfe_subdev_init(struct vfe_device *vfe, const struct resources *res)
|
|||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct resource *r;
|
||||
struct camss *camss = to_camss(vfe);
|
||||
int i;
|
||||
int i, j;
|
||||
int ret;
|
||||
|
||||
/* Memory */
|
||||
|
|
@ -2587,23 +2797,30 @@ int msm_vfe_subdev_init(struct vfe_device *vfe, const struct resources *res)
|
|||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < vfe->nclocks; i++) {
|
||||
vfe->clock[i] = devm_clk_get(dev, res->clock[i]);
|
||||
if (IS_ERR(vfe->clock[i]))
|
||||
return PTR_ERR(vfe->clock[i]);
|
||||
struct camss_clock *clock = &vfe->clock[i];
|
||||
|
||||
if (res->clock_rate[i]) {
|
||||
long clk_rate = clk_round_rate(vfe->clock[i],
|
||||
res->clock_rate[i]);
|
||||
if (clk_rate < 0) {
|
||||
dev_err(dev, "clk round rate failed\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
ret = clk_set_rate(vfe->clock[i], clk_rate);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "clk set rate failed\n");
|
||||
return ret;
|
||||
}
|
||||
clock->clk = devm_clk_get(dev, res->clock[i]);
|
||||
if (IS_ERR(clock->clk))
|
||||
return PTR_ERR(clock->clk);
|
||||
|
||||
clock->name = res->clock[i];
|
||||
|
||||
clock->nfreqs = 0;
|
||||
while (res->clock_rate[i][clock->nfreqs])
|
||||
clock->nfreqs++;
|
||||
|
||||
if (!clock->nfreqs) {
|
||||
clock->freq = NULL;
|
||||
continue;
|
||||
}
|
||||
|
||||
clock->freq = devm_kzalloc(dev, clock->nfreqs *
|
||||
sizeof(*clock->freq), GFP_KERNEL);
|
||||
if (!clock->freq)
|
||||
return -ENOMEM;
|
||||
|
||||
for (j = 0; j < clock->nfreqs; j++)
|
||||
clock->freq[j] = res->clock_rate[i][j];
|
||||
}
|
||||
|
||||
mutex_init(&vfe->power_lock);
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ struct vfe_device {
|
|||
void __iomem *base;
|
||||
u32 irq;
|
||||
char irq_name[30];
|
||||
struct clk **clock;
|
||||
struct camss_clock *clock;
|
||||
int nclocks;
|
||||
struct completion reset_complete;
|
||||
struct completion halt_complete;
|
||||
|
|
|
|||
|
|
@ -33,13 +33,19 @@
|
|||
|
||||
#include "camss.h"
|
||||
|
||||
#define CAMSS_CLOCK_MARGIN_NUMERATOR 105
|
||||
#define CAMSS_CLOCK_MARGIN_DENOMINATOR 100
|
||||
|
||||
static const struct resources csiphy_res[] = {
|
||||
/* CSIPHY0 */
|
||||
{
|
||||
.regulator = { NULL },
|
||||
.clock = { "camss_top_ahb", "ispif_ahb",
|
||||
"camss_ahb", "csiphy0_timer" },
|
||||
.clock_rate = { 0, 0, 0, 200000000 },
|
||||
.clock_rate = { { 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 100000000, 200000000 } },
|
||||
.reg = { "csiphy0", "csiphy0_clk_mux" },
|
||||
.interrupt = { "csiphy0" }
|
||||
},
|
||||
|
|
@ -49,7 +55,10 @@ static const struct resources csiphy_res[] = {
|
|||
.regulator = { NULL },
|
||||
.clock = { "camss_top_ahb", "ispif_ahb",
|
||||
"camss_ahb", "csiphy1_timer" },
|
||||
.clock_rate = { 0, 0, 0, 200000000 },
|
||||
.clock_rate = { { 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 100000000, 200000000 } },
|
||||
.reg = { "csiphy1", "csiphy1_clk_mux" },
|
||||
.interrupt = { "csiphy1" }
|
||||
}
|
||||
|
|
@ -62,7 +71,14 @@ static const struct resources csid_res[] = {
|
|||
.clock = { "camss_top_ahb", "ispif_ahb",
|
||||
"csi0_ahb", "camss_ahb",
|
||||
"csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
|
||||
.clock_rate = { 0, 0, 0, 0, 200000000, 0, 0, 0 },
|
||||
.clock_rate = { { 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 100000000, 200000000 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 } },
|
||||
.reg = { "csid0" },
|
||||
.interrupt = { "csid0" }
|
||||
},
|
||||
|
|
@ -73,7 +89,14 @@ static const struct resources csid_res[] = {
|
|||
.clock = { "camss_top_ahb", "ispif_ahb",
|
||||
"csi1_ahb", "camss_ahb",
|
||||
"csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
|
||||
.clock_rate = { 0, 0, 0, 0, 200000000, 0, 0, 0 },
|
||||
.clock_rate = { { 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 100000000, 200000000 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 } },
|
||||
.reg = { "csid1" },
|
||||
.interrupt = { "csid1" }
|
||||
},
|
||||
|
|
@ -95,11 +118,34 @@ static const struct resources vfe_res = {
|
|||
.regulator = { NULL },
|
||||
.clock = { "camss_top_ahb", "camss_vfe_vfe", "camss_csi_vfe",
|
||||
"iface", "bus", "camss_ahb" },
|
||||
.clock_rate = { 0, 320000000, 0, 0, 0, 0, 0, 0 },
|
||||
.clock_rate = { { 0 },
|
||||
{ 50000000, 80000000, 100000000, 160000000,
|
||||
177780000, 200000000, 266670000, 320000000,
|
||||
400000000, 465000000 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 },
|
||||
{ 0 } },
|
||||
.reg = { "vfe0" },
|
||||
.interrupt = { "vfe0" }
|
||||
};
|
||||
|
||||
/*
|
||||
* camss_add_clock_margin - Add margin to clock frequency rate
|
||||
* @rate: Clock frequency rate
|
||||
*
|
||||
* When making calculations with physical clock frequency values
|
||||
* some safety margin must be added. Add it.
|
||||
*/
|
||||
inline void camss_add_clock_margin(u64 *rate)
|
||||
{
|
||||
*rate *= CAMSS_CLOCK_MARGIN_NUMERATOR;
|
||||
*rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR);
|
||||
}
|
||||
|
||||
/*
|
||||
* camss_enable_clocks - Enable multiple clocks
|
||||
* @nclocks: Number of clocks in clock array
|
||||
|
|
@ -108,13 +154,14 @@ static const struct resources vfe_res = {
|
|||
*
|
||||
* Return 0 on success or a negative error code otherwise
|
||||
*/
|
||||
int camss_enable_clocks(int nclocks, struct clk **clock, struct device *dev)
|
||||
int camss_enable_clocks(int nclocks, struct camss_clock *clock,
|
||||
struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nclocks; i++) {
|
||||
ret = clk_prepare_enable(clock[i]);
|
||||
ret = clk_prepare_enable(clock[i].clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "clock enable failed: %d\n", ret);
|
||||
goto error;
|
||||
|
|
@ -125,7 +172,7 @@ int camss_enable_clocks(int nclocks, struct clk **clock, struct device *dev)
|
|||
|
||||
error:
|
||||
for (i--; i >= 0; i--)
|
||||
clk_disable_unprepare(clock[i]);
|
||||
clk_disable_unprepare(clock[i].clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -135,12 +182,12 @@ error:
|
|||
* @nclocks: Number of clocks in clock array
|
||||
* @clock: Clock array
|
||||
*/
|
||||
void camss_disable_clocks(int nclocks, struct clk **clock)
|
||||
void camss_disable_clocks(int nclocks, struct camss_clock *clock)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = nclocks - 1; i >= 0; i--)
|
||||
clk_disable_unprepare(clock[i]);
|
||||
clk_disable_unprepare(clock[i].clk);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@
|
|||
struct resources {
|
||||
char *regulator[CAMSS_RES_MAX];
|
||||
char *clock[CAMSS_RES_MAX];
|
||||
s32 clock_rate[CAMSS_RES_MAX];
|
||||
u32 clock_rate[CAMSS_RES_MAX][CAMSS_RES_MAX];
|
||||
char *reg[CAMSS_RES_MAX];
|
||||
char *interrupt[CAMSS_RES_MAX];
|
||||
};
|
||||
|
|
@ -89,8 +89,17 @@ struct camss_async_subdev {
|
|||
struct v4l2_async_subdev asd;
|
||||
};
|
||||
|
||||
int camss_enable_clocks(int nclocks, struct clk **clock, struct device *dev);
|
||||
void camss_disable_clocks(int nclocks, struct clk **clock);
|
||||
struct camss_clock {
|
||||
struct clk *clk;
|
||||
const char *name;
|
||||
u32 *freq;
|
||||
u32 nfreqs;
|
||||
};
|
||||
|
||||
void camss_add_clock_margin(u64 *rate);
|
||||
int camss_enable_clocks(int nclocks, struct camss_clock *clock,
|
||||
struct device *dev);
|
||||
void camss_disable_clocks(int nclocks, struct camss_clock *clock);
|
||||
int camss_get_pixel_clock(struct media_entity *entity, u32 *pixel_clock);
|
||||
void camss_delete(struct camss *camss);
|
||||
|
||||
|
|
|
|||
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