CRIS v32: Remove hwregs/timer_defs.h, it is now architecture specific.
- File is moved to arch-v32/mach-fs/hwregs/timer_defs.h
This commit is contained in:
Jesper Nilsson
Родитель
69b06c15e7
Коммит
bc10ac3f2f
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#ifndef __timer_defs_h
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#define __timer_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/timer/rtl/timer_regs.r
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* id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
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* last modfied: Mon Apr 11 16:09:53 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
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* id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope timer */
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/* Register rw_tmr0_div, scope timer, type rw */
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typedef unsigned int reg_timer_rw_tmr0_div;
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#define REG_RD_ADDR_timer_rw_tmr0_div 0
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#define REG_WR_ADDR_timer_rw_tmr0_div 0
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/* Register r_tmr0_data, scope timer, type r */
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typedef unsigned int reg_timer_r_tmr0_data;
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#define REG_RD_ADDR_timer_r_tmr0_data 4
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/* Register rw_tmr0_ctrl, scope timer, type rw */
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typedef struct {
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unsigned int op : 2;
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unsigned int freq : 3;
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unsigned int dummy1 : 27;
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} reg_timer_rw_tmr0_ctrl;
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#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
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#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
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/* Register rw_tmr1_div, scope timer, type rw */
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typedef unsigned int reg_timer_rw_tmr1_div;
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#define REG_RD_ADDR_timer_rw_tmr1_div 16
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#define REG_WR_ADDR_timer_rw_tmr1_div 16
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/* Register r_tmr1_data, scope timer, type r */
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typedef unsigned int reg_timer_r_tmr1_data;
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#define REG_RD_ADDR_timer_r_tmr1_data 20
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/* Register rw_tmr1_ctrl, scope timer, type rw */
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typedef struct {
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unsigned int op : 2;
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unsigned int freq : 3;
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unsigned int dummy1 : 27;
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} reg_timer_rw_tmr1_ctrl;
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#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
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#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
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/* Register rs_cnt_data, scope timer, type rs */
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typedef struct {
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unsigned int tmr : 24;
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unsigned int cnt : 8;
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} reg_timer_rs_cnt_data;
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#define REG_RD_ADDR_timer_rs_cnt_data 32
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/* Register r_cnt_data, scope timer, type r */
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typedef struct {
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unsigned int tmr : 24;
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unsigned int cnt : 8;
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} reg_timer_r_cnt_data;
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#define REG_RD_ADDR_timer_r_cnt_data 36
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/* Register rw_cnt_cfg, scope timer, type rw */
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typedef struct {
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unsigned int clk : 2;
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unsigned int dummy1 : 30;
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} reg_timer_rw_cnt_cfg;
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#define REG_RD_ADDR_timer_rw_cnt_cfg 40
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#define REG_WR_ADDR_timer_rw_cnt_cfg 40
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/* Register rw_trig, scope timer, type rw */
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typedef unsigned int reg_timer_rw_trig;
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#define REG_RD_ADDR_timer_rw_trig 48
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#define REG_WR_ADDR_timer_rw_trig 48
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/* Register rw_trig_cfg, scope timer, type rw */
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typedef struct {
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unsigned int tmr : 2;
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unsigned int dummy1 : 30;
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} reg_timer_rw_trig_cfg;
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#define REG_RD_ADDR_timer_rw_trig_cfg 52
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#define REG_WR_ADDR_timer_rw_trig_cfg 52
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/* Register r_time, scope timer, type r */
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typedef unsigned int reg_timer_r_time;
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#define REG_RD_ADDR_timer_r_time 56
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/* Register rw_out, scope timer, type rw */
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typedef struct {
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unsigned int tmr : 2;
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unsigned int dummy1 : 30;
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} reg_timer_rw_out;
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#define REG_RD_ADDR_timer_rw_out 60
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#define REG_WR_ADDR_timer_rw_out 60
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/* Register rw_wd_ctrl, scope timer, type rw */
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typedef struct {
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unsigned int cnt : 8;
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unsigned int cmd : 1;
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unsigned int key : 7;
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unsigned int dummy1 : 16;
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} reg_timer_rw_wd_ctrl;
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#define REG_RD_ADDR_timer_rw_wd_ctrl 64
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#define REG_WR_ADDR_timer_rw_wd_ctrl 64
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/* Register r_wd_stat, scope timer, type r */
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typedef struct {
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unsigned int cnt : 8;
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unsigned int cmd : 1;
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unsigned int dummy1 : 23;
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} reg_timer_r_wd_stat;
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#define REG_RD_ADDR_timer_r_wd_stat 68
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/* Register rw_intr_mask, scope timer, type rw */
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typedef struct {
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unsigned int tmr0 : 1;
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unsigned int tmr1 : 1;
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unsigned int cnt : 1;
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unsigned int trig : 1;
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unsigned int dummy1 : 28;
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} reg_timer_rw_intr_mask;
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#define REG_RD_ADDR_timer_rw_intr_mask 72
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#define REG_WR_ADDR_timer_rw_intr_mask 72
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/* Register rw_ack_intr, scope timer, type rw */
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typedef struct {
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unsigned int tmr0 : 1;
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unsigned int tmr1 : 1;
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unsigned int cnt : 1;
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unsigned int trig : 1;
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unsigned int dummy1 : 28;
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} reg_timer_rw_ack_intr;
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#define REG_RD_ADDR_timer_rw_ack_intr 76
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#define REG_WR_ADDR_timer_rw_ack_intr 76
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/* Register r_intr, scope timer, type r */
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typedef struct {
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unsigned int tmr0 : 1;
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unsigned int tmr1 : 1;
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unsigned int cnt : 1;
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unsigned int trig : 1;
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unsigned int dummy1 : 28;
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} reg_timer_r_intr;
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#define REG_RD_ADDR_timer_r_intr 80
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/* Register r_masked_intr, scope timer, type r */
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typedef struct {
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unsigned int tmr0 : 1;
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unsigned int tmr1 : 1;
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unsigned int cnt : 1;
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unsigned int trig : 1;
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unsigned int dummy1 : 28;
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} reg_timer_r_masked_intr;
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#define REG_RD_ADDR_timer_r_masked_intr 84
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/* Register rw_test, scope timer, type rw */
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typedef struct {
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unsigned int dis : 1;
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unsigned int en : 1;
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unsigned int dummy1 : 30;
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} reg_timer_rw_test;
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#define REG_RD_ADDR_timer_rw_test 88
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#define REG_WR_ADDR_timer_rw_test 88
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/* Constants */
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enum {
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regk_timer_ext = 0x00000001,
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regk_timer_f100 = 0x00000007,
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regk_timer_f29_493 = 0x00000004,
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regk_timer_f32 = 0x00000005,
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regk_timer_f32_768 = 0x00000006,
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regk_timer_hold = 0x00000001,
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regk_timer_ld = 0x00000000,
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regk_timer_no = 0x00000000,
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regk_timer_off = 0x00000000,
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regk_timer_run = 0x00000002,
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regk_timer_rw_cnt_cfg_default = 0x00000000,
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regk_timer_rw_intr_mask_default = 0x00000000,
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regk_timer_rw_out_default = 0x00000000,
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regk_timer_rw_test_default = 0x00000000,
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regk_timer_rw_tmr0_ctrl_default = 0x00000000,
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regk_timer_rw_tmr1_ctrl_default = 0x00000000,
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regk_timer_rw_trig_cfg_default = 0x00000000,
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regk_timer_start = 0x00000001,
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regk_timer_stop = 0x00000000,
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regk_timer_time = 0x00000001,
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regk_timer_tmr0 = 0x00000002,
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regk_timer_tmr1 = 0x00000003,
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regk_timer_yes = 0x00000001
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};
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#endif /* __timer_defs_h */
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