clk: tegra: add locking to periph clks
Tegra124 has periph clocks which share the hw register. Hence locking is required. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Peter De Schrijver
Родитель
2b239077d1
Коммит
bc44275b8e
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@ -118,75 +118,78 @@
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_clk_num, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
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_clk_num, _gate_flags, _clk_id, _parents##_idx, 0)
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_clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
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NULL)
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#define MUX_FLAGS(_name, _parents, _offset,\
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_clk_num, _gate_flags, _clk_id, flags)\
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
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_clk_num, _gate_flags, _clk_id, _parents##_idx, flags)
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_clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
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NULL)
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#define MUX8(_name, _parents, _offset, \
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_clk_num, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
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_clk_num, _gate_flags, _clk_id, _parents##_idx, 0)
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_clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
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NULL)
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#define INT(_name, _parents, _offset, \
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_clk_num, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
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TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
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_clk_id, _parents##_idx, 0)
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_clk_id, _parents##_idx, 0, NULL)
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#define INT_FLAGS(_name, _parents, _offset,\
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_clk_num, _gate_flags, _clk_id, flags)\
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
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TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
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_clk_id, _parents##_idx, flags)
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_clk_id, _parents##_idx, flags, NULL)
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#define INT8(_name, _parents, _offset,\
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_clk_num, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
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TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
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_clk_id, _parents##_idx, 0)
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_clk_id, _parents##_idx, 0, NULL)
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#define UART(_name, _parents, _offset,\
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_clk_num, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
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TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
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_parents##_idx, 0)
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_parents##_idx, 0, NULL)
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#define I2C(_name, _parents, _offset,\
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_clk_num, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
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_clk_num, 0, _clk_id, _parents##_idx, 0)
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_clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
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#define XUSB(_name, _parents, _offset, \
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_clk_num, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
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29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
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TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
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_clk_id, _parents##_idx, 0)
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_clk_id, _parents##_idx, 0, NULL)
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#define AUDIO(_name, _offset, _clk_num,\
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_gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
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_offset, 16, 0xE01F, 0, 0, 8, 1, \
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TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
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_clk_id, mux_d_audio_clk_idx, 0)
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_clk_id, mux_d_audio_clk_idx, 0, NULL)
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#define NODIV(_name, _parents, _offset, \
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_mux_shift, _mux_mask, _clk_num, \
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_gate_flags, _clk_id) \
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_gate_flags, _clk_id, _lock) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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_mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
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_clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
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_clk_id, _parents##_idx, 0)
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_clk_id, _parents##_idx, 0, _lock)
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#define GATE(_name, _parent_name, \
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_clk_num, _gate_flags, _clk_id, _flags) \
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@ -195,7 +198,7 @@
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.clk_id = _clk_id, \
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.p.parent_name = _parent_name, \
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.periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
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_clk_num, _gate_flags, 0), \
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_clk_num, _gate_flags, 0, NULL), \
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.flags = _flags \
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}
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@ -414,8 +417,8 @@ static struct tegra_periph_init_data periph_clks[] = {
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MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
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MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
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MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
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NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1),
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NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2),
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NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
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NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
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UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
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UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
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UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
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@ -439,19 +439,21 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
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#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
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_div_shift, _div_width, _div_frac_width, \
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_div_flags, _clk_num,\
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_gate_flags, _table) \
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_gate_flags, _table, _lock) \
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{ \
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.mux = { \
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.flags = _mux_flags, \
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.shift = _mux_shift, \
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.mask = _mux_mask, \
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.table = _table, \
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.lock = _lock, \
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}, \
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.divider = { \
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.flags = _div_flags, \
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.shift = _div_shift, \
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.width = _div_width, \
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.frac_width = _div_frac_width, \
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.lock = _lock, \
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}, \
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.gate = { \
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.flags = _gate_flags, \
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@ -481,7 +483,7 @@ struct tegra_periph_init_data {
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_mux_shift, _mux_mask, _mux_flags, _div_shift, \
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_div_width, _div_frac_width, _div_flags, \
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_clk_num, _gate_flags, _clk_id, _table, \
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_flags) \
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_flags, _lock) \
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{ \
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.name = _name, \
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.clk_id = _clk_id, \
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@ -491,7 +493,7 @@ struct tegra_periph_init_data {
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_mux_flags, _div_shift, \
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_div_width, _div_frac_width, \
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_div_flags, _clk_num, \
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_gate_flags, _table), \
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_gate_flags, _table, _lock), \
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.offset = _offset, \
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.con_id = _con_id, \
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.dev_id = _dev_id, \
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@ -506,7 +508,7 @@ struct tegra_periph_init_data {
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_mux_shift, BIT(_mux_width) - 1, _mux_flags, \
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_div_shift, _div_width, _div_frac_width, _div_flags, \
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_clk_num, _gate_flags, _clk_id,\
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NULL, 0)
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NULL, 0, NULL)
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/**
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* struct clk_super_mux - super clock
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