[PATCH] x86_64 irq: Add constants for the reserved IRQ vectors.
For the ISA irqs we reserve 16 vectors. This patch adds constants for those vectors and modifies the code to use them. Making the code a little clearer and making it possible to move these vectors in the future. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Eric W. Biederman
Linus Torvalds
Родитель
b93179bdfc
Коммит
bc5e81a151
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@ -299,7 +299,7 @@ void init_8259A(int auto_eoi)
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* outb_p - this has to work on a wide range of PC hardware.
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*/
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outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
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outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
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outb_p(IRQ0_VECTOR, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
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outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
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if (auto_eoi)
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outb_p(0x03, 0x21); /* master does Auto EOI */
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@ -307,7 +307,7 @@ void init_8259A(int auto_eoi)
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outb_p(0x01, 0x21); /* master expects normal EOI */
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outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
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outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
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outb_p(IRQ8_VECTOR, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
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outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
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outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
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is to be investigated) */
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@ -398,24 +398,24 @@ device_initcall(i8259A_init_sysfs);
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static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
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DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
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[0 ... FIRST_EXTERNAL_VECTOR - 1] = -1,
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[FIRST_EXTERNAL_VECTOR + 0] = 0,
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[FIRST_EXTERNAL_VECTOR + 1] = 1,
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[FIRST_EXTERNAL_VECTOR + 2] = 2,
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[FIRST_EXTERNAL_VECTOR + 3] = 3,
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[FIRST_EXTERNAL_VECTOR + 4] = 4,
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[FIRST_EXTERNAL_VECTOR + 5] = 5,
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[FIRST_EXTERNAL_VECTOR + 6] = 6,
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[FIRST_EXTERNAL_VECTOR + 7] = 7,
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[FIRST_EXTERNAL_VECTOR + 8] = 8,
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[FIRST_EXTERNAL_VECTOR + 9] = 9,
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[FIRST_EXTERNAL_VECTOR + 10] = 10,
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[FIRST_EXTERNAL_VECTOR + 11] = 11,
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[FIRST_EXTERNAL_VECTOR + 12] = 12,
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[FIRST_EXTERNAL_VECTOR + 13] = 13,
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[FIRST_EXTERNAL_VECTOR + 14] = 14,
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[FIRST_EXTERNAL_VECTOR + 15] = 15,
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[FIRST_EXTERNAL_VECTOR + 16 ... NR_VECTORS - 1] = -1
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[0 ... IRQ0_VECTOR - 1] = -1,
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[IRQ0_VECTOR] = 0,
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[IRQ1_VECTOR] = 1,
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[IRQ2_VECTOR] = 2,
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[IRQ3_VECTOR] = 3,
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[IRQ4_VECTOR] = 4,
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[IRQ5_VECTOR] = 5,
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[IRQ6_VECTOR] = 6,
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[IRQ7_VECTOR] = 7,
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[IRQ8_VECTOR] = 8,
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[IRQ9_VECTOR] = 9,
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[IRQ10_VECTOR] = 10,
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[IRQ11_VECTOR] = 11,
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[IRQ12_VECTOR] = 12,
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[IRQ13_VECTOR] = 13,
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[IRQ14_VECTOR] = 14,
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[IRQ15_VECTOR] = 15,
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[IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
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};
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void __init init_ISA_irqs (void)
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@ -54,22 +54,22 @@ struct irq_cfg {
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/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
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struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
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[0] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 0 },
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[1] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 1 },
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[2] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 2 },
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[3] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 3 },
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[4] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 4 },
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[5] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 5 },
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[6] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 6 },
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[7] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 7 },
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[8] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 8 },
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[9] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 9 },
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[10] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 10 },
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[11] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 11 },
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[12] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 12 },
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[13] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 13 },
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[14] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 14 },
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[15] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 15 },
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[0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
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[1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
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[2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
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[3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
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[4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
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[5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
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[6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
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[7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
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[8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
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[9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
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[10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
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[11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
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[12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
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[13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
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[14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
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[15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
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};
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static int assign_irq_vector(int irq, cpumask_t mask);
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@ -35,6 +35,22 @@
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/*
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* Vectors 0x20-0x2f are used for ISA interrupts.
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*/
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#define IRQ0_VECTOR FIRST_EXTERNAL_VECTOR
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#define IRQ1_VECTOR IRQ0_VECTOR + 1
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#define IRQ2_VECTOR IRQ0_VECTOR + 2
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#define IRQ3_VECTOR IRQ0_VECTOR + 3
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#define IRQ4_VECTOR IRQ0_VECTOR + 4
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#define IRQ5_VECTOR IRQ0_VECTOR + 5
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#define IRQ6_VECTOR IRQ0_VECTOR + 6
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#define IRQ7_VECTOR IRQ0_VECTOR + 7
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#define IRQ8_VECTOR IRQ0_VECTOR + 8
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#define IRQ9_VECTOR IRQ0_VECTOR + 9
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#define IRQ10_VECTOR IRQ0_VECTOR + 10
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#define IRQ11_VECTOR IRQ0_VECTOR + 11
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#define IRQ12_VECTOR IRQ0_VECTOR + 12
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#define IRQ13_VECTOR IRQ0_VECTOR + 13
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#define IRQ14_VECTOR IRQ0_VECTOR + 14
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#define IRQ15_VECTOR IRQ0_VECTOR + 15
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/*
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* Special IRQ vectors used by the SMP architecture, 0xf0-0xff
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@ -69,7 +85,7 @@
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* we start at 0x31 to spread out vectors evenly between priority
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* levels. (0x80 is the syscall vector)
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*/
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#define FIRST_DEVICE_VECTOR 0x31
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#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
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#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */
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