crypto: qat - add pfvf_ops
Add pfvf_ops structure to isolate PFVF related functions inside the adf_hw_device_data structure. For GEN2, the structure is populated using one of the two helper functions, adf_gen2_init_pf_pfvf_ops() or adf_gen2_init_vf_pfvf_ops(), for the PF and VF driver respectively. For the DH895XCC PF driver, the structure is populated using adf_gen2_init_pf_pfvf_ops() but some of the functions are then overwritten. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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Родитель
6f2e28015b
Коммит
bc63dabe52
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@ -254,8 +254,8 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data)
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hw_data->uof_get_ae_mask = uof_get_ae_mask;
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hw_data->set_msix_rttable = set_msix_default_rttable;
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hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
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hw_data->enable_pfvf_comms = adf_pfvf_comms_disabled;
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hw_data->get_vf2pf_sources = get_vf2pf_sources;
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hw_data->pfvf_ops.enable_comms = adf_pfvf_comms_disabled;
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hw_data->pfvf_ops.get_vf2pf_sources = get_vf2pf_sources;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
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@ -136,14 +136,10 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
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hw_data->enable_ints = adf_enable_ints;
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hw_data->reset_device = adf_reset_flr;
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hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
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hw_data->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset;
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hw_data->get_vf2pf_sources = adf_gen2_get_vf2pf_sources;
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hw_data->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts;
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hw_data->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts;
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hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
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adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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}
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@ -82,13 +82,12 @@ void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
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hw_data->get_num_aes = get_num_aes;
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hw_data->get_etr_bar_id = get_etr_bar_id;
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hw_data->get_misc_bar_id = get_misc_bar_id;
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hw_data->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset;
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hw_data->get_sku = get_sku;
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hw_data->enable_ints = adf_vf_void_noop;
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hw_data->enable_pfvf_comms = adf_enable_vf2pf_comms;
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hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
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hw_data->dev_class->instances++;
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adf_devmgr_update_class_index(hw_data);
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adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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}
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@ -138,14 +138,10 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
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hw_data->enable_ints = adf_enable_ints;
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hw_data->reset_device = adf_reset_flr;
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hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
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hw_data->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset;
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hw_data->get_vf2pf_sources = adf_gen2_get_vf2pf_sources;
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hw_data->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts;
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hw_data->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts;
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hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
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adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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}
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@ -82,13 +82,12 @@ void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
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hw_data->get_num_aes = get_num_aes;
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hw_data->get_etr_bar_id = get_etr_bar_id;
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hw_data->get_misc_bar_id = get_misc_bar_id;
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hw_data->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset;
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hw_data->get_sku = get_sku;
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hw_data->enable_ints = adf_vf_void_noop;
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hw_data->enable_pfvf_comms = adf_enable_vf2pf_comms;
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hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
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hw_data->dev_class->instances++;
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adf_devmgr_update_class_index(hw_data);
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adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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}
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@ -16,9 +16,9 @@ intel_qat-objs := adf_cfg.o \
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qat_algs.o \
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qat_asym_algs.o \
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qat_uclo.o \
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qat_hal.o \
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adf_gen2_pfvf.o
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qat_hal.o
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intel_qat-$(CONFIG_DEBUG_FS) += adf_transport_debug.o
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intel_qat-$(CONFIG_PCI_IOV) += adf_sriov.o adf_pf2vf_msg.o \
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adf_vf2pf_msg.o adf_vf_isr.o
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adf_vf2pf_msg.o adf_vf_isr.o \
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adf_gen2_pfvf.o
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@ -147,6 +147,14 @@ struct adf_accel_dev;
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struct adf_etr_data;
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struct adf_etr_ring_data;
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struct adf_pfvf_ops {
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int (*enable_comms)(struct adf_accel_dev *accel_dev);
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u32 (*get_pf2vf_offset)(u32 i);
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u32 (*get_vf2pf_sources)(void __iomem *pmisc_addr);
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void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
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void (*disable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
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};
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struct adf_hw_device_data {
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struct adf_hw_device_class *dev_class;
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u32 (*get_accel_mask)(struct adf_hw_device_data *self);
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@ -157,7 +165,6 @@ struct adf_hw_device_data {
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u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
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u32 (*get_num_aes)(struct adf_hw_device_data *self);
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u32 (*get_num_accels)(struct adf_hw_device_data *self);
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u32 (*get_pf2vf_offset)(u32 i);
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void (*get_arb_info)(struct arb_info *arb_csrs_info);
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void (*get_admin_info)(struct admin_info *admin_csrs_info);
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enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
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@ -176,17 +183,12 @@ struct adf_hw_device_data {
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bool enable);
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void (*enable_ints)(struct adf_accel_dev *accel_dev);
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void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
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int (*enable_pfvf_comms)(struct adf_accel_dev *accel_dev);
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u32 (*get_vf2pf_sources)(void __iomem *pmisc_addr);
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void (*enable_vf2pf_interrupts)(void __iomem *pmisc_bar_addr,
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u32 vf_mask);
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void (*disable_vf2pf_interrupts)(void __iomem *pmisc_bar_addr,
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u32 vf_mask);
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void (*reset_device)(struct adf_accel_dev *accel_dev);
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void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
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char *(*uof_get_name)(u32 obj_num);
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u32 (*uof_get_num_objs)(void);
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u32 (*uof_get_ae_mask)(u32 obj_num);
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struct adf_pfvf_ops pfvf_ops;
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struct adf_hw_csr_ops csr_ops;
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const char *fw_name;
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const char *fw_mmp_name;
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@ -222,6 +224,7 @@ struct adf_hw_device_data {
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GET_HW_DATA(accel_dev)->num_rings_per_bank
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#define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
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#define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
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#define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops)
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#define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
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struct adf_admin_comms;
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@ -2,6 +2,7 @@
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/* Copyright(c) 2021 Intel Corporation */
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#include <linux/types.h>
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#include "adf_accel_devices.h"
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#include "adf_common_drv.h"
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#include "adf_gen2_pfvf.h"
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/* VF2PF interrupts */
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@ -11,19 +12,17 @@
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#define ADF_GEN2_PF_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
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#define ADF_GEN2_VF_PF2VF_OFFSET 0x200
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u32 adf_gen2_pf_get_pf2vf_offset(u32 i)
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static u32 adf_gen2_pf_get_pf2vf_offset(u32 i)
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{
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return ADF_GEN2_PF_PF2VF_OFFSET(i);
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}
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EXPORT_SYMBOL_GPL(adf_gen2_pf_get_pf2vf_offset);
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u32 adf_gen2_vf_get_pf2vf_offset(u32 i)
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static u32 adf_gen2_vf_get_pf2vf_offset(u32 i)
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{
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return ADF_GEN2_VF_PF2VF_OFFSET;
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}
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EXPORT_SYMBOL_GPL(adf_gen2_vf_get_pf2vf_offset);
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u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_addr)
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static u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_addr)
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{
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u32 errsou3, errmsk3, vf_int_mask;
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@ -39,9 +38,9 @@ u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_addr)
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return vf_int_mask;
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}
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EXPORT_SYMBOL_GPL(adf_gen2_get_vf2pf_sources);
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void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
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static void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr,
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u32 vf_mask)
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{
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/* Enable VF2PF Messaging Ints - VFs 0 through 15 per vf_mask[15:0] */
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if (vf_mask & 0xFFFF) {
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@ -50,9 +49,9 @@ void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
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}
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}
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EXPORT_SYMBOL_GPL(adf_gen2_enable_vf2pf_interrupts);
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void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
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static void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr,
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u32 vf_mask)
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{
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/* Disable VF2PF interrupts for VFs 0 through 15 per vf_mask[15:0] */
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if (vf_mask & 0xFFFF) {
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@ -61,4 +60,20 @@ void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
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}
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}
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EXPORT_SYMBOL_GPL(adf_gen2_disable_vf2pf_interrupts);
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void adf_gen2_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops)
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{
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pfvf_ops->enable_comms = adf_enable_pf2vf_comms;
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pfvf_ops->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset;
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pfvf_ops->get_vf2pf_sources = adf_gen2_get_vf2pf_sources;
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pfvf_ops->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts;
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pfvf_ops->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts;
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}
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EXPORT_SYMBOL_GPL(adf_gen2_init_pf_pfvf_ops);
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void adf_gen2_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops)
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{
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pfvf_ops->enable_comms = adf_enable_vf2pf_comms;
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pfvf_ops->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset;
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}
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EXPORT_SYMBOL_GPL(adf_gen2_init_vf_pfvf_ops);
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@ -11,10 +11,19 @@
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#define ADF_GEN2_ERRMSK3 (0x3A000 + 0x1C)
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#define ADF_GEN2_ERRMSK5 (0x3A000 + 0xDC)
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u32 adf_gen2_pf_get_pf2vf_offset(u32 i);
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u32 adf_gen2_vf_get_pf2vf_offset(u32 i);
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u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_bar);
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void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask);
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void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask);
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#if defined(CONFIG_PCI_IOV)
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void adf_gen2_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops);
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void adf_gen2_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops);
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#else
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static inline void adf_gen2_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops)
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{
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pfvf_ops->enable_comms = adf_pfvf_comms_disabled;
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}
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static inline void adf_gen2_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops)
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{
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pfvf_ops->enable_comms = adf_pfvf_comms_disabled;
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}
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#endif
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#endif /* ADF_GEN2_PFVF_H */
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@ -117,7 +117,7 @@ int adf_dev_init(struct adf_accel_dev *accel_dev)
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hw_data->enable_ints(accel_dev);
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hw_data->enable_error_correction(accel_dev);
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ret = hw_data->enable_pfvf_comms(accel_dev);
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ret = hw_data->pfvf_ops.enable_comms(accel_dev);
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if (ret)
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return ret;
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@ -64,7 +64,7 @@ void adf_enable_vf2pf_interrupts(struct adf_accel_dev *accel_dev, u32 vf_mask)
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unsigned long flags;
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spin_lock_irqsave(&accel_dev->pf.vf2pf_ints_lock, flags);
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hw_data->enable_vf2pf_interrupts(pmisc_addr, vf_mask);
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hw_data->pfvf_ops.enable_vf2pf_interrupts(pmisc_addr, vf_mask);
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spin_unlock_irqrestore(&accel_dev->pf.vf2pf_ints_lock, flags);
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}
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@ -77,7 +77,7 @@ void adf_disable_vf2pf_interrupts(struct adf_accel_dev *accel_dev, u32 vf_mask)
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unsigned long flags;
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spin_lock_irqsave(&accel_dev->pf.vf2pf_ints_lock, flags);
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hw_data->disable_vf2pf_interrupts(pmisc_addr, vf_mask);
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hw_data->pfvf_ops.disable_vf2pf_interrupts(pmisc_addr, vf_mask);
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spin_unlock_irqrestore(&accel_dev->pf.vf2pf_ints_lock, flags);
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}
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@ -90,7 +90,7 @@ static void adf_disable_vf2pf_interrupts_irq(struct adf_accel_dev *accel_dev,
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void __iomem *pmisc_addr = pmisc->virt_addr;
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spin_lock(&accel_dev->pf.vf2pf_ints_lock);
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hw_data->disable_vf2pf_interrupts(pmisc_addr, vf_mask);
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hw_data->pfvf_ops.disable_vf2pf_interrupts(pmisc_addr, vf_mask);
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spin_unlock(&accel_dev->pf.vf2pf_ints_lock);
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}
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@ -104,7 +104,7 @@ static bool adf_handle_vf2pf_int(struct adf_accel_dev *accel_dev)
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unsigned long vf_mask;
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/* Get the interrupt sources triggered by VFs */
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vf_mask = hw_data->get_vf2pf_sources(pmisc_addr);
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vf_mask = hw_data->pfvf_ops.get_vf2pf_sources(pmisc_addr);
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if (vf_mask) {
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struct adf_accel_vf_info *vf_info;
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@ -29,7 +29,7 @@ static int adf_iov_putmsg(struct adf_accel_dev *accel_dev, u32 msg, u8 vf_nr)
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int ret;
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if (accel_dev->is_vf) {
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pf2vf_offset = hw_data->get_pf2vf_offset(0);
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pf2vf_offset = hw_data->pfvf_ops.get_pf2vf_offset(0);
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lock = &accel_dev->vf.vf2pf_lock;
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local_in_use_mask = ADF_VF2PF_IN_USE_BY_VF_MASK;
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local_in_use_pattern = ADF_VF2PF_IN_USE_BY_VF;
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@ -37,7 +37,7 @@ static int adf_iov_putmsg(struct adf_accel_dev *accel_dev, u32 msg, u8 vf_nr)
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remote_in_use_pattern = ADF_PF2VF_IN_USE_BY_PF;
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int_bit = ADF_VF2PF_INT;
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} else {
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pf2vf_offset = hw_data->get_pf2vf_offset(vf_nr);
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pf2vf_offset = hw_data->pfvf_ops.get_pf2vf_offset(vf_nr);
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lock = &accel_dev->pf.vf_info[vf_nr].pf2vf_lock;
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local_in_use_mask = ADF_PF2VF_IN_USE_BY_PF_MASK;
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local_in_use_pattern = ADF_PF2VF_IN_USE_BY_PF;
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@ -258,7 +258,7 @@ bool adf_recv_and_handle_vf2pf_msg(struct adf_accel_dev *accel_dev, u32 vf_nr)
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u32 msg, resp = 0;
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||||
/* Read message from the VF */
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||||
msg = ADF_CSR_RD(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr));
|
||||
msg = ADF_CSR_RD(pmisc_addr, hw_data->pfvf_ops.get_pf2vf_offset(vf_nr));
|
||||
if (!(msg & ADF_VF2PF_INT)) {
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||||
dev_info(&GET_DEV(accel_dev),
|
||||
"Spurious VF2PF interrupt, msg %X. Ignored\n", msg);
|
||||
|
@ -275,7 +275,7 @@ bool adf_recv_and_handle_vf2pf_msg(struct adf_accel_dev *accel_dev, u32 vf_nr)
|
|||
|
||||
/* To ACK, clear the VF2PFINT bit */
|
||||
msg &= ~ADF_VF2PF_INT;
|
||||
ADF_CSR_WR(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr), msg);
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||||
ADF_CSR_WR(pmisc_addr, hw_data->pfvf_ops.get_pf2vf_offset(vf_nr), msg);
|
||||
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if (adf_handle_vf2pf_msg(accel_dev, vf_nr, msg, &resp))
|
||||
return false;
|
||||
|
|
|
@ -70,7 +70,7 @@ static int adf_enable_sriov(struct adf_accel_dev *accel_dev)
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|||
hw_data->configure_iov_threads(accel_dev, true);
|
||||
|
||||
/* Enable VF to PF interrupts for all VFs */
|
||||
if (hw_data->get_pf2vf_offset)
|
||||
if (hw_data->pfvf_ops.get_pf2vf_offset)
|
||||
adf_enable_vf2pf_interrupts(accel_dev, BIT_ULL(totalvfs) - 1);
|
||||
|
||||
/*
|
||||
|
@ -100,13 +100,13 @@ void adf_disable_sriov(struct adf_accel_dev *accel_dev)
|
|||
if (!accel_dev->pf.vf_info)
|
||||
return;
|
||||
|
||||
if (hw_data->get_pf2vf_offset)
|
||||
if (hw_data->pfvf_ops.get_pf2vf_offset)
|
||||
adf_pf2vf_notify_restarting(accel_dev);
|
||||
|
||||
pci_disable_sriov(accel_to_pci_dev(accel_dev));
|
||||
|
||||
/* Disable VF to PF interrupts */
|
||||
if (hw_data->get_pf2vf_offset)
|
||||
if (hw_data->pfvf_ops.get_pf2vf_offset)
|
||||
adf_disable_vf2pf_interrupts(accel_dev, GENMASK(31, 0));
|
||||
|
||||
/* Clear Valid bits in AE Thread to PCIe Function Mapping */
|
||||
|
|
|
@ -81,7 +81,7 @@ bool adf_recv_and_handle_pf2vf_msg(struct adf_accel_dev *accel_dev)
|
|||
struct adf_bar *pmisc =
|
||||
&GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
|
||||
void __iomem *pmisc_bar_addr = pmisc->virt_addr;
|
||||
u32 offset = hw_data->get_pf2vf_offset(0);
|
||||
u32 offset = hw_data->pfvf_ops.get_pf2vf_offset(0);
|
||||
u32 msg;
|
||||
|
||||
/* Read the message from PF */
|
||||
|
|
|
@ -215,14 +215,13 @@ void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
|
|||
hw_data->get_arb_mapping = adf_get_arbiter_mapping;
|
||||
hw_data->enable_ints = adf_enable_ints;
|
||||
hw_data->reset_device = adf_reset_sbr;
|
||||
hw_data->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset;
|
||||
hw_data->get_vf2pf_sources = get_vf2pf_sources;
|
||||
hw_data->enable_vf2pf_interrupts = enable_vf2pf_interrupts;
|
||||
hw_data->disable_vf2pf_interrupts = disable_vf2pf_interrupts;
|
||||
hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms;
|
||||
hw_data->disable_iov = adf_disable_sriov;
|
||||
hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
|
||||
|
||||
adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
|
||||
hw_data->pfvf_ops.get_vf2pf_sources = get_vf2pf_sources;
|
||||
hw_data->pfvf_ops.enable_vf2pf_interrupts = enable_vf2pf_interrupts;
|
||||
hw_data->pfvf_ops.disable_vf2pf_interrupts = disable_vf2pf_interrupts;
|
||||
adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
|
||||
}
|
||||
|
||||
|
|
|
@ -82,13 +82,12 @@ void adf_init_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data)
|
|||
hw_data->get_num_aes = get_num_aes;
|
||||
hw_data->get_etr_bar_id = get_etr_bar_id;
|
||||
hw_data->get_misc_bar_id = get_misc_bar_id;
|
||||
hw_data->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset;
|
||||
hw_data->get_sku = get_sku;
|
||||
hw_data->enable_ints = adf_vf_void_noop;
|
||||
hw_data->enable_pfvf_comms = adf_enable_vf2pf_comms;
|
||||
hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
|
||||
hw_data->dev_class->instances++;
|
||||
adf_devmgr_update_class_index(hw_data);
|
||||
adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
|
||||
adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
|
||||
}
|
||||
|
||||
|
|
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