ARM: dts: ls1021a: add PCIe dts node
LS1021a contains two PCIe controllers. The patch adds their node to dts file. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Коммит
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@ -560,5 +560,49 @@
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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};
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pcie@3400000 {
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compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
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0x40 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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fsl,pcie-scfg = <&scfg 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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};
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pcie@3500000 {
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compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
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reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
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0x48 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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fsl,pcie-scfg = <&scfg 1>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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