drm/i915: Retry DP aux_ch communications with a different clock after failure
The w/a db makes the recommendation to both use a non-default value for the initial clock and then to retry with an alternative clock for Haswell with the Lakeport PCH. "On LPT:H, use a divider value of 63 decimal (03Fh). If there is a failure, retry at least three times with 63, then retry at least three times with 72 decimal (048h)." Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson
Daniel Vetter
Родитель
b8f102e8bf
Коммит
bc86625a4f
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@ -276,7 +276,8 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
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return status;
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}
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static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp)
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static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
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int index)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = intel_dig_port->base.base.dev;
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@ -290,22 +291,27 @@ static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp)
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* clock divider.
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*/
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if (IS_VALLEYVIEW(dev)) {
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return 100;
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return index ? 0 : 100;
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} else if (intel_dig_port->port == PORT_A) {
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if (index)
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return 0;
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if (HAS_DDI(dev))
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return DIV_ROUND_CLOSEST(
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intel_ddi_get_cdclk_freq(dev_priv), 2000);
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return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
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else if (IS_GEN6(dev) || IS_GEN7(dev))
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return 200; /* SNB & IVB eDP input clock at 400Mhz */
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else
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return 225; /* eDP input clock at 450Mhz */
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} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
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/* Workaround for non-ULT HSW */
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return 74;
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switch (index) {
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case 0: return 63;
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case 1: return 72;
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default: return 0;
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}
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} else if (HAS_PCH_SPLIT(dev)) {
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return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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} else {
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return intel_hrawclk(dev) / 2;
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return index ? 0 :intel_hrawclk(dev) / 2;
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}
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}
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@ -319,10 +325,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
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uint32_t ch_data = ch_ctl + 4;
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uint32_t aux_clock_divider;
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int i, ret, recv_bytes;
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uint32_t status;
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uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp);
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int try, precharge;
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int try, precharge, clock = 0;
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bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
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/* dp aux is extremely sensitive to irq latency, hence request the
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@ -353,37 +359,41 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
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goto out;
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}
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/* Must try at least 3 times according to DP spec */
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for (try = 0; try < 5; try++) {
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/* Load the send data into the aux channel data registers */
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for (i = 0; i < send_bytes; i += 4)
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I915_WRITE(ch_data + i,
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pack_aux(send + i, send_bytes - i));
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while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
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/* Must try at least 3 times according to DP spec */
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for (try = 0; try < 5; try++) {
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/* Load the send data into the aux channel data registers */
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for (i = 0; i < send_bytes; i += 4)
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I915_WRITE(ch_data + i,
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pack_aux(send + i, send_bytes - i));
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/* Send the command and wait for it to complete */
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I915_WRITE(ch_ctl,
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DP_AUX_CH_CTL_SEND_BUSY |
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(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
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DP_AUX_CH_CTL_TIME_OUT_400us |
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(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
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DP_AUX_CH_CTL_DONE |
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DP_AUX_CH_CTL_TIME_OUT_ERROR |
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DP_AUX_CH_CTL_RECEIVE_ERROR);
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/* Send the command and wait for it to complete */
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I915_WRITE(ch_ctl,
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DP_AUX_CH_CTL_SEND_BUSY |
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(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
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DP_AUX_CH_CTL_TIME_OUT_400us |
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(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
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DP_AUX_CH_CTL_DONE |
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DP_AUX_CH_CTL_TIME_OUT_ERROR |
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DP_AUX_CH_CTL_RECEIVE_ERROR);
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status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
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status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
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/* Clear done status and any errors */
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I915_WRITE(ch_ctl,
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status |
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DP_AUX_CH_CTL_DONE |
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DP_AUX_CH_CTL_TIME_OUT_ERROR |
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DP_AUX_CH_CTL_RECEIVE_ERROR);
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/* Clear done status and any errors */
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I915_WRITE(ch_ctl,
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status |
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DP_AUX_CH_CTL_DONE |
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DP_AUX_CH_CTL_TIME_OUT_ERROR |
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DP_AUX_CH_CTL_RECEIVE_ERROR);
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if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
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DP_AUX_CH_CTL_RECEIVE_ERROR))
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continue;
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if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
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DP_AUX_CH_CTL_RECEIVE_ERROR))
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continue;
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if (status & DP_AUX_CH_CTL_DONE)
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break;
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}
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if (status & DP_AUX_CH_CTL_DONE)
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break;
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}
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@ -1453,7 +1463,7 @@ static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp);
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uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
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int precharge = 0x3;
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int msg_size = 5; /* Header(4) + Message(1) */
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