drm/i915: Merge legacy+execlists context structs
struct intel_context contains two substructs, one for the legacy RCS and one for every execlists engine. Since legacy RCS is a subset of the execlists engine support, just combine the two substructs. v2: Only pin the default context for legacy mode (the object only exists for legacy, but adding i915.enable_execlists provides symmetry with the cleanup functions). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1464098023-3294-8-git-send-email-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
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Коммит
bca44d8055
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@ -199,13 +199,6 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
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seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
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}
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static void describe_ctx(struct seq_file *m, struct i915_gem_context *ctx)
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{
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seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
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seq_putc(m, ctx->remap_slice ? 'R' : 'r');
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seq_putc(m, ' ');
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}
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static int i915_gem_object_list_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = m->private;
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@ -2001,7 +1994,6 @@ static int i915_context_status(struct seq_file *m, void *unused)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_engine_cs *engine;
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struct i915_gem_context *ctx;
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enum intel_engine_id id;
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int ret;
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ret = mutex_lock_interruptible(&dev->struct_mutex);
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@ -2009,10 +2001,6 @@ static int i915_context_status(struct seq_file *m, void *unused)
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return ret;
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list_for_each_entry(ctx, &dev_priv->context_list, link) {
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if (!i915.enable_execlists &&
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ctx->legacy_hw_ctx.rcs_state == NULL)
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continue;
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seq_printf(m, "HW context %u ", ctx->hw_id);
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if (IS_ERR(ctx->file_priv)) {
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seq_puts(m, "(deleted) ");
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@ -2030,25 +2018,19 @@ static int i915_context_status(struct seq_file *m, void *unused)
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seq_puts(m, "(kernel) ");
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}
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describe_ctx(m, ctx);
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seq_putc(m, ctx->remap_slice ? 'R' : 'r');
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seq_putc(m, '\n');
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if (i915.enable_execlists) {
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for_each_engine(engine, dev_priv) {
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struct intel_context *ce = &ctx->engine[engine->id];
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seq_printf(m, "%s: ", engine->name);
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seq_putc(m, ce->initialised ? 'I' : 'i');
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if (ce->state)
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describe_obj(m, ce->state);
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if (ce->ringbuf)
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describe_ctx_ringbuf(m, ce->ringbuf);
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seq_putc(m, '\n');
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for_each_engine_id(engine, dev_priv, id) {
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struct drm_i915_gem_object *ctx_obj =
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ctx->engine[id].state;
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struct intel_ringbuffer *ringbuf =
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ctx->engine[id].ringbuf;
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seq_printf(m, "%s: ", engine->name);
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if (ctx_obj)
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describe_obj(m, ctx_obj);
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if (ringbuf)
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describe_ctx_ringbuf(m, ringbuf);
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seq_putc(m, '\n');
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}
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} else {
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describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
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}
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seq_putc(m, '\n');
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@ -2063,10 +2045,10 @@ static void i915_dump_lrc_obj(struct seq_file *m,
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struct i915_gem_context *ctx,
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struct intel_engine_cs *engine)
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{
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struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
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struct page *page;
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uint32_t *reg_state;
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int j;
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struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
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unsigned long ggtt_offset = 0;
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seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
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@ -862,13 +862,6 @@ struct i915_gem_context {
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/* Unique identifier for this context, used by the hw for tracking */
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unsigned hw_id;
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/* Legacy ring buffer submission */
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struct {
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struct drm_i915_gem_object *rcs_state;
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bool initialized;
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} legacy_hw_ctx;
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/* Execlists */
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struct intel_context {
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struct drm_i915_gem_object *state;
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struct intel_ringbuffer *ringbuf;
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@ -152,13 +152,11 @@ static void i915_gem_context_clean(struct i915_gem_context *ctx)
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void i915_gem_context_free(struct kref *ctx_ref)
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{
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struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
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int i;
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lockdep_assert_held(&ctx->i915->dev->struct_mutex);
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trace_i915_context_free(ctx);
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if (i915.enable_execlists)
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intel_lr_context_free(ctx);
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/*
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* This context is going away and we need to remove all VMAs still
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* around. This is to handle imported shared objects for which
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@ -168,8 +166,19 @@ void i915_gem_context_free(struct kref *ctx_ref)
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i915_ppgtt_put(ctx->ppgtt);
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if (ctx->legacy_hw_ctx.rcs_state)
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drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);
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for (i = 0; i < I915_NUM_ENGINES; i++) {
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struct intel_context *ce = &ctx->engine[i];
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if (!ce->state)
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continue;
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WARN_ON(ce->pin_count);
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if (ce->ringbuf)
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intel_ringbuffer_free(ce->ringbuf);
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drm_gem_object_unreference(&ce->state->base);
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}
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list_del(&ctx->link);
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ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
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@ -266,7 +275,7 @@ __create_hw_context(struct drm_device *dev,
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ret = PTR_ERR(obj);
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goto err_out;
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}
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ctx->legacy_hw_ctx.rcs_state = obj;
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ctx->engine[RCS].state = obj;
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}
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/* Default context will never have a file_priv */
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@ -336,8 +345,11 @@ static void i915_gem_context_unpin(struct i915_gem_context *ctx,
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if (i915.enable_execlists) {
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intel_lr_context_unpin(ctx, engine);
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} else {
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if (engine->id == RCS && ctx->legacy_hw_ctx.rcs_state)
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i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
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struct intel_context *ce = &ctx->engine[engine->id];
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if (ce->state)
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i915_gem_object_ggtt_unpin(ce->state);
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i915_gem_context_unreference(ctx);
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}
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}
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@ -401,7 +413,7 @@ int i915_gem_context_init(struct drm_device *dev)
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return PTR_ERR(ctx);
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}
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if (ctx->legacy_hw_ctx.rcs_state) {
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if (!i915.enable_execlists && ctx->engine[RCS].state) {
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int ret;
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/* We may need to do things with the shrinker which
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@ -411,7 +423,7 @@ int i915_gem_context_init(struct drm_device *dev)
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* be available. To avoid this we always pin the default
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* context.
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*/
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ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
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ret = i915_gem_obj_ggtt_pin(ctx->engine[RCS].state,
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get_context_alignment(dev_priv), 0);
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if (ret) {
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DRM_ERROR("Failed to pinned default global context (error %d)\n",
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@ -436,15 +448,17 @@ void i915_gem_context_lost(struct drm_i915_private *dev_priv)
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lockdep_assert_held(&dev_priv->dev->struct_mutex);
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for_each_engine(engine, dev_priv) {
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if (engine->last_context == NULL)
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continue;
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if (engine->last_context) {
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i915_gem_context_unpin(engine->last_context, engine);
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engine->last_context = NULL;
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}
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i915_gem_context_unpin(engine->last_context, engine);
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engine->last_context = NULL;
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/* Force the GPU state to be reinitialised on enabling */
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dev_priv->kernel_context->engine[engine->id].initialised =
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engine->init_context == NULL;
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}
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/* Force the GPU state to be reinitialised on enabling */
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dev_priv->kernel_context->legacy_hw_ctx.initialized = false;
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dev_priv->kernel_context->remap_slice = ALL_L3_SLICES(dev_priv);
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}
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@ -455,8 +469,8 @@ void i915_gem_context_fini(struct drm_device *dev)
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lockdep_assert_held(&dev->struct_mutex);
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if (dctx->legacy_hw_ctx.rcs_state)
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i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
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if (!i915.enable_execlists && dctx->engine[RCS].state)
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i915_gem_object_ggtt_unpin(dctx->engine[RCS].state);
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i915_gem_context_unreference(dctx);
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dev_priv->kernel_context = NULL;
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@ -564,7 +578,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
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intel_ring_emit(engine, MI_NOOP);
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intel_ring_emit(engine, MI_SET_CONTEXT);
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intel_ring_emit(engine,
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i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) |
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i915_gem_obj_ggtt_offset(req->ctx->engine[RCS].state) |
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flags);
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/*
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* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
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@ -641,7 +655,7 @@ static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
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if (to->remap_slice)
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return false;
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if (!to->legacy_hw_ctx.initialized)
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if (!to->engine[RCS].initialised)
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return false;
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if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
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@ -706,7 +720,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
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return 0;
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/* Trying to pin first makes error handling easier. */
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ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
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ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state,
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get_context_alignment(engine->i915),
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0);
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if (ret)
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@ -729,7 +743,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
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*
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* XXX: We need a real interface to do this instead of trickery.
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*/
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ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false);
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ret = i915_gem_object_set_to_gtt_domain(to->engine[RCS].state, false);
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if (ret)
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goto unpin_out;
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@ -744,7 +758,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
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goto unpin_out;
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}
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if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to))
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if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
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/* NB: If we inhibit the restore, the context is not allowed to
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* die because future work may end up depending on valid address
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* space. This means we must enforce that a page table load
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@ -768,8 +782,8 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
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* MI_SET_CONTEXT instead of when the next seqno has completed.
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*/
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if (from != NULL) {
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from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req);
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from->engine[RCS].state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->engine[RCS].state), req);
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/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
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* whole damn pipeline, we don't need to explicitly mark the
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* object dirty. The only exception is that the context must be
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@ -777,10 +791,10 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
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* able to defer doing this until we know the object would be
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* swapped, but there is no way to do that yet.
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*/
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from->legacy_hw_ctx.rcs_state->dirty = 1;
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from->engine[RCS].state->dirty = 1;
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/* obj is kept alive until the next request by its active ref */
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i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state);
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i915_gem_object_ggtt_unpin(from->engine[RCS].state);
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i915_gem_context_unreference(from);
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}
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i915_gem_context_reference(to);
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@ -815,19 +829,19 @@ static int do_rcs_switch(struct drm_i915_gem_request *req)
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to->remap_slice &= ~(1<<i);
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}
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if (!to->legacy_hw_ctx.initialized) {
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if (!to->engine[RCS].initialised) {
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if (engine->init_context) {
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ret = engine->init_context(req);
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if (ret)
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return ret;
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}
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to->legacy_hw_ctx.initialized = true;
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to->engine[RCS].initialised = true;
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}
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return 0;
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unpin_out:
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i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state);
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i915_gem_object_ggtt_unpin(to->engine[RCS].state);
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return ret;
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}
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@ -851,8 +865,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
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WARN_ON(i915.enable_execlists);
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lockdep_assert_held(&req->i915->dev->struct_mutex);
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if (engine->id != RCS ||
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req->ctx->legacy_hw_ctx.rcs_state == NULL) {
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if (!req->ctx->engine[engine->id].state) {
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struct i915_gem_context *to = req->ctx;
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struct i915_hw_ppgtt *ppgtt =
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to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
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@ -2409,31 +2409,6 @@ populate_lr_context(struct i915_gem_context *ctx,
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return 0;
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}
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/**
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* intel_lr_context_free() - free the LRC specific bits of a context
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* @ctx: the LR context to free.
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*
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* The real context freeing is done in i915_gem_context_free: this only
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* takes care of the bits that are LRC related: the per-engine backing
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* objects and the logical ringbuffer.
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*/
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void intel_lr_context_free(struct i915_gem_context *ctx)
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{
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int i;
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for (i = I915_NUM_ENGINES; --i >= 0; ) {
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struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
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struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
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if (!ctx_obj)
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continue;
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WARN_ON(ctx->engine[i].pin_count);
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intel_ringbuffer_free(ringbuf);
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drm_gem_object_unreference(&ctx_obj->base);
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}
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}
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/**
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* intel_lr_context_size() - return the size of the context for an engine
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* @ring: which engine to find the context size for
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@ -2494,7 +2469,6 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
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struct intel_ringbuffer *ringbuf;
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int ret;
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WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
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WARN_ON(ce->state);
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context_size = round_up(intel_lr_context_size(engine), 4096);
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@ -101,7 +101,6 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
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struct i915_gem_context;
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void intel_lr_context_free(struct i915_gem_context *ctx);
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uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
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void intel_lr_context_unpin(struct i915_gem_context *ctx,
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struct intel_engine_cs *engine);
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