PCI: mobiveil: Unify register accessors
It is confusing to have two sets of functions to read/write registers, some with csr_readl()/csr_writel(), while others with read_paged_register()/write_paged_register(). In the register space the lower 3KB of 4KB PCIe configure space can be accessed directly and higher 1KB through a simple paging mechanism. Unify the register accessors in csr_readl() and csr_writel() by comparing the register offset with page access boundary 3KB in the accessor internal so that the paging mechanism is hidden behind the csr_read()/write() common function calls. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
This commit is contained in:
Hou Zhiqiang
Lorenzo Pieralisi
Родитель
a188339ca5
Коммит
bcbe0d9a8d
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@ -47,7 +47,6 @@
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#define PAGE_SEL_SHIFT 13
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#define PAGE_SEL_MASK 0x3f
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#define PAGE_LO_MASK 0x3ff
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#define PAGE_SEL_EN 0xc00
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#define PAGE_SEL_OFFSET_SHIFT 10
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#define PAB_AXI_PIO_CTRL 0x0840
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@ -117,6 +116,12 @@
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#define LINK_WAIT_MIN 90000
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#define LINK_WAIT_MAX 100000
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#define PAGED_ADDR_BNDRY 0xc00
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#define OFFSET_TO_PAGE_ADDR(off) \
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((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
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#define OFFSET_TO_PAGE_IDX(off) \
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((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
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struct mobiveil_msi { /* MSI information */
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struct mutex lock; /* protect bitmap variable */
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struct irq_domain *msi_domain;
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@ -145,15 +150,119 @@ struct mobiveil_pcie {
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struct mobiveil_msi msi;
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};
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static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,
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const u32 reg)
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/*
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* mobiveil_pcie_sel_page - routine to access paged register
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*
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* Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
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* for this scheme to work extracted higher 6 bits of the offset will be
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* written to pg_sel field of PAB_CTRL register and rest of the lower 10
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* bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
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*/
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static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
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{
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writel_relaxed(value, pcie->csr_axi_slave_base + reg);
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u32 val;
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val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
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val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
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val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
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writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
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}
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static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)
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static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
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{
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return readl_relaxed(pcie->csr_axi_slave_base + reg);
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if (off < PAGED_ADDR_BNDRY) {
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/* For directly accessed registers, clear the pg_sel field */
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mobiveil_pcie_sel_page(pcie, 0);
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return pcie->csr_axi_slave_base + off;
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}
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mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
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return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
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}
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static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
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{
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if ((uintptr_t)addr & (size - 1)) {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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switch (size) {
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case 4:
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*val = readl(addr);
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break;
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case 2:
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*val = readw(addr);
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break;
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case 1:
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*val = readb(addr);
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break;
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default:
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
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{
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if ((uintptr_t)addr & (size - 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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switch (size) {
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case 4:
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writel(val, addr);
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break;
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case 2:
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writew(val, addr);
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break;
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case 1:
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writeb(val, addr);
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break;
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default:
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
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{
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void *addr;
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u32 val;
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int ret;
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addr = mobiveil_pcie_comp_addr(pcie, off);
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ret = mobiveil_pcie_read(addr, size, &val);
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if (ret)
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dev_err(&pcie->pdev->dev, "read CSR address failed\n");
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return val;
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}
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static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
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{
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void *addr;
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int ret;
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addr = mobiveil_pcie_comp_addr(pcie, off);
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ret = mobiveil_pcie_write(addr, size, val);
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if (ret)
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dev_err(&pcie->pdev->dev, "write CSR address failed\n");
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}
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static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
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{
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return csr_read(pcie, off, 0x4);
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}
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static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
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{
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csr_write(pcie, val, off, 0x4);
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}
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static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
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@ -342,45 +451,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
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return 0;
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}
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/*
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* select_paged_register - routine to access paged register of root complex
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*
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* registers of RC are paged, for this scheme to work
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* extracted higher 6 bits of the offset will be written to pg_sel
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* field of PAB_CTRL register and rest of the lower 10 bits enabled with
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* PAGE_SEL_EN are used as offset of the register.
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*/
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static void select_paged_register(struct mobiveil_pcie *pcie, u32 offset)
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{
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int pab_ctrl_dw, pg_sel;
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/* clear pg_sel field */
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pab_ctrl_dw = csr_readl(pcie, PAB_CTRL);
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pab_ctrl_dw = (pab_ctrl_dw & ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT));
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/* set pg_sel field */
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pg_sel = (offset >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK;
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pab_ctrl_dw |= ((pg_sel << PAGE_SEL_SHIFT));
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csr_writel(pcie, pab_ctrl_dw, PAB_CTRL);
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}
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static void write_paged_register(struct mobiveil_pcie *pcie,
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u32 val, u32 offset)
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{
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u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
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select_paged_register(pcie, offset);
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csr_writel(pcie, val, off);
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}
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static u32 read_paged_register(struct mobiveil_pcie *pcie, u32 offset)
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{
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u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
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select_paged_register(pcie, offset);
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return csr_readl(pcie, off);
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}
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static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
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int pci_addr, u32 type, u64 size)
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{
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@ -397,19 +467,19 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
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pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
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csr_writel(pcie,
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pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
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amap_ctrl_dw = read_paged_register(pcie, PAB_PEX_AMAP_CTRL(win_num));
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amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
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amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
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amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
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write_paged_register(pcie, amap_ctrl_dw | lower_32_bits(size64),
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csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
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PAB_PEX_AMAP_CTRL(win_num));
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write_paged_register(pcie, upper_32_bits(size64),
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csr_writel(pcie, upper_32_bits(size64),
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PAB_EXT_PEX_AMAP_SIZEN(win_num));
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write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
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write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
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write_paged_register(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
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csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
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csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
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csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
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}
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/*
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@ -437,8 +507,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
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csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
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lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
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write_paged_register(pcie, upper_32_bits(size64),
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PAB_EXT_AXI_AMAP_SIZE(win_num));
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csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
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/*
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* program AXI window base with appropriate value in
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