Merge 3.5-rc4 into staging-next
This picks up the staging changes made in 3.5-rc4 so that everyone can sync up properly. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman
Коммит
bcc66c0b88
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.mailmap
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.mailmap
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@ -111,6 +111,7 @@ Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
|
|||
Uwe Kleine-König <ukl@pengutronix.de>
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||||
Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
|
||||
Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
|
||||
Viresh Kumar <viresh.linux@gmail.com> <viresh.kumar@st.com>
|
||||
Takashi YOSHII <takashi.yoshii.zj@renesas.com>
|
||||
Yusuke Goda <goda.yusuke@renesas.com>
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||||
Gustavo Padovan <gustavo@las.ic.unicamp.br>
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||||
|
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|
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@ -60,4 +60,4 @@ Introduction
|
|||
Document Author
|
||||
---------------
|
||||
|
||||
Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
|
||||
Viresh Kumar <viresh.linux@gmail.com>, (c) 2010-2012 ST Microelectronics
|
||||
|
|
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|
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@ -0,0 +1,93 @@
|
|||
Pinctrl-based I2C Bus Mux
|
||||
|
||||
This binding describes an I2C bus multiplexer that uses pin multiplexing to
|
||||
route the I2C signals, and represents the pin multiplexing configuration
|
||||
using the pinctrl device tree bindings.
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||||
|
||||
+-----+ +-----+
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||||
| dev | | dev |
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||||
+------------------------+ +-----+ +-----+
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||||
| SoC | | |
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||||
| /----|------+--------+
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||||
| +---+ +------+ | child bus A, on first set of pins
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||||
| |I2C|---|Pinmux| |
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||||
| +---+ +------+ | child bus B, on second set of pins
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||||
| \----|------+--------+--------+
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||||
| | | | |
|
||||
+------------------------+ +-----+ +-----+ +-----+
|
||||
| dev | | dev | | dev |
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||||
+-----+ +-----+ +-----+
|
||||
|
||||
Required properties:
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||||
- compatible: i2c-mux-pinctrl
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||||
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
|
||||
port is connected to.
|
||||
|
||||
Also required are:
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||||
|
||||
* Standard pinctrl properties that specify the pin mux state for each child
|
||||
bus. See ../pinctrl/pinctrl-bindings.txt.
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||||
|
||||
* Standard I2C mux properties. See mux.txt in this directory.
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||||
|
||||
* I2C child bus nodes. See mux.txt in this directory.
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|
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For each named state defined in the pinctrl-names property, an I2C child bus
|
||||
will be created. I2C child bus numbers are assigned based on the index into
|
||||
the pinctrl-names property.
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|
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The only exception is that no bus will be created for a state named "idle". If
|
||||
such a state is defined, it must be the last entry in pinctrl-names. For
|
||||
example:
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|
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pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1
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||||
pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last)
|
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pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last)
|
||||
|
||||
Whenever an access is made to a device on a child bus, the relevant pinctrl
|
||||
state will be programmed into hardware.
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||||
|
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If an idle state is defined, whenever an access is not being made to a device
|
||||
on a child bus, the idle pinctrl state will be programmed into hardware.
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|
||||
If an idle state is not defined, the most recently used pinctrl state will be
|
||||
left programmed into hardware whenever no access is being made of a device on
|
||||
a child bus.
|
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|
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Example:
|
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|
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i2cmux {
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compatible = "i2c-mux-pinctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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|
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i2c-parent = <&i2c1>;
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pinctrl-names = "ddc", "pta", "idle";
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pinctrl-0 = <&state_i2cmux_ddc>;
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pinctrl-1 = <&state_i2cmux_pta>;
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pinctrl-2 = <&state_i2cmux_idle>;
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|
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i2c@0 {
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||||
reg = <0>;
|
||||
#address-cells = <1>;
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||||
#size-cells = <0>;
|
||||
|
||||
eeprom {
|
||||
compatible = "eeprom";
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||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eeprom {
|
||||
compatible = "eeprom";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -6,7 +6,9 @@ Supported chips:
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|||
Prefix: 'coretemp'
|
||||
CPUID: family 0x6, models 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
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||||
0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
|
||||
0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield)
|
||||
0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
|
||||
0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
|
||||
0x36 (Cedar Trail Atom)
|
||||
Datasheet: Intel 64 and IA-32 Architectures Software Developer's Manual
|
||||
Volume 3A: System Programming Guide
|
||||
http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
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||||
|
|
@ -52,6 +54,17 @@ Some information comes from ark.intel.com
|
|||
|
||||
Process Processor TjMax(C)
|
||||
|
||||
22nm Core i5/i7 Processors
|
||||
i7 3920XM, 3820QM, 3720QM, 3667U, 3520M 105
|
||||
i5 3427U, 3360M/3320M 105
|
||||
i7 3770/3770K 105
|
||||
i5 3570/3570K, 3550, 3470/3450 105
|
||||
i7 3770S 103
|
||||
i5 3570S/3550S, 3475S/3470S/3450S 103
|
||||
i7 3770T 94
|
||||
i5 3570T 94
|
||||
i5 3470T 91
|
||||
|
||||
32nm Core i3/i5/i7 Processors
|
||||
i7 660UM/640/620, 640LM/620, 620M, 610E 105
|
||||
i5 540UM/520/430, 540M/520/450/430 105
|
||||
|
|
@ -65,6 +78,11 @@ Process Processor TjMax(C)
|
|||
U3400 105
|
||||
P4505/P4500 90
|
||||
|
||||
32nm Atom Processors
|
||||
Z2460 90
|
||||
D2700/2550/2500 100
|
||||
N2850/2800/2650/2600 100
|
||||
|
||||
45nm Xeon Processors 5400 Quad-Core
|
||||
X5492, X5482, X5472, X5470, X5460, X5450 85
|
||||
E5472, E5462, E5450/40/30/20/10/05 85
|
||||
|
|
@ -85,6 +103,8 @@ Process Processor TjMax(C)
|
|||
N475/470/455/450 100
|
||||
N280/270 90
|
||||
330/230 125
|
||||
E680/660/640/620 90
|
||||
E680T/660T/640T/620T 110
|
||||
|
||||
45nm Core2 Processors
|
||||
Solo ULV SU3500/3300 100
|
||||
|
|
|
|||
|
|
@ -2543,6 +2543,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
|
||||
sched_debug [KNL] Enables verbose scheduler debug messages.
|
||||
|
||||
skew_tick= [KNL] Offset the periodic timer tick per cpu to mitigate
|
||||
xtime_lock contention on larger systems, and/or RCU lock
|
||||
contention on all systems with CONFIG_MAXSMP set.
|
||||
Format: { "0" | "1" }
|
||||
0 -- disable. (may be 1 via CONFIG_CMDLINE="skew_tick=1"
|
||||
1 -- enable.
|
||||
Note: increases power consumption, thus should only be
|
||||
enabled if running jitter sensitive (HPC/RT) workloads.
|
||||
|
||||
security= [SECURITY] Choose a security module to enable at boot.
|
||||
If this boot parameter is not specified, only the first
|
||||
security module asking for security registration will be
|
||||
|
|
|
|||
|
|
@ -10,8 +10,8 @@ Currently this network device driver is for all STM embedded MAC/GMAC
|
|||
(i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000
|
||||
FF1152AMT0221 D1215994A VIRTEX FPGA board.
|
||||
|
||||
DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether MAC 10/100
|
||||
Universal version 4.0 have been used for developing this driver.
|
||||
DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether
|
||||
MAC 10/100 Universal version 4.0 have been used for developing this driver.
|
||||
|
||||
This driver supports both the platform bus and PCI.
|
||||
|
||||
|
|
@ -54,27 +54,27 @@ net_device structure enabling the scatter/gather feature.
|
|||
When one or more packets are received, an interrupt happens. The interrupts
|
||||
are not queued so the driver has to scan all the descriptors in the ring during
|
||||
the receive process.
|
||||
This is based on NAPI so the interrupt handler signals only if there is work to be
|
||||
done, and it exits.
|
||||
This is based on NAPI so the interrupt handler signals only if there is work
|
||||
to be done, and it exits.
|
||||
Then the poll method will be scheduled at some future point.
|
||||
The incoming packets are stored, by the DMA, in a list of pre-allocated socket
|
||||
buffers in order to avoid the memcpy (Zero-copy).
|
||||
|
||||
4.3) Timer-Driver Interrupt
|
||||
Instead of having the device that asynchronously notifies the frame receptions, the
|
||||
driver configures a timer to generate an interrupt at regular intervals.
|
||||
Based on the granularity of the timer, the frames that are received by the device
|
||||
will experience different levels of latency. Some NICs have dedicated timer
|
||||
device to perform this task. STMMAC can use either the RTC device or the TMU
|
||||
channel 2 on STLinux platforms.
|
||||
Instead of having the device that asynchronously notifies the frame receptions,
|
||||
the driver configures a timer to generate an interrupt at regular intervals.
|
||||
Based on the granularity of the timer, the frames that are received by the
|
||||
device will experience different levels of latency. Some NICs have dedicated
|
||||
timer device to perform this task. STMMAC can use either the RTC device or the
|
||||
TMU channel 2 on STLinux platforms.
|
||||
The timers frequency can be passed to the driver as parameter; when change it,
|
||||
take care of both hardware capability and network stability/performance impact.
|
||||
Several performance tests on STM platforms showed this optimisation allows to spare
|
||||
the CPU while having the maximum throughput.
|
||||
Several performance tests on STM platforms showed this optimisation allows to
|
||||
spare the CPU while having the maximum throughput.
|
||||
|
||||
4.4) WOL
|
||||
Wake up on Lan feature through Magic and Unicast frames are supported for the GMAC
|
||||
core.
|
||||
Wake up on Lan feature through Magic and Unicast frames are supported for the
|
||||
GMAC core.
|
||||
|
||||
4.5) DMA descriptors
|
||||
Driver handles both normal and enhanced descriptors. The latter has been only
|
||||
|
|
@ -106,7 +106,8 @@ Several driver's information can be passed through the platform
|
|||
These are included in the include/linux/stmmac.h header file
|
||||
and detailed below as well:
|
||||
|
||||
struct plat_stmmacenet_data {
|
||||
struct plat_stmmacenet_data {
|
||||
char *phy_bus_name;
|
||||
int bus_id;
|
||||
int phy_addr;
|
||||
int interface;
|
||||
|
|
@ -124,19 +125,24 @@ and detailed below as well:
|
|||
void (*bus_setup)(void __iomem *ioaddr);
|
||||
int (*init)(struct platform_device *pdev);
|
||||
void (*exit)(struct platform_device *pdev);
|
||||
void *custom_cfg;
|
||||
void *custom_data;
|
||||
void *bsp_priv;
|
||||
};
|
||||
|
||||
Where:
|
||||
o phy_bus_name: phy bus name to attach to the stmmac.
|
||||
o bus_id: bus identifier.
|
||||
o phy_addr: the physical address can be passed from the platform.
|
||||
If it is set to -1 the driver will automatically
|
||||
detect it at run-time by probing all the 32 addresses.
|
||||
o interface: PHY device's interface.
|
||||
o mdio_bus_data: specific platform fields for the MDIO bus.
|
||||
o pbl: the Programmable Burst Length is maximum number of beats to
|
||||
o dma_cfg: internal DMA parameters
|
||||
o pbl: the Programmable Burst Length is maximum number of beats to
|
||||
be transferred in one DMA transaction.
|
||||
GMAC also enables the 4xPBL by default.
|
||||
o fixed_burst/mixed_burst/burst_len
|
||||
o clk_csr: fixed CSR Clock range selection.
|
||||
o has_gmac: uses the GMAC core.
|
||||
o enh_desc: if sets the MAC will use the enhanced descriptor structure.
|
||||
|
|
@ -160,8 +166,9 @@ Where:
|
|||
this is sometime necessary on some platforms (e.g. ST boxes)
|
||||
where the HW needs to have set some PIO lines or system cfg
|
||||
registers.
|
||||
o custom_cfg: this is a custom configuration that can be passed while
|
||||
initialising the resources.
|
||||
o custom_cfg/custom_data: this is a custom configuration that can be passed
|
||||
while initialising the resources.
|
||||
o bsp_priv: another private poiter.
|
||||
|
||||
For MDIO bus The we have:
|
||||
|
||||
|
|
@ -180,7 +187,6 @@ Where:
|
|||
o irqs: list of IRQs, one per PHY.
|
||||
o probed_phy_irq: if irqs is NULL, use this for probed PHY.
|
||||
|
||||
|
||||
For DMA engine we have the following internal fields that should be
|
||||
tuned according to the HW capabilities.
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,278 @@
|
|||
Frontswap provides a "transcendent memory" interface for swap pages.
|
||||
In some environments, dramatic performance savings may be obtained because
|
||||
swapped pages are saved in RAM (or a RAM-like device) instead of a swap disk.
|
||||
|
||||
(Note, frontswap -- and cleancache (merged at 3.0) -- are the "frontends"
|
||||
and the only necessary changes to the core kernel for transcendent memory;
|
||||
all other supporting code -- the "backends" -- is implemented as drivers.
|
||||
See the LWN.net article "Transcendent memory in a nutshell" for a detailed
|
||||
overview of frontswap and related kernel parts:
|
||||
https://lwn.net/Articles/454795/ )
|
||||
|
||||
Frontswap is so named because it can be thought of as the opposite of
|
||||
a "backing" store for a swap device. The storage is assumed to be
|
||||
a synchronous concurrency-safe page-oriented "pseudo-RAM device" conforming
|
||||
to the requirements of transcendent memory (such as Xen's "tmem", or
|
||||
in-kernel compressed memory, aka "zcache", or future RAM-like devices);
|
||||
this pseudo-RAM device is not directly accessible or addressable by the
|
||||
kernel and is of unknown and possibly time-varying size. The driver
|
||||
links itself to frontswap by calling frontswap_register_ops to set the
|
||||
frontswap_ops funcs appropriately and the functions it provides must
|
||||
conform to certain policies as follows:
|
||||
|
||||
An "init" prepares the device to receive frontswap pages associated
|
||||
with the specified swap device number (aka "type"). A "store" will
|
||||
copy the page to transcendent memory and associate it with the type and
|
||||
offset associated with the page. A "load" will copy the page, if found,
|
||||
from transcendent memory into kernel memory, but will NOT remove the page
|
||||
from from transcendent memory. An "invalidate_page" will remove the page
|
||||
from transcendent memory and an "invalidate_area" will remove ALL pages
|
||||
associated with the swap type (e.g., like swapoff) and notify the "device"
|
||||
to refuse further stores with that swap type.
|
||||
|
||||
Once a page is successfully stored, a matching load on the page will normally
|
||||
succeed. So when the kernel finds itself in a situation where it needs
|
||||
to swap out a page, it first attempts to use frontswap. If the store returns
|
||||
success, the data has been successfully saved to transcendent memory and
|
||||
a disk write and, if the data is later read back, a disk read are avoided.
|
||||
If a store returns failure, transcendent memory has rejected the data, and the
|
||||
page can be written to swap as usual.
|
||||
|
||||
If a backend chooses, frontswap can be configured as a "writethrough
|
||||
cache" by calling frontswap_writethrough(). In this mode, the reduction
|
||||
in swap device writes is lost (and also a non-trivial performance advantage)
|
||||
in order to allow the backend to arbitrarily "reclaim" space used to
|
||||
store frontswap pages to more completely manage its memory usage.
|
||||
|
||||
Note that if a page is stored and the page already exists in transcendent memory
|
||||
(a "duplicate" store), either the store succeeds and the data is overwritten,
|
||||
or the store fails AND the page is invalidated. This ensures stale data may
|
||||
never be obtained from frontswap.
|
||||
|
||||
If properly configured, monitoring of frontswap is done via debugfs in
|
||||
the /sys/kernel/debug/frontswap directory. The effectiveness of
|
||||
frontswap can be measured (across all swap devices) with:
|
||||
|
||||
failed_stores - how many store attempts have failed
|
||||
loads - how many loads were attempted (all should succeed)
|
||||
succ_stores - how many store attempts have succeeded
|
||||
invalidates - how many invalidates were attempted
|
||||
|
||||
A backend implementation may provide additional metrics.
|
||||
|
||||
FAQ
|
||||
|
||||
1) Where's the value?
|
||||
|
||||
When a workload starts swapping, performance falls through the floor.
|
||||
Frontswap significantly increases performance in many such workloads by
|
||||
providing a clean, dynamic interface to read and write swap pages to
|
||||
"transcendent memory" that is otherwise not directly addressable to the kernel.
|
||||
This interface is ideal when data is transformed to a different form
|
||||
and size (such as with compression) or secretly moved (as might be
|
||||
useful for write-balancing for some RAM-like devices). Swap pages (and
|
||||
evicted page-cache pages) are a great use for this kind of slower-than-RAM-
|
||||
but-much-faster-than-disk "pseudo-RAM device" and the frontswap (and
|
||||
cleancache) interface to transcendent memory provides a nice way to read
|
||||
and write -- and indirectly "name" -- the pages.
|
||||
|
||||
Frontswap -- and cleancache -- with a fairly small impact on the kernel,
|
||||
provides a huge amount of flexibility for more dynamic, flexible RAM
|
||||
utilization in various system configurations:
|
||||
|
||||
In the single kernel case, aka "zcache", pages are compressed and
|
||||
stored in local memory, thus increasing the total anonymous pages
|
||||
that can be safely kept in RAM. Zcache essentially trades off CPU
|
||||
cycles used in compression/decompression for better memory utilization.
|
||||
Benchmarks have shown little or no impact when memory pressure is
|
||||
low while providing a significant performance improvement (25%+)
|
||||
on some workloads under high memory pressure.
|
||||
|
||||
"RAMster" builds on zcache by adding "peer-to-peer" transcendent memory
|
||||
support for clustered systems. Frontswap pages are locally compressed
|
||||
as in zcache, but then "remotified" to another system's RAM. This
|
||||
allows RAM to be dynamically load-balanced back-and-forth as needed,
|
||||
i.e. when system A is overcommitted, it can swap to system B, and
|
||||
vice versa. RAMster can also be configured as a memory server so
|
||||
many servers in a cluster can swap, dynamically as needed, to a single
|
||||
server configured with a large amount of RAM... without pre-configuring
|
||||
how much of the RAM is available for each of the clients!
|
||||
|
||||
In the virtual case, the whole point of virtualization is to statistically
|
||||
multiplex physical resources acrosst the varying demands of multiple
|
||||
virtual machines. This is really hard to do with RAM and efforts to do
|
||||
it well with no kernel changes have essentially failed (except in some
|
||||
well-publicized special-case workloads).
|
||||
Specifically, the Xen Transcendent Memory backend allows otherwise
|
||||
"fallow" hypervisor-owned RAM to not only be "time-shared" between multiple
|
||||
virtual machines, but the pages can be compressed and deduplicated to
|
||||
optimize RAM utilization. And when guest OS's are induced to surrender
|
||||
underutilized RAM (e.g. with "selfballooning"), sudden unexpected
|
||||
memory pressure may result in swapping; frontswap allows those pages
|
||||
to be swapped to and from hypervisor RAM (if overall host system memory
|
||||
conditions allow), thus mitigating the potentially awful performance impact
|
||||
of unplanned swapping.
|
||||
|
||||
A KVM implementation is underway and has been RFC'ed to lkml. And,
|
||||
using frontswap, investigation is also underway on the use of NVM as
|
||||
a memory extension technology.
|
||||
|
||||
2) Sure there may be performance advantages in some situations, but
|
||||
what's the space/time overhead of frontswap?
|
||||
|
||||
If CONFIG_FRONTSWAP is disabled, every frontswap hook compiles into
|
||||
nothingness and the only overhead is a few extra bytes per swapon'ed
|
||||
swap device. If CONFIG_FRONTSWAP is enabled but no frontswap "backend"
|
||||
registers, there is one extra global variable compared to zero for
|
||||
every swap page read or written. If CONFIG_FRONTSWAP is enabled
|
||||
AND a frontswap backend registers AND the backend fails every "store"
|
||||
request (i.e. provides no memory despite claiming it might),
|
||||
CPU overhead is still negligible -- and since every frontswap fail
|
||||
precedes a swap page write-to-disk, the system is highly likely
|
||||
to be I/O bound and using a small fraction of a percent of a CPU
|
||||
will be irrelevant anyway.
|
||||
|
||||
As for space, if CONFIG_FRONTSWAP is enabled AND a frontswap backend
|
||||
registers, one bit is allocated for every swap page for every swap
|
||||
device that is swapon'd. This is added to the EIGHT bits (which
|
||||
was sixteen until about 2.6.34) that the kernel already allocates
|
||||
for every swap page for every swap device that is swapon'd. (Hugh
|
||||
Dickins has observed that frontswap could probably steal one of
|
||||
the existing eight bits, but let's worry about that minor optimization
|
||||
later.) For very large swap disks (which are rare) on a standard
|
||||
4K pagesize, this is 1MB per 32GB swap.
|
||||
|
||||
When swap pages are stored in transcendent memory instead of written
|
||||
out to disk, there is a side effect that this may create more memory
|
||||
pressure that can potentially outweigh the other advantages. A
|
||||
backend, such as zcache, must implement policies to carefully (but
|
||||
dynamically) manage memory limits to ensure this doesn't happen.
|
||||
|
||||
3) OK, how about a quick overview of what this frontswap patch does
|
||||
in terms that a kernel hacker can grok?
|
||||
|
||||
Let's assume that a frontswap "backend" has registered during
|
||||
kernel initialization; this registration indicates that this
|
||||
frontswap backend has access to some "memory" that is not directly
|
||||
accessible by the kernel. Exactly how much memory it provides is
|
||||
entirely dynamic and random.
|
||||
|
||||
Whenever a swap-device is swapon'd frontswap_init() is called,
|
||||
passing the swap device number (aka "type") as a parameter.
|
||||
This notifies frontswap to expect attempts to "store" swap pages
|
||||
associated with that number.
|
||||
|
||||
Whenever the swap subsystem is readying a page to write to a swap
|
||||
device (c.f swap_writepage()), frontswap_store is called. Frontswap
|
||||
consults with the frontswap backend and if the backend says it does NOT
|
||||
have room, frontswap_store returns -1 and the kernel swaps the page
|
||||
to the swap device as normal. Note that the response from the frontswap
|
||||
backend is unpredictable to the kernel; it may choose to never accept a
|
||||
page, it could accept every ninth page, or it might accept every
|
||||
page. But if the backend does accept a page, the data from the page
|
||||
has already been copied and associated with the type and offset,
|
||||
and the backend guarantees the persistence of the data. In this case,
|
||||
frontswap sets a bit in the "frontswap_map" for the swap device
|
||||
corresponding to the page offset on the swap device to which it would
|
||||
otherwise have written the data.
|
||||
|
||||
When the swap subsystem needs to swap-in a page (swap_readpage()),
|
||||
it first calls frontswap_load() which checks the frontswap_map to
|
||||
see if the page was earlier accepted by the frontswap backend. If
|
||||
it was, the page of data is filled from the frontswap backend and
|
||||
the swap-in is complete. If not, the normal swap-in code is
|
||||
executed to obtain the page of data from the real swap device.
|
||||
|
||||
So every time the frontswap backend accepts a page, a swap device read
|
||||
and (potentially) a swap device write are replaced by a "frontswap backend
|
||||
store" and (possibly) a "frontswap backend loads", which are presumably much
|
||||
faster.
|
||||
|
||||
4) Can't frontswap be configured as a "special" swap device that is
|
||||
just higher priority than any real swap device (e.g. like zswap,
|
||||
or maybe swap-over-nbd/NFS)?
|
||||
|
||||
No. First, the existing swap subsystem doesn't allow for any kind of
|
||||
swap hierarchy. Perhaps it could be rewritten to accomodate a hierarchy,
|
||||
but this would require fairly drastic changes. Even if it were
|
||||
rewritten, the existing swap subsystem uses the block I/O layer which
|
||||
assumes a swap device is fixed size and any page in it is linearly
|
||||
addressable. Frontswap barely touches the existing swap subsystem,
|
||||
and works around the constraints of the block I/O subsystem to provide
|
||||
a great deal of flexibility and dynamicity.
|
||||
|
||||
For example, the acceptance of any swap page by the frontswap backend is
|
||||
entirely unpredictable. This is critical to the definition of frontswap
|
||||
backends because it grants completely dynamic discretion to the
|
||||
backend. In zcache, one cannot know a priori how compressible a page is.
|
||||
"Poorly" compressible pages can be rejected, and "poorly" can itself be
|
||||
defined dynamically depending on current memory constraints.
|
||||
|
||||
Further, frontswap is entirely synchronous whereas a real swap
|
||||
device is, by definition, asynchronous and uses block I/O. The
|
||||
block I/O layer is not only unnecessary, but may perform "optimizations"
|
||||
that are inappropriate for a RAM-oriented device including delaying
|
||||
the write of some pages for a significant amount of time. Synchrony is
|
||||
required to ensure the dynamicity of the backend and to avoid thorny race
|
||||
conditions that would unnecessarily and greatly complicate frontswap
|
||||
and/or the block I/O subsystem. That said, only the initial "store"
|
||||
and "load" operations need be synchronous. A separate asynchronous thread
|
||||
is free to manipulate the pages stored by frontswap. For example,
|
||||
the "remotification" thread in RAMster uses standard asynchronous
|
||||
kernel sockets to move compressed frontswap pages to a remote machine.
|
||||
Similarly, a KVM guest-side implementation could do in-guest compression
|
||||
and use "batched" hypercalls.
|
||||
|
||||
In a virtualized environment, the dynamicity allows the hypervisor
|
||||
(or host OS) to do "intelligent overcommit". For example, it can
|
||||
choose to accept pages only until host-swapping might be imminent,
|
||||
then force guests to do their own swapping.
|
||||
|
||||
There is a downside to the transcendent memory specifications for
|
||||
frontswap: Since any "store" might fail, there must always be a real
|
||||
slot on a real swap device to swap the page. Thus frontswap must be
|
||||
implemented as a "shadow" to every swapon'd device with the potential
|
||||
capability of holding every page that the swap device might have held
|
||||
and the possibility that it might hold no pages at all. This means
|
||||
that frontswap cannot contain more pages than the total of swapon'd
|
||||
swap devices. For example, if NO swap device is configured on some
|
||||
installation, frontswap is useless. Swapless portable devices
|
||||
can still use frontswap but a backend for such devices must configure
|
||||
some kind of "ghost" swap device and ensure that it is never used.
|
||||
|
||||
5) Why this weird definition about "duplicate stores"? If a page
|
||||
has been previously successfully stored, can't it always be
|
||||
successfully overwritten?
|
||||
|
||||
Nearly always it can, but no, sometimes it cannot. Consider an example
|
||||
where data is compressed and the original 4K page has been compressed
|
||||
to 1K. Now an attempt is made to overwrite the page with data that
|
||||
is non-compressible and so would take the entire 4K. But the backend
|
||||
has no more space. In this case, the store must be rejected. Whenever
|
||||
frontswap rejects a store that would overwrite, it also must invalidate
|
||||
the old data and ensure that it is no longer accessible. Since the
|
||||
swap subsystem then writes the new data to the read swap device,
|
||||
this is the correct course of action to ensure coherency.
|
||||
|
||||
6) What is frontswap_shrink for?
|
||||
|
||||
When the (non-frontswap) swap subsystem swaps out a page to a real
|
||||
swap device, that page is only taking up low-value pre-allocated disk
|
||||
space. But if frontswap has placed a page in transcendent memory, that
|
||||
page may be taking up valuable real estate. The frontswap_shrink
|
||||
routine allows code outside of the swap subsystem to force pages out
|
||||
of the memory managed by frontswap and back into kernel-addressable memory.
|
||||
For example, in RAMster, a "suction driver" thread will attempt
|
||||
to "repatriate" pages sent to a remote machine back to the local machine;
|
||||
this is driven using the frontswap_shrink mechanism when memory pressure
|
||||
subsides.
|
||||
|
||||
7) Why does the frontswap patch create the new include file swapfile.h?
|
||||
|
||||
The frontswap code depends on some swap-subsystem-internal data
|
||||
structures that have, over the years, moved back and forth between
|
||||
static and global. This seemed a reasonable compromise: Define
|
||||
them as global but declare them in a new include file that isn't
|
||||
included by the large number of source files that include swap.h.
|
||||
|
||||
Dan Magenheimer, last updated April 9, 2012
|
||||
86
MAINTAINERS
86
MAINTAINERS
|
|
@ -579,7 +579,7 @@ F: drivers/net/appletalk/
|
|||
F: net/appletalk/
|
||||
|
||||
ARASAN COMPACT FLASH PATA CONTROLLER
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: linux-ide@vger.kernel.org
|
||||
S: Maintained
|
||||
F: include/linux/pata_arasan_cf_data.h
|
||||
|
|
@ -1077,7 +1077,7 @@ F: drivers/media/video/s5p-fimc/
|
|||
ARM/SAMSUNG S5P SERIES Multi Format Codec (MFC) SUPPORT
|
||||
M: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
M: Kamil Debski <k.debski@samsung.com>
|
||||
M: Jeongtae Park <jtp.park@samsung.com>
|
||||
M: Jeongtae Park <jtp.park@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org
|
||||
L: linux-media@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -1646,11 +1646,11 @@ S: Maintained
|
|||
F: drivers/gpio/gpio-bt8xx.c
|
||||
|
||||
BTRFS FILE SYSTEM
|
||||
M: Chris Mason <chris.mason@oracle.com>
|
||||
M: Chris Mason <chris.mason@fusionio.com>
|
||||
L: linux-btrfs@vger.kernel.org
|
||||
W: http://btrfs.wiki.kernel.org/
|
||||
Q: http://patchwork.kernel.org/project/linux-btrfs/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfs.git
|
||||
S: Maintained
|
||||
F: Documentation/filesystems/btrfs.txt
|
||||
F: fs/btrfs/
|
||||
|
|
@ -1743,10 +1743,10 @@ F: include/linux/can/platform/
|
|||
CAPABILITIES
|
||||
M: Serge Hallyn <serge.hallyn@canonical.com>
|
||||
L: linux-security-module@vger.kernel.org
|
||||
S: Supported
|
||||
S: Supported
|
||||
F: include/linux/capability.h
|
||||
F: security/capability.c
|
||||
F: security/commoncap.c
|
||||
F: security/commoncap.c
|
||||
F: kernel/capability.c
|
||||
|
||||
CELL BROADBAND ENGINE ARCHITECTURE
|
||||
|
|
@ -1800,6 +1800,9 @@ F: include/linux/cfag12864b.h
|
|||
CFG80211 and NL80211
|
||||
M: Johannes Berg <johannes@sipsolutions.net>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
W: http://wireless.kernel.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
|
||||
S: Maintained
|
||||
F: include/linux/nl80211.h
|
||||
F: include/net/cfg80211.h
|
||||
|
|
@ -2146,11 +2149,11 @@ S: Orphan
|
|||
F: drivers/net/wan/pc300*
|
||||
|
||||
CYTTSP TOUCHSCREEN DRIVER
|
||||
M: Javier Martinez Canillas <javier@dowhile0.org>
|
||||
L: linux-input@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/input/touchscreen/cyttsp*
|
||||
F: include/linux/input/cyttsp.h
|
||||
M: Javier Martinez Canillas <javier@dowhile0.org>
|
||||
L: linux-input@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/input/touchscreen/cyttsp*
|
||||
F: include/linux/input/cyttsp.h
|
||||
|
||||
DAMA SLAVE for AX.25
|
||||
M: Joerg Reuter <jreuter@yaina.de>
|
||||
|
|
@ -2270,7 +2273,7 @@ F: include/linux/device-mapper.h
|
|||
F: include/linux/dm-*.h
|
||||
|
||||
DIOLAN U2C-12 I2C DRIVER
|
||||
M: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/i2c/busses/i2c-diolan-u2c.c
|
||||
|
|
@ -2930,6 +2933,13 @@ F: Documentation/power/freezing-of-tasks.txt
|
|||
F: include/linux/freezer.h
|
||||
F: kernel/freezer.c
|
||||
|
||||
FRONTSWAP API
|
||||
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: mm/frontswap.c
|
||||
F: include/linux/frontswap.h
|
||||
|
||||
FS-CACHE: LOCAL CACHING FOR NETWORK FILESYSTEMS
|
||||
M: David Howells <dhowells@redhat.com>
|
||||
L: linux-cachefs@redhat.com
|
||||
|
|
@ -3138,7 +3148,7 @@ F: drivers/tty/hvc/
|
|||
|
||||
HARDWARE MONITORING
|
||||
M: Jean Delvare <khali@linux-fr.org>
|
||||
M: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
W: http://www.lm-sensors.org/
|
||||
T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
|
||||
|
|
@ -4096,6 +4106,8 @@ F: drivers/scsi/53c700*
|
|||
LED SUBSYSTEM
|
||||
M: Bryan Wu <bryan.wu@canonical.com>
|
||||
M: Richard Purdie <rpurdie@rpsys.net>
|
||||
L: linux-leds@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds.git
|
||||
S: Maintained
|
||||
F: drivers/leds/
|
||||
F: include/linux/leds.h
|
||||
|
|
@ -4340,7 +4352,8 @@ MAC80211
|
|||
M: Johannes Berg <johannes@sipsolutions.net>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
W: http://linuxwireless.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
|
||||
S: Maintained
|
||||
F: Documentation/networking/mac80211-injection.txt
|
||||
F: include/net/mac80211.h
|
||||
|
|
@ -4351,7 +4364,8 @@ M: Stefano Brivio <stefano.brivio@polimi.it>
|
|||
M: Mattias Nissler <mattias.nissler@gmx.de>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
W: http://linuxwireless.org/en/developers/Documentation/mac80211/RateControl/PID
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
|
||||
S: Maintained
|
||||
F: net/mac80211/rc80211_pid*
|
||||
|
||||
|
|
@ -4411,6 +4425,13 @@ S: Orphan
|
|||
F: drivers/video/matrox/matroxfb_*
|
||||
F: include/linux/matroxfb.h
|
||||
|
||||
MAX16065 HARDWARE MONITOR DRIVER
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
S: Maintained
|
||||
F: Documentation/hwmon/max16065
|
||||
F: drivers/hwmon/max16065.c
|
||||
|
||||
MAX6650 HARDWARE MONITOR AND FAN CONTROLLER DRIVER
|
||||
M: "Hans J. Koch" <hjk@hansjkoch.de>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
|
|
@ -5149,7 +5170,7 @@ F: drivers/leds/leds-pca9532.c
|
|||
F: include/linux/leds-pca9532.h
|
||||
|
||||
PCA9541 I2C BUS MASTER SELECTOR DRIVER
|
||||
M: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/i2c/muxes/i2c-mux-pca9541.c
|
||||
|
|
@ -5169,7 +5190,7 @@ S: Maintained
|
|||
F: drivers/firmware/pcdp.*
|
||||
|
||||
PCI ERROR RECOVERY
|
||||
M: Linas Vepstas <linasvepstas@gmail.com>
|
||||
M: Linas Vepstas <linasvepstas@gmail.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/PCI/pci-error-recovery.txt
|
||||
|
|
@ -5275,7 +5296,7 @@ S: Maintained
|
|||
F: drivers/pinctrl/
|
||||
|
||||
PIN CONTROLLER - ST SPEAR
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.st.com/spear
|
||||
|
|
@ -5299,7 +5320,7 @@ F: drivers/video/fb-puv3.c
|
|||
F: drivers/rtc/rtc-puv3.c
|
||||
|
||||
PMBUS HARDWARE MONITORING DRIVERS
|
||||
M: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
W: http://www.lm-sensors.org/
|
||||
W: http://www.roeck-us.net/linux/drivers/
|
||||
|
|
@ -5695,6 +5716,9 @@ F: include/linux/remoteproc.h
|
|||
RFKILL
|
||||
M: Johannes Berg <johannes@sipsolutions.net>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
W: http://wireless.kernel.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
|
||||
S: Maintained
|
||||
F: Documentation/rfkill.txt
|
||||
F: net/rfkill/
|
||||
|
|
@ -5849,7 +5873,7 @@ S: Maintained
|
|||
F: drivers/tty/serial
|
||||
|
||||
SYNOPSYS DESIGNWARE DMAC DRIVER
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
S: Maintained
|
||||
F: include/linux/dw_dmac.h
|
||||
F: drivers/dma/dw_dmac_regs.h
|
||||
|
|
@ -5997,7 +6021,7 @@ S: Maintained
|
|||
F: drivers/mmc/host/sdhci-s3c.c
|
||||
|
||||
SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) ST SPEAR DRIVER
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-mmc@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -6353,7 +6377,7 @@ S: Maintained
|
|||
F: include/linux/compiler.h
|
||||
|
||||
SPEAR PLATFORM SUPPORT
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
M: Shiraz Hashim <shiraz.hashim@st.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -6362,7 +6386,7 @@ S: Maintained
|
|||
F: arch/arm/plat-spear/
|
||||
|
||||
SPEAR13XX MACHINE SUPPORT
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
M: Shiraz Hashim <shiraz.hashim@st.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -6371,7 +6395,7 @@ S: Maintained
|
|||
F: arch/arm/mach-spear13xx/
|
||||
|
||||
SPEAR3XX MACHINE SUPPORT
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
M: Shiraz Hashim <shiraz.hashim@st.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -6382,7 +6406,7 @@ F: arch/arm/mach-spear3xx/
|
|||
SPEAR6XX MACHINE SUPPORT
|
||||
M: Rajeev Kumar <rajeev-dlh.kumar@st.com>
|
||||
M: Shiraz Hashim <shiraz.hashim@st.com>
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.st.com/spear
|
||||
|
|
@ -6390,7 +6414,7 @@ S: Maintained
|
|||
F: arch/arm/mach-spear6xx/
|
||||
|
||||
SPEAR CLOCK FRAMEWORK SUPPORT
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.st.com/spear
|
||||
|
|
@ -7291,11 +7315,11 @@ F: Documentation/DocBook/uio-howto.tmpl
|
|||
F: drivers/uio/
|
||||
F: include/linux/uio*.h
|
||||
|
||||
UTIL-LINUX-NG PACKAGE
|
||||
UTIL-LINUX PACKAGE
|
||||
M: Karel Zak <kzak@redhat.com>
|
||||
L: util-linux-ng@vger.kernel.org
|
||||
W: http://kernel.org/~kzak/util-linux-ng/
|
||||
T: git git://git.kernel.org/pub/scm/utils/util-linux-ng/util-linux-ng.git
|
||||
L: util-linux@vger.kernel.org
|
||||
W: http://en.wikipedia.org/wiki/Util-linux
|
||||
T: git git://git.kernel.org/pub/scm/utils/util-linux/util-linux.git
|
||||
S: Maintained
|
||||
|
||||
UVESAFB DRIVER
|
||||
|
|
@ -7397,7 +7421,7 @@ F: include/linux/vlynq.h
|
|||
|
||||
VME SUBSYSTEM
|
||||
M: Martyn Welch <martyn.welch@ge.com>
|
||||
M: Manohar Vanga <manohar.vanga@cern.ch>
|
||||
M: Manohar Vanga <manohar.vanga@gmail.com>
|
||||
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
L: devel@driverdev.osuosl.org
|
||||
S: Maintained
|
||||
|
|
|
|||
6
Makefile
6
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 5
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc1
|
||||
EXTRAVERSION = -rc4
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
@ -561,6 +561,8 @@ else
|
|||
KBUILD_CFLAGS += -O2
|
||||
endif
|
||||
|
||||
include $(srctree)/arch/$(SRCARCH)/Makefile
|
||||
|
||||
ifdef CONFIG_READABLE_ASM
|
||||
# Disable optimizations that make assembler listings hard to read.
|
||||
# reorder blocks reorders the control in the function
|
||||
|
|
@ -571,8 +573,6 @@ KBUILD_CFLAGS += $(call cc-option,-fno-reorder-blocks,) \
|
|||
$(call cc-option,-fno-partial-inlining)
|
||||
endif
|
||||
|
||||
include $(srctree)/arch/$(SRCARCH)/Makefile
|
||||
|
||||
ifneq ($(CONFIG_FRAME_WARN),0)
|
||||
KBUILD_CFLAGS += $(call cc-option,-Wframe-larger-than=${CONFIG_FRAME_WARN})
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@ config ARM
|
|||
select HAVE_IDE if PCI || ISA || PCMCIA
|
||||
select HAVE_DMA_ATTRS
|
||||
select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
|
||||
select CMA if (CPU_V6 || CPU_V6K || CPU_V7)
|
||||
select HAVE_MEMBLOCK
|
||||
select RTC_LIB
|
||||
select SYS_SUPPORTS_APM_EMULATION
|
||||
|
|
@ -294,6 +293,7 @@ config ARCH_VERSATILE
|
|||
select ICST
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select NEED_MACH_IO_H if PCI
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_CLCD
|
||||
select PLAT_VERSATILE_FPGA_IRQ
|
||||
|
|
@ -589,6 +589,7 @@ config ARCH_ORION5X
|
|||
select PCI
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select NEED_MACH_IO_H
|
||||
select PLAT_ORION
|
||||
help
|
||||
Support for the following Marvell Orion 5x series SoCs:
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
/include/ "mmp2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell MMP2 Aspenite Development Board";
|
||||
model = "Marvell MMP2 Brownstone Development Board";
|
||||
compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
|
||||
|
||||
chosen {
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x04000000>;
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
|
|
|
|||
|
|
@ -44,6 +44,8 @@
|
|||
compatible = "ti,omap2-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
ti,intc-size = <96>;
|
||||
reg = <0x480FE000 0x1000>;
|
||||
};
|
||||
|
||||
uart1: serial@4806a000 {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr1310 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for all SPEAr1310 SoCs
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr1340 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for all SPEAr1340 SoCs
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for all SPEAr13xx SoCs
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr300 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr300 SoC
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr310 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr310 SoC
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr320 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr320 SoC
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for all SPEAr3xx SoCs
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -366,8 +366,8 @@ static int __dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr,
|
|||
struct safe_buffer *buf;
|
||||
unsigned long off;
|
||||
|
||||
dev_dbg(dev, "%s(dma=%#x,off=%#lx,sz=%zx,dir=%x)\n",
|
||||
__func__, addr, off, sz, dir);
|
||||
dev_dbg(dev, "%s(dma=%#x,sz=%zx,dir=%x)\n",
|
||||
__func__, addr, sz, dir);
|
||||
|
||||
buf = find_safe_buffer_dev(dev, addr, __func__);
|
||||
if (!buf)
|
||||
|
|
@ -377,8 +377,8 @@ static int __dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr,
|
|||
|
||||
BUG_ON(buf->direction != dir);
|
||||
|
||||
dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
|
||||
__func__, buf->ptr, virt_to_dma(dev, buf->ptr),
|
||||
dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x off=%#lx) mapped to %p (dma=%#x)\n",
|
||||
__func__, buf->ptr, virt_to_dma(dev, buf->ptr), off,
|
||||
buf->safe, buf->safe_dma_addr);
|
||||
|
||||
DO_STATS(dev->archdata.dmabounce->bounce_count++);
|
||||
|
|
@ -406,8 +406,8 @@ static int __dmabounce_sync_for_device(struct device *dev, dma_addr_t addr,
|
|||
struct safe_buffer *buf;
|
||||
unsigned long off;
|
||||
|
||||
dev_dbg(dev, "%s(dma=%#x,off=%#lx,sz=%zx,dir=%x)\n",
|
||||
__func__, addr, off, sz, dir);
|
||||
dev_dbg(dev, "%s(dma=%#x,sz=%zx,dir=%x)\n",
|
||||
__func__, addr, sz, dir);
|
||||
|
||||
buf = find_safe_buffer_dev(dev, addr, __func__);
|
||||
if (!buf)
|
||||
|
|
@ -417,8 +417,8 @@ static int __dmabounce_sync_for_device(struct device *dev, dma_addr_t addr,
|
|||
|
||||
BUG_ON(buf->direction != dir);
|
||||
|
||||
dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
|
||||
__func__, buf->ptr, virt_to_dma(dev, buf->ptr),
|
||||
dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x off=%#lx) mapped to %p (dma=%#x)\n",
|
||||
__func__, buf->ptr, virt_to_dma(dev, buf->ptr), off,
|
||||
buf->safe, buf->safe_dma_addr);
|
||||
|
||||
DO_STATS(dev->archdata.dmabounce->bounce_count++);
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
" .long 1b, 4f, 2b, 4f\n" \
|
||||
" .popsection\n" \
|
||||
" .pushsection .fixup,\"ax\"\n" \
|
||||
" .align 2\n" \
|
||||
"4: mov %0, " err_reg "\n" \
|
||||
" b 3b\n" \
|
||||
" .popsection"
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* ARM PrimeXsys System Controller SP810 header file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -495,6 +495,7 @@ ENDPROC(__und_usr)
|
|||
* The out of line fixup for the ldrt above.
|
||||
*/
|
||||
.pushsection .fixup, "ax"
|
||||
.align 2
|
||||
4: mov pc, r9
|
||||
.popsection
|
||||
.pushsection __ex_table,"a"
|
||||
|
|
|
|||
|
|
@ -660,7 +660,7 @@ static const union decode_item t32_table_1111_100x[] = {
|
|||
/* LDRSB (literal) 1111 1001 x001 1111 xxxx xxxx xxxx xxxx */
|
||||
/* LDRH (literal) 1111 1000 x011 1111 xxxx xxxx xxxx xxxx */
|
||||
/* LDRSH (literal) 1111 1001 x011 1111 xxxx xxxx xxxx xxxx */
|
||||
DECODE_EMULATEX (0xfe5f0000, 0xf81f0000, t32_simulate_ldr_literal,
|
||||
DECODE_SIMULATEX(0xfe5f0000, 0xf81f0000, t32_simulate_ldr_literal,
|
||||
REGS(PC, NOSPPCX, 0, 0, 0)),
|
||||
|
||||
/* STRB (immediate) 1111 1000 0000 xxxx xxxx 1xxx xxxx xxxx */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,8 @@
|
|||
obj-y := clock.o highbank.o system.o
|
||||
obj-y := clock.o highbank.o system.o smc.o
|
||||
|
||||
plus_sec := $(call as-instr,.arch_extension sec,+sec)
|
||||
AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
obj-$(CONFIG_DEBUG_HIGHBANK_UART) += lluart.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
|
|
|||
|
|
@ -8,3 +8,4 @@ extern void highbank_lluart_map_io(void);
|
|||
static inline void highbank_lluart_map_io(void) {}
|
||||
#endif
|
||||
|
||||
extern void highbank_smc1(int fn, int arg);
|
||||
|
|
|
|||
|
|
@ -85,10 +85,24 @@ const static struct of_device_id irq_match[] = {
|
|||
{}
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
static void highbank_l2x0_disable(void)
|
||||
{
|
||||
/* Disable PL310 L2 Cache controller */
|
||||
highbank_smc1(0x102, 0x0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init highbank_init_irq(void)
|
||||
{
|
||||
of_irq_init(irq_match);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Enable PL310 L2 Cache controller */
|
||||
highbank_smc1(0x102, 0x1);
|
||||
l2x0_of_init(0, ~0UL);
|
||||
outer_cache.disable = highbank_l2x0_disable;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init highbank_timer_init(void)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copied from omap44xx-smc.S Copyright (C) 2010 Texas Instruments, Inc.
|
||||
* Copyright 2012 Calxeda, Inc.
|
||||
*
|
||||
* This program is free software,you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
/*
|
||||
* This is common routine to manage secure monitor API
|
||||
* used to modify the PL310 secure registers.
|
||||
* 'r0' contains the value to be modified and 'r12' contains
|
||||
* the monitor API number.
|
||||
* Function signature : void highbank_smc1(u32 fn, u32 arg)
|
||||
*/
|
||||
|
||||
ENTRY(highbank_smc1)
|
||||
stmfd sp!, {r4-r11, lr}
|
||||
mov r12, r0
|
||||
mov r0, r1
|
||||
dsb
|
||||
smc #0
|
||||
ldmfd sp!, {r4-r11, pc}
|
||||
ENDPROC(highbank_smc1)
|
||||
|
|
@ -477,6 +477,7 @@ config MACH_MX31_3DS
|
|||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_IMX_KEYPAD
|
||||
select IMX_HAVE_PLATFORM_IMX_SSI
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_IPU_CORE
|
||||
select IMX_HAVE_PLATFORM_MXC_EHCI
|
||||
|
|
|
|||
|
|
@ -108,8 +108,7 @@ int __init mx1_clocks_init(unsigned long fref)
|
|||
clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0");
|
||||
clk_register_clkdev(clk[clko], "clko", NULL);
|
||||
|
||||
mxc_timer_init(NULL, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
|
||||
MX1_TIM1_INT);
|
||||
mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -180,7 +180,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
|
|||
clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
|
||||
|
||||
mxc_timer_init(NULL, MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
|
||||
MX21_INT_GPT1);
|
||||
mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -243,6 +243,6 @@ int __init mx25_clocks_init(void)
|
|||
clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
|
||||
clk_register_clkdev(clk[iim_ipg], "iim", NULL);
|
||||
|
||||
mxc_timer_init(NULL, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
|
||||
mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -263,8 +263,7 @@ int __init mx27_clocks_init(unsigned long fref)
|
|||
clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
|
||||
|
||||
mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
|
||||
MX27_INT_GPT1);
|
||||
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
|
||||
|
||||
clk_prepare_enable(clk[emi_ahb_gate]);
|
||||
|
||||
|
|
|
|||
|
|
@ -175,8 +175,7 @@ int __init mx31_clocks_init(unsigned long fref)
|
|||
mx31_revision();
|
||||
clk_disable_unprepare(clk[iim_gate]);
|
||||
|
||||
mxc_timer_init(NULL, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
|
||||
MX31_INT_GPT);
|
||||
mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -267,11 +267,9 @@ int __init mx35_clocks_init()
|
|||
imx_print_silicon_rev("i.MX35", mx35_revision());
|
||||
|
||||
#ifdef CONFIG_MXC_USE_EPIT
|
||||
epit_timer_init(&epit1_clk,
|
||||
MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
|
||||
epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
|
||||
#else
|
||||
mxc_timer_init(NULL, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR),
|
||||
MX35_INT_GPT);
|
||||
mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -104,12 +104,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
|||
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
|
||||
clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
|
||||
main_bus_sel, ARRAY_SIZE(main_bus_sel));
|
||||
clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1,
|
||||
clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
|
||||
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
|
||||
clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
|
||||
clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
|
||||
clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
|
||||
clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0,
|
||||
clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
|
||||
per_root_sel, ARRAY_SIZE(per_root_sel));
|
||||
clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
|
||||
clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
|
||||
|
|
@ -172,7 +172,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
|||
clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
|
||||
clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
|
||||
clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
|
||||
clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18);
|
||||
clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18);
|
||||
clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
|
||||
clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
|
||||
clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
|
||||
|
|
@ -366,8 +366,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
clk_set_rate(clk[esdhc_b_podf], 166250000);
|
||||
|
||||
/* System timer */
|
||||
mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
|
||||
MX51_INT_GPT);
|
||||
mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
|
||||
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
imx_print_silicon_rev("i.MX51", mx51_revision());
|
||||
|
|
@ -452,8 +451,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
clk_set_rate(clk[esdhc_b_podf], 200000000);
|
||||
|
||||
/* System timer */
|
||||
mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
|
||||
MX53_INT_GPT);
|
||||
mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
|
||||
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
imx_print_silicon_rev("i.MX53", mx53_revision());
|
||||
|
|
|
|||
|
|
@ -122,10 +122,6 @@ static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5
|
|||
"dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
|
||||
"ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", };
|
||||
|
||||
static const char * const clks_init_on[] __initconst = {
|
||||
"mmdc_ch0_axi", "mmdc_ch1_axi", "usboh3",
|
||||
};
|
||||
|
||||
enum mx6q_clks {
|
||||
dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
|
||||
pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
|
||||
|
|
@ -161,11 +157,14 @@ enum mx6q_clks {
|
|||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
static enum mx6q_clks const clks_init_on[] __initconst = {
|
||||
mmdc_ch0_axi, mmdc_ch1_axi,
|
||||
};
|
||||
|
||||
int __init mx6q_clocks_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *base;
|
||||
struct clk *c;
|
||||
int i, irq;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
|
|
@ -424,21 +423,14 @@ int __init mx6q_clocks_init(void)
|
|||
clk_register_clkdev(clk[ahb], "ahb", NULL);
|
||||
clk_register_clkdev(clk[cko1], "cko1", NULL);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) {
|
||||
c = clk_get_sys(clks_init_on[i], NULL);
|
||||
if (IS_ERR(c)) {
|
||||
pr_err("%s: failed to get clk %s", __func__,
|
||||
clks_init_on[i]);
|
||||
return PTR_ERR(c);
|
||||
}
|
||||
clk_prepare_enable(c);
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clk[clks_init_on[i]]);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
mxc_timer_init(NULL, base, irq);
|
||||
mxc_timer_init(base, irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,30 +74,15 @@ struct clk_pllv2 {
|
|||
void __iomem *base;
|
||||
};
|
||||
|
||||
static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
|
||||
u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn)
|
||||
{
|
||||
long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
|
||||
unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
|
||||
void __iomem *pllbase;
|
||||
unsigned long dbl;
|
||||
s64 temp;
|
||||
struct clk_pllv2 *pll = to_clk_pllv2(hw);
|
||||
|
||||
pllbase = pll->base;
|
||||
|
||||
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
|
||||
pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
|
||||
dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
|
||||
|
||||
if (pll_hfsm == 0) {
|
||||
dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
|
||||
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
|
||||
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
|
||||
} else {
|
||||
dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
|
||||
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
|
||||
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
|
||||
}
|
||||
pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
|
||||
mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
|
||||
mfi = (mfi <= 5) ? 5 : mfi;
|
||||
|
|
@ -123,18 +108,30 @@ static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
|
|||
return temp;
|
||||
}
|
||||
|
||||
static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_pllv2 *pll = to_clk_pllv2(hw);
|
||||
u32 reg;
|
||||
u32 dp_op, dp_mfd, dp_mfn, dp_ctl;
|
||||
void __iomem *pllbase;
|
||||
struct clk_pllv2 *pll = to_clk_pllv2(hw);
|
||||
|
||||
pllbase = pll->base;
|
||||
|
||||
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
|
||||
dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
|
||||
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
|
||||
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
|
||||
|
||||
return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
|
||||
}
|
||||
|
||||
static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
|
||||
u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn)
|
||||
{
|
||||
u32 reg;
|
||||
long mfi, pdf, mfn, mfd = 999999;
|
||||
s64 temp64;
|
||||
unsigned long quad_parent_rate;
|
||||
unsigned long pll_hfsm, dp_ctl;
|
||||
|
||||
pllbase = pll->base;
|
||||
|
||||
quad_parent_rate = 4 * parent_rate;
|
||||
pdf = mfi = -1;
|
||||
|
|
@ -144,25 +141,41 @@ static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return -EINVAL;
|
||||
pdf--;
|
||||
|
||||
temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
|
||||
do_div(temp64, quad_parent_rate/1000000);
|
||||
temp64 = rate * (pdf + 1) - quad_parent_rate * mfi;
|
||||
do_div(temp64, quad_parent_rate / 1000000);
|
||||
mfn = (long)temp64;
|
||||
|
||||
reg = mfi << 4 | pdf;
|
||||
|
||||
*dp_op = reg;
|
||||
*dp_mfd = mfd;
|
||||
*dp_mfn = mfn;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_pllv2 *pll = to_clk_pllv2(hw);
|
||||
void __iomem *pllbase;
|
||||
u32 dp_ctl, dp_op, dp_mfd, dp_mfn;
|
||||
int ret;
|
||||
|
||||
pllbase = pll->base;
|
||||
|
||||
|
||||
ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
|
||||
/* use dpdck0_2 */
|
||||
__raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
|
||||
pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
|
||||
if (pll_hfsm == 0) {
|
||||
reg = mfi << 4 | pdf;
|
||||
__raw_writel(reg, pllbase + MXC_PLL_DP_OP);
|
||||
__raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
|
||||
__raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
|
||||
} else {
|
||||
reg = mfi << 4 | pdf;
|
||||
__raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
|
||||
__raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
|
||||
__raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
|
||||
}
|
||||
|
||||
__raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
|
||||
__raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
|
||||
__raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -170,7 +183,11 @@ static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
return rate;
|
||||
u32 dp_op, dp_mfd, dp_mfn;
|
||||
|
||||
__clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
|
||||
return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
|
||||
dp_op, dp_mfd, dp_mfn);
|
||||
}
|
||||
|
||||
static int clk_pllv2_prepare(struct clk_hw *hw)
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
|
||||
#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
|
||||
#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
|
||||
#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
|
||||
#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
|
||||
|
||||
/* PLL Register Offsets */
|
||||
#define MXC_PLL_DP_CTL 0x00
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
#include <linux/errno.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cp15.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
int platform_cpu_kill(unsigned int cpu)
|
||||
|
|
@ -19,6 +20,44 @@ int platform_cpu_kill(unsigned int cpu)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static inline void cpu_enter_lowpower(void)
|
||||
{
|
||||
unsigned int v;
|
||||
|
||||
flush_cache_all();
|
||||
asm volatile(
|
||||
"mcr p15, 0, %1, c7, c5, 0\n"
|
||||
" mcr p15, 0, %1, c7, c10, 4\n"
|
||||
/*
|
||||
* Turn off coherency
|
||||
*/
|
||||
" mrc p15, 0, %0, c1, c0, 1\n"
|
||||
" bic %0, %0, %3\n"
|
||||
" mcr p15, 0, %0, c1, c0, 1\n"
|
||||
" mrc p15, 0, %0, c1, c0, 0\n"
|
||||
" bic %0, %0, %2\n"
|
||||
" mcr p15, 0, %0, c1, c0, 0\n"
|
||||
: "=&r" (v)
|
||||
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
static inline void cpu_leave_lowpower(void)
|
||||
{
|
||||
unsigned int v;
|
||||
|
||||
asm volatile(
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
" orr %0, %0, %1\n"
|
||||
" mcr p15, 0, %0, c1, c0, 0\n"
|
||||
" mrc p15, 0, %0, c1, c0, 1\n"
|
||||
" orr %0, %0, %2\n"
|
||||
" mcr p15, 0, %0, c1, c0, 1\n"
|
||||
: "=&r" (v)
|
||||
: "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
/*
|
||||
* platform-specific code to shutdown a CPU
|
||||
*
|
||||
|
|
@ -26,9 +65,10 @@ int platform_cpu_kill(unsigned int cpu)
|
|||
*/
|
||||
void platform_cpu_die(unsigned int cpu)
|
||||
{
|
||||
flush_cache_all();
|
||||
cpu_enter_lowpower();
|
||||
imx_enable_cpu(cpu, false);
|
||||
cpu_do_idle();
|
||||
cpu_leave_lowpower();
|
||||
|
||||
/* We should never return from idle */
|
||||
panic("cpu %d unexpectedly exit from shutdown\n", cpu);
|
||||
|
|
|
|||
|
|
@ -70,7 +70,6 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
|
|||
I2C_BOARD_INFO("pcf8563", 0x51),
|
||||
}, {
|
||||
I2C_BOARD_INFO("tsc2007", 0x48),
|
||||
.type = "tsc2007",
|
||||
.platform_data = &tsc2007_info,
|
||||
.irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
|
||||
},
|
||||
|
|
|
|||
|
|
@ -142,7 +142,6 @@ static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
|
|||
I2C_BOARD_INFO("pcf8563", 0x51),
|
||||
}, {
|
||||
I2C_BOARD_INFO("tsc2007", 0x49),
|
||||
.type = "tsc2007",
|
||||
.platform_data = &tsc2007_info,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -116,6 +116,8 @@ static const int visstrim_m10_pins[] __initconst = {
|
|||
PB23_PF_USB_PWR,
|
||||
PB24_PF_USB_OC,
|
||||
/* CSI */
|
||||
TVP5150_RSTN | GPIO_GPIO | GPIO_OUT,
|
||||
TVP5150_PWDN | GPIO_GPIO | GPIO_OUT,
|
||||
PB10_PF_CSI_D0,
|
||||
PB11_PF_CSI_D1,
|
||||
PB12_PF_CSI_D2,
|
||||
|
|
@ -147,6 +149,24 @@ static struct gpio visstrim_m10_version_gpios[] = {
|
|||
{ MOTHERBOARD_BIT2, GPIOF_IN, "mother-version-2" },
|
||||
};
|
||||
|
||||
static const struct gpio visstrim_m10_gpios[] __initconst = {
|
||||
{
|
||||
.gpio = TVP5150_RSTN,
|
||||
.flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH,
|
||||
.label = "tvp5150_rstn",
|
||||
},
|
||||
{
|
||||
.gpio = TVP5150_PWDN,
|
||||
.flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW,
|
||||
.label = "tvp5150_pwdn",
|
||||
},
|
||||
{
|
||||
.gpio = OTG_PHY_CS_GPIO,
|
||||
.flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW,
|
||||
.label = "usbotg_cs",
|
||||
},
|
||||
};
|
||||
|
||||
/* Camera */
|
||||
static int visstrim_camera_power(struct device *dev, int on)
|
||||
{
|
||||
|
|
@ -190,13 +210,6 @@ static void __init visstrim_camera_init(void)
|
|||
struct platform_device *pdev;
|
||||
int dma;
|
||||
|
||||
/* Initialize tvp5150 gpios */
|
||||
mxc_gpio_mode(TVP5150_RSTN | GPIO_GPIO | GPIO_OUT);
|
||||
mxc_gpio_mode(TVP5150_PWDN | GPIO_GPIO | GPIO_OUT);
|
||||
gpio_set_value(TVP5150_RSTN, 1);
|
||||
gpio_set_value(TVP5150_PWDN, 0);
|
||||
ndelay(1);
|
||||
|
||||
gpio_set_value(TVP5150_PWDN, 1);
|
||||
ndelay(1);
|
||||
gpio_set_value(TVP5150_RSTN, 0);
|
||||
|
|
@ -377,10 +390,6 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
|
|||
/* USB OTG */
|
||||
static int otg_phy_init(struct platform_device *pdev)
|
||||
{
|
||||
gpio_set_value(OTG_PHY_CS_GPIO, 0);
|
||||
|
||||
mdelay(10);
|
||||
|
||||
return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
|
||||
}
|
||||
|
||||
|
|
@ -435,6 +444,11 @@ static void __init visstrim_m10_board_init(void)
|
|||
if (ret)
|
||||
pr_err("Failed to setup pins (%d)\n", ret);
|
||||
|
||||
ret = gpio_request_array(visstrim_m10_gpios,
|
||||
ARRAY_SIZE(visstrim_m10_gpios));
|
||||
if (ret)
|
||||
pr_err("Failed to request gpios (%d)\n", ret);
|
||||
|
||||
imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
|
||||
imx27_add_imx_uart0(&uart_pdata);
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
* Memory-mapped I/O on MX21ADS base board
|
||||
*/
|
||||
#define MX21ADS_MMIO_BASE_ADDR 0xf5000000
|
||||
#define MX21ADS_MMIO_SIZE SZ_16M
|
||||
#define MX21ADS_MMIO_SIZE 0xc00000
|
||||
|
||||
#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
|
||||
(MX21ADS_MMIO_BASE_ADDR + (offset))
|
||||
|
|
|
|||
|
|
@ -86,6 +86,7 @@ static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
|
|||
|
||||
void __init imx3_init_l2x0(void)
|
||||
{
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
void __iomem *l2x0_base;
|
||||
void __iomem *clkctl_base;
|
||||
|
||||
|
|
@ -115,6 +116,7 @@ void __init imx3_init_l2x0(void)
|
|||
}
|
||||
|
||||
l2x0_init(l2x0_base, 0x00030024, 0x00000000);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX31
|
||||
|
|
@ -179,6 +181,8 @@ void __init imx31_soc_init(void)
|
|||
mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
if (to_version == 1) {
|
||||
strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
|
||||
strlen(imx31_sdma_pdata.fw_name));
|
||||
|
|
|
|||
|
|
@ -202,6 +202,8 @@ void __init imx51_soc_init(void)
|
|||
mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
/* i.mx51 has the i.mx35 type sdma */
|
||||
imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
|
||||
|
||||
|
|
|
|||
|
|
@ -20,9 +20,6 @@
|
|||
#include <linux/mv643xx_eth.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/spi/flash.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/orion_spi.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
|
|
|
|||
|
|
@ -159,6 +159,7 @@ static struct clk __init *clk_register_gate_fn(struct device *dev,
|
|||
gate_fn->gate.flags = clk_gate_flags;
|
||||
gate_fn->gate.lock = lock;
|
||||
gate_fn->gate.hw.init = &init;
|
||||
gate_fn->fn = fn;
|
||||
|
||||
/* ops is the gate ops, but with our disable function */
|
||||
if (clk_gate_fn_ops.disable != clk_gate_fn_disable) {
|
||||
|
|
@ -193,9 +194,11 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
|
|||
bit_idx, 0, &gating_lock, fn);
|
||||
}
|
||||
|
||||
static struct clk *ge0, *ge1;
|
||||
|
||||
void __init kirkwood_clk_init(void)
|
||||
{
|
||||
struct clk *runit, *ge0, *ge1, *sata0, *sata1, *usb0, *sdio;
|
||||
struct clk *runit, *sata0, *sata1, *usb0, *sdio;
|
||||
struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio;
|
||||
|
||||
tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
|
||||
|
|
@ -257,6 +260,9 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
|
|||
orion_ge00_init(eth_data,
|
||||
GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
|
||||
IRQ_KIRKWOOD_GE00_ERR);
|
||||
/* The interface forgets the MAC address assigned by u-boot if
|
||||
the clock is turned off, so claim the clk now. */
|
||||
clk_prepare_enable(ge0);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -268,6 +274,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
|
|||
orion_ge01_init(eth_data,
|
||||
GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
|
||||
IRQ_KIRKWOOD_GE01_ERR);
|
||||
clk_prepare_enable(ge1);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
#define IRQ_MASK_HIGH_OFF 0x0014
|
||||
|
||||
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
|
||||
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
|
||||
|
||||
#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
|
||||
#define L2_WRITETHROUGH 0x00000010
|
||||
|
|
|
|||
|
|
@ -80,6 +80,7 @@
|
|||
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
|
||||
|
||||
#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
|
||||
#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x20000)
|
||||
|
||||
#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
|
||||
|
||||
|
|
|
|||
|
|
@ -241,6 +241,7 @@ void __init mmp2_init_icu(void)
|
|||
icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
|
||||
icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
|
||||
icu_data[1].nr_irqs = 2;
|
||||
icu_data[1].cascade_irq = 4;
|
||||
icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
|
||||
icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
|
||||
icu_data[1].virq_base, 0,
|
||||
|
|
@ -249,6 +250,7 @@ void __init mmp2_init_icu(void)
|
|||
icu_data[2].reg_status = mmp_icu_base + 0x154;
|
||||
icu_data[2].reg_mask = mmp_icu_base + 0x16c;
|
||||
icu_data[2].nr_irqs = 2;
|
||||
icu_data[2].cascade_irq = 5;
|
||||
icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
|
||||
icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
|
||||
icu_data[2].virq_base, 0,
|
||||
|
|
@ -257,6 +259,7 @@ void __init mmp2_init_icu(void)
|
|||
icu_data[3].reg_status = mmp_icu_base + 0x180;
|
||||
icu_data[3].reg_mask = mmp_icu_base + 0x17c;
|
||||
icu_data[3].nr_irqs = 3;
|
||||
icu_data[3].cascade_irq = 9;
|
||||
icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
|
||||
icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
|
||||
icu_data[3].virq_base, 0,
|
||||
|
|
@ -265,6 +268,7 @@ void __init mmp2_init_icu(void)
|
|||
icu_data[4].reg_status = mmp_icu_base + 0x158;
|
||||
icu_data[4].reg_mask = mmp_icu_base + 0x170;
|
||||
icu_data[4].nr_irqs = 5;
|
||||
icu_data[4].cascade_irq = 17;
|
||||
icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
|
||||
icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
|
||||
icu_data[4].virq_base, 0,
|
||||
|
|
@ -273,6 +277,7 @@ void __init mmp2_init_icu(void)
|
|||
icu_data[5].reg_status = mmp_icu_base + 0x15c;
|
||||
icu_data[5].reg_mask = mmp_icu_base + 0x174;
|
||||
icu_data[5].nr_irqs = 15;
|
||||
icu_data[5].cascade_irq = 35;
|
||||
icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
|
||||
icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
|
||||
icu_data[5].virq_base, 0,
|
||||
|
|
@ -281,6 +286,7 @@ void __init mmp2_init_icu(void)
|
|||
icu_data[6].reg_status = mmp_icu_base + 0x160;
|
||||
icu_data[6].reg_mask = mmp_icu_base + 0x178;
|
||||
icu_data[6].nr_irqs = 2;
|
||||
icu_data[6].cascade_irq = 51;
|
||||
icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
|
||||
icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
|
||||
icu_data[6].virq_base, 0,
|
||||
|
|
@ -289,6 +295,7 @@ void __init mmp2_init_icu(void)
|
|||
icu_data[7].reg_status = mmp_icu_base + 0x188;
|
||||
icu_data[7].reg_mask = mmp_icu_base + 0x184;
|
||||
icu_data[7].nr_irqs = 2;
|
||||
icu_data[7].cascade_irq = 55;
|
||||
icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
|
||||
icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
|
||||
icu_data[7].virq_base, 0,
|
||||
|
|
|
|||
|
|
@ -83,11 +83,9 @@ static struct musb_hdrc_config musb_config = {
|
|||
};
|
||||
|
||||
static struct musb_hdrc_platform_data tusb_data = {
|
||||
#if defined(CONFIG_USB_MUSB_OTG)
|
||||
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
|
||||
.mode = MUSB_OTG,
|
||||
#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
|
||||
.mode = MUSB_PERIPHERAL,
|
||||
#else /* defined(CONFIG_USB_MUSB_HOST) */
|
||||
#else
|
||||
.mode = MUSB_HOST,
|
||||
#endif
|
||||
.set_power = tusb_set_power,
|
||||
|
|
|
|||
|
|
@ -81,13 +81,13 @@ static u8 omap3_beagle_version;
|
|||
static struct {
|
||||
int mmc1_gpio_wp;
|
||||
int usb_pwr_level;
|
||||
int reset_gpio;
|
||||
int dvi_pd_gpio;
|
||||
int usr_button_gpio;
|
||||
int mmc_caps;
|
||||
} beagle_config = {
|
||||
.mmc1_gpio_wp = -EINVAL,
|
||||
.usb_pwr_level = GPIOF_OUT_INIT_LOW,
|
||||
.reset_gpio = 129,
|
||||
.dvi_pd_gpio = -EINVAL,
|
||||
.usr_button_gpio = 4,
|
||||
.mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
|
||||
};
|
||||
|
|
@ -126,21 +126,21 @@ static void __init omap3_beagle_init_rev(void)
|
|||
printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
|
||||
omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
|
||||
beagle_config.mmc1_gpio_wp = 29;
|
||||
beagle_config.reset_gpio = 170;
|
||||
beagle_config.dvi_pd_gpio = 170;
|
||||
beagle_config.usr_button_gpio = 7;
|
||||
break;
|
||||
case 6:
|
||||
printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
|
||||
omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3;
|
||||
beagle_config.mmc1_gpio_wp = 23;
|
||||
beagle_config.reset_gpio = 170;
|
||||
beagle_config.dvi_pd_gpio = 170;
|
||||
beagle_config.usr_button_gpio = 7;
|
||||
break;
|
||||
case 5:
|
||||
printk(KERN_INFO "OMAP3 Beagle Rev: C4\n");
|
||||
omap3_beagle_version = OMAP3BEAGLE_BOARD_C4;
|
||||
beagle_config.mmc1_gpio_wp = 23;
|
||||
beagle_config.reset_gpio = 170;
|
||||
beagle_config.dvi_pd_gpio = 170;
|
||||
beagle_config.usr_button_gpio = 7;
|
||||
break;
|
||||
case 0:
|
||||
|
|
@ -274,11 +274,9 @@ static int beagle_twl_gpio_setup(struct device *dev,
|
|||
if (r)
|
||||
pr_err("%s: unable to configure nDVI_PWR_EN\n",
|
||||
__func__);
|
||||
r = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH,
|
||||
"DVI_LDO_EN");
|
||||
if (r)
|
||||
pr_err("%s: unable to configure DVI_LDO_EN\n",
|
||||
__func__);
|
||||
|
||||
beagle_config.dvi_pd_gpio = gpio + 2;
|
||||
|
||||
} else {
|
||||
/*
|
||||
* REVISIT: need ehci-omap hooks for external VBUS
|
||||
|
|
@ -287,7 +285,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
|
|||
if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
|
||||
pr_err("%s: unable to configure EHCI_nOC\n", __func__);
|
||||
}
|
||||
dvi_panel.power_down_gpio = beagle_config.reset_gpio;
|
||||
dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio;
|
||||
|
||||
gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
|
||||
"nEN_USB_PWR");
|
||||
|
|
@ -499,7 +497,7 @@ static void __init omap3_beagle_init(void)
|
|||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap3_beagle_init_rev();
|
||||
|
||||
if (beagle_config.mmc1_gpio_wp != -EINVAL)
|
||||
if (gpio_is_valid(beagle_config.mmc1_gpio_wp))
|
||||
omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
|
||||
mmc[0].caps = beagle_config.mmc_caps;
|
||||
omap_hsmmc_init(mmc);
|
||||
|
|
@ -510,15 +508,13 @@ static void __init omap3_beagle_init(void)
|
|||
|
||||
platform_add_devices(omap3_beagle_devices,
|
||||
ARRAY_SIZE(omap3_beagle_devices));
|
||||
if (gpio_is_valid(beagle_config.dvi_pd_gpio))
|
||||
omap_mux_init_gpio(beagle_config.dvi_pd_gpio, OMAP_PIN_OUTPUT);
|
||||
omap_display_init(&beagle_dss_data);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
|
||||
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
|
||||
/* REVISIT leave DVI powered down until it's needed ... */
|
||||
gpio_request_one(170, GPIOF_OUT_INIT_HIGH, "DVI_nPD");
|
||||
|
||||
usb_musb_init(NULL);
|
||||
usbhs_init(&usbhs_bdata);
|
||||
omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
|
||||
|
|
|
|||
|
|
@ -144,7 +144,6 @@ static struct lis3lv02d_platform_data rx51_lis3lv02d_data = {
|
|||
.release_resources = lis302_release,
|
||||
.st_min_limits = {-32, 3, 3},
|
||||
.st_max_limits = {-3, 32, 32},
|
||||
.irq2 = OMAP_GPIO_IRQ(LIS302_IRQ2_GPIO),
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -1030,7 +1029,6 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_3[] = {
|
|||
{
|
||||
I2C_BOARD_INFO("lis3lv02d", 0x1d),
|
||||
.platform_data = &rx51_lis3lv02d_data,
|
||||
.irq = OMAP_GPIO_IRQ(LIS302_IRQ1_GPIO),
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
|
@ -1056,6 +1054,10 @@ static int __init rx51_i2c_init(void)
|
|||
omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
|
||||
omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
|
||||
ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
|
||||
#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
|
||||
rx51_lis3lv02d_data.irq2 = gpio_to_irq(LIS302_IRQ2_GPIO);
|
||||
rx51_peripherals_i2c_board_info_3[0].irq = gpio_to_irq(LIS302_IRQ1_GPIO);
|
||||
#endif
|
||||
omap_register_i2c_bus(3, 400, rx51_peripherals_i2c_board_info_3,
|
||||
ARRAY_SIZE(rx51_peripherals_i2c_board_info_3));
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -3514,7 +3514,7 @@ int __init omap3xxx_clk_init(void)
|
|||
struct omap_clk *c;
|
||||
u32 cpu_clkflg = 0;
|
||||
|
||||
if (cpu_is_omap3517()) {
|
||||
if (soc_is_am35xx()) {
|
||||
cpu_mask = RATE_IN_34XX;
|
||||
cpu_clkflg = CK_AM35XX;
|
||||
} else if (cpu_is_omap3630()) {
|
||||
|
|
|
|||
|
|
@ -84,6 +84,7 @@ static struct clk slimbus_clk = {
|
|||
|
||||
static struct clk sys_32k_ck = {
|
||||
.name = "sys_32k_ck",
|
||||
.clkdm_name = "prm_clkdm",
|
||||
.rate = 32768,
|
||||
.ops = &clkops_null,
|
||||
};
|
||||
|
|
@ -512,6 +513,7 @@ static struct clk ddrphy_ck = {
|
|||
.name = "ddrphy_ck",
|
||||
.parent = &dpll_core_m2_ck,
|
||||
.ops = &clkops_null,
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.fixed_div = 2,
|
||||
.recalc = &omap_fixed_divisor_recalc,
|
||||
};
|
||||
|
|
@ -769,6 +771,7 @@ static const struct clksel dpll_mpu_m2_div[] = {
|
|||
static struct clk dpll_mpu_m2_ck = {
|
||||
.name = "dpll_mpu_m2_ck",
|
||||
.parent = &dpll_mpu_ck,
|
||||
.clkdm_name = "cm_clkdm",
|
||||
.clksel = dpll_mpu_m2_div,
|
||||
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
|
||||
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
|
||||
|
|
@ -1149,6 +1152,7 @@ static const struct clksel l3_div_div[] = {
|
|||
static struct clk l3_div_ck = {
|
||||
.name = "l3_div_ck",
|
||||
.parent = &div_core_ck,
|
||||
.clkdm_name = "cm_clkdm",
|
||||
.clksel = l3_div_div,
|
||||
.clksel_reg = OMAP4430_CM_CLKSEL_CORE,
|
||||
.clksel_mask = OMAP4430_CLKSEL_L3_MASK,
|
||||
|
|
@ -2824,6 +2828,7 @@ static const struct clksel trace_clk_div_div[] = {
|
|||
static struct clk trace_clk_div_ck = {
|
||||
.name = "trace_clk_div_ck",
|
||||
.parent = &pmd_trace_clk_mux_ck,
|
||||
.clkdm_name = "emu_sys_clkdm",
|
||||
.clksel = trace_clk_div_div,
|
||||
.clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
|
||||
.clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
|
||||
|
|
|
|||
|
|
@ -22,4 +22,15 @@
|
|||
*/
|
||||
#define MAX_MODULE_READY_TIME 2000
|
||||
|
||||
/*
|
||||
* MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for
|
||||
* the PRCM to request that a module enter the inactive state in the
|
||||
* case of OMAP2 & 3. In the case of OMAP4 this is the max duration
|
||||
* in microseconds for the module to reach the inactive state from
|
||||
* a functional state.
|
||||
* XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during
|
||||
* kernel init.
|
||||
*/
|
||||
#define MAX_MODULE_DISABLE_TIME 5000
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -313,9 +313,9 @@ int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_off
|
|||
|
||||
omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
|
||||
CLKCTRL_IDLEST_DISABLED),
|
||||
MAX_MODULE_READY_TIME, i);
|
||||
MAX_MODULE_DISABLE_TIME, i);
|
||||
|
||||
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
|
||||
return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -271,9 +271,9 @@ static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
|
|||
goto err;
|
||||
}
|
||||
|
||||
r = omap_device_register(pdev);
|
||||
r = platform_device_add(pdev);
|
||||
if (r) {
|
||||
pr_err("Could not register omap_device for %s\n", pdev_name);
|
||||
pr_err("Could not register platform_device for %s\n", pdev_name);
|
||||
goto err;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,9 @@
|
|||
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/memblock.h>
|
||||
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "prm2xxx_3xxx.h"
|
||||
#ifdef CONFIG_BRIDGE_DVFS
|
||||
|
|
|
|||
|
|
@ -246,6 +246,17 @@ void __init omap3xxx_check_features(void)
|
|||
|
||||
omap_features |= OMAP3_HAS_SDRC;
|
||||
|
||||
/*
|
||||
* am35x fixups:
|
||||
* - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
|
||||
* reserved and therefore return 0 when read. Unfortunately,
|
||||
* OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
|
||||
* mean that a feature is present even though it isn't so clear
|
||||
* the incorrectly set feature bits.
|
||||
*/
|
||||
if (soc_is_am35xx())
|
||||
omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
|
||||
|
||||
/*
|
||||
* TODO: Get additional info (where applicable)
|
||||
* e.g. Size of L2 cache.
|
||||
|
|
|
|||
|
|
@ -149,6 +149,7 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
|
|||
ct->chip.irq_ack = omap_mask_ack_irq;
|
||||
ct->chip.irq_mask = irq_gc_mask_disable_reg;
|
||||
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
|
||||
ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
|
||||
|
||||
ct->regs.enable = INTC_MIR_CLEAR0;
|
||||
ct->regs.disable = INTC_MIR_SET0;
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#include "control.h"
|
||||
#include "mux.h"
|
||||
#include "prm.h"
|
||||
#include "common.h"
|
||||
|
||||
#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
|
||||
#define OMAP_MUX_BASE_SZ 0x5ca
|
||||
|
|
@ -217,8 +218,7 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int __init
|
||||
omap_mux_get_by_name(const char *muxname,
|
||||
int __init omap_mux_get_by_name(const char *muxname,
|
||||
struct omap_mux_partition **found_partition,
|
||||
struct omap_mux **found_mux)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@
|
|||
#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
|
||||
|
||||
#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
|
||||
#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
|
||||
|
||||
/* Flags for omapX_mux_init */
|
||||
#define OMAP_PACKAGE_MASK 0xffff
|
||||
|
|
@ -225,8 +226,18 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
|
|||
*/
|
||||
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
|
||||
|
||||
int omap_mux_get_by_name(const char *muxname,
|
||||
struct omap_mux_partition **found_partition,
|
||||
struct omap_mux **found_mux);
|
||||
#else
|
||||
|
||||
static inline int omap_mux_get_by_name(const char *muxname,
|
||||
struct omap_mux_partition **found_partition,
|
||||
struct omap_mux **found_mux)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int omap_mux_init_gpio(int gpio, int val)
|
||||
{
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -530,7 +530,7 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
|
|||
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
|
||||
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
|
||||
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
|
||||
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
|
||||
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v);
|
||||
|
||||
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
|
||||
|
||||
|
|
|
|||
|
|
@ -393,8 +393,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
|
|||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0004,
|
||||
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
SIDLE_SMART_WKUP),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
|
|
@ -854,6 +853,11 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
|
|||
.name = "dss_hdmi",
|
||||
.class = &omap44xx_hdmi_hwmod_class,
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
/*
|
||||
* HDMI audio requires to use no-idle mode. Hence,
|
||||
* set idle mode by software.
|
||||
*/
|
||||
.flags = HWMOD_SWSUP_SIDLE,
|
||||
.mpu_irqs = omap44xx_dss_hdmi_irqs,
|
||||
.sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
|
||||
.main_clk = "dss_48mhz_clk",
|
||||
|
|
|
|||
|
|
@ -155,10 +155,11 @@ static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
|
|||
u8 multi = error & L3_ERROR_LOG_MULTI;
|
||||
u32 address = omap3_l3_decode_addr(error_addr);
|
||||
|
||||
WARN(true, "%s seen by %s %s at address %x\n",
|
||||
pr_err("%s seen by %s %s at address %x\n",
|
||||
omap3_l3_code_string(code),
|
||||
omap3_l3_initiator_string(initid),
|
||||
multi ? "Multiple Errors" : "", address);
|
||||
WARN_ON(1);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -239,21 +239,15 @@ void am35x_set_mode(u8 musb_mode)
|
|||
|
||||
devconf2 &= ~CONF2_OTGMODE;
|
||||
switch (musb_mode) {
|
||||
#ifdef CONFIG_USB_MUSB_HDRC_HCD
|
||||
case MUSB_HOST: /* Force VBUS valid, ID = 0 */
|
||||
devconf2 |= CONF2_FORCE_HOST;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
|
||||
case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
|
||||
devconf2 |= CONF2_FORCE_DEVICE;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_USB_MUSB_OTG
|
||||
case MUSB_OTG: /* Don't override the VBUS/ID comparators */
|
||||
devconf2 |= CONF2_NO_OVERRIDE;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -724,6 +724,7 @@ int __init omap3_pm_init(void)
|
|||
ret = request_irq(omap_prcm_event_to_irq("io"),
|
||||
_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
|
||||
omap3_pm_init);
|
||||
enable_irq(omap_prcm_event_to_irq("io"));
|
||||
|
||||
if (ret) {
|
||||
pr_err("pm: Failed to request pm_io irq\n");
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include "common.h"
|
||||
#include <plat/cpu.h>
|
||||
|
|
@ -303,8 +304,15 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
|
|||
|
||||
static int __init omap3xxx_prcm_init(void)
|
||||
{
|
||||
if (cpu_is_omap34xx())
|
||||
return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
|
||||
return 0;
|
||||
int ret = 0;
|
||||
|
||||
if (cpu_is_omap34xx()) {
|
||||
ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
|
||||
if (!ret)
|
||||
irq_set_status_flags(omap_prcm_event_to_irq("io"),
|
||||
IRQ_NOAUTOEN);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
subsys_initcall(omap3xxx_prcm_init);
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ struct omap_uart_state {
|
|||
|
||||
struct list_head node;
|
||||
struct omap_hwmod *oh;
|
||||
struct omap_device_pad default_omap_uart_pads[2];
|
||||
};
|
||||
|
||||
static LIST_HEAD(uart_list);
|
||||
|
|
@ -126,11 +127,70 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {}
|
|||
#endif /* CONFIG_PM */
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
|
||||
|
||||
#define OMAP_UART_DEFAULT_PAD_NAME_LEN 28
|
||||
static char rx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN],
|
||||
tx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN] __initdata;
|
||||
|
||||
static void __init
|
||||
omap_serial_fill_uart_tx_rx_pads(struct omap_board_data *bdata,
|
||||
struct omap_uart_state *uart)
|
||||
{
|
||||
uart->default_omap_uart_pads[0].name = rx_pad_name;
|
||||
uart->default_omap_uart_pads[0].flags = OMAP_DEVICE_PAD_REMUX |
|
||||
OMAP_DEVICE_PAD_WAKEUP;
|
||||
uart->default_omap_uart_pads[0].enable = OMAP_PIN_INPUT |
|
||||
OMAP_MUX_MODE0;
|
||||
uart->default_omap_uart_pads[0].idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0;
|
||||
uart->default_omap_uart_pads[1].name = tx_pad_name;
|
||||
uart->default_omap_uart_pads[1].enable = OMAP_PIN_OUTPUT |
|
||||
OMAP_MUX_MODE0;
|
||||
bdata->pads = uart->default_omap_uart_pads;
|
||||
bdata->pads_cnt = ARRAY_SIZE(uart->default_omap_uart_pads);
|
||||
}
|
||||
|
||||
static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
|
||||
struct omap_uart_state *uart)
|
||||
{
|
||||
struct omap_mux_partition *tx_partition = NULL, *rx_partition = NULL;
|
||||
struct omap_mux *rx_mux = NULL, *tx_mux = NULL;
|
||||
char *rx_fmt, *tx_fmt;
|
||||
int uart_nr = bdata->id + 1;
|
||||
|
||||
if (bdata->id != 2) {
|
||||
rx_fmt = "uart%d_rx.uart%d_rx";
|
||||
tx_fmt = "uart%d_tx.uart%d_tx";
|
||||
} else {
|
||||
rx_fmt = "uart%d_rx_irrx.uart%d_rx_irrx";
|
||||
tx_fmt = "uart%d_tx_irtx.uart%d_tx_irtx";
|
||||
}
|
||||
|
||||
snprintf(rx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, rx_fmt,
|
||||
uart_nr, uart_nr);
|
||||
snprintf(tx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, tx_fmt,
|
||||
uart_nr, uart_nr);
|
||||
|
||||
if (omap_mux_get_by_name(rx_pad_name, &rx_partition, &rx_mux) >= 0 &&
|
||||
omap_mux_get_by_name
|
||||
(tx_pad_name, &tx_partition, &tx_mux) >= 0) {
|
||||
u16 tx_mode, rx_mode;
|
||||
|
||||
tx_mode = omap_mux_read(tx_partition, tx_mux->reg_offset);
|
||||
rx_mode = omap_mux_read(rx_partition, rx_mux->reg_offset);
|
||||
|
||||
/*
|
||||
* Check if uart is used in default tx/rx mode i.e. in mux mode0
|
||||
* if yes then configure rx pin for wake up capability
|
||||
*/
|
||||
if (OMAP_MODE_UART(rx_mode) && OMAP_MODE_UART(tx_mode))
|
||||
omap_serial_fill_uart_tx_rx_pads(bdata, uart);
|
||||
}
|
||||
}
|
||||
#else
|
||||
static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
|
||||
static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
|
||||
struct omap_uart_state *uart)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
static char *cmdline_find_option(char *str)
|
||||
|
|
@ -287,8 +347,7 @@ void __init omap_serial_board_init(struct omap_uart_port_info *info)
|
|||
bdata.pads = NULL;
|
||||
bdata.pads_cnt = 0;
|
||||
|
||||
if (cpu_is_omap44xx() || cpu_is_omap34xx())
|
||||
omap_serial_fill_default_pads(&bdata);
|
||||
omap_serial_check_wakeup(&bdata, uart);
|
||||
|
||||
if (!info)
|
||||
omap_serial_init_port(&bdata, NULL);
|
||||
|
|
|
|||
|
|
@ -41,12 +41,10 @@ static struct musb_hdrc_config musb_config = {
|
|||
};
|
||||
|
||||
static struct musb_hdrc_platform_data musb_plat = {
|
||||
#ifdef CONFIG_USB_MUSB_OTG
|
||||
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
|
||||
.mode = MUSB_OTG,
|
||||
#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
|
||||
#else
|
||||
.mode = MUSB_HOST,
|
||||
#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
|
||||
.mode = MUSB_PERIPHERAL,
|
||||
#endif
|
||||
/* .clock is set dynamically */
|
||||
.config = &musb_config,
|
||||
|
|
|
|||
|
|
@ -300,7 +300,7 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
|
|||
printk(error, 3, status);
|
||||
return status;
|
||||
}
|
||||
tusb_resources[2].start = irq + IH_GPIO_BASE;
|
||||
tusb_resources[2].start = gpio_to_irq(irq);
|
||||
|
||||
/* set up memory timings ... can speed them up later */
|
||||
if (!ps_refclk) {
|
||||
|
|
|
|||
|
|
@ -35,5 +35,5 @@
|
|||
#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204)
|
||||
|
||||
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
|
||||
|
||||
#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE | 0x300)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* arch/arm/mach-orion5x/include/mach/io.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IO_H
|
||||
#define __ASM_ARCH_IO_H
|
||||
|
||||
#include <mach/orion5x.h>
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#define IO_SPACE_LIMIT SZ_2M
|
||||
static inline void __iomem *__io(unsigned long addr)
|
||||
{
|
||||
return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE);
|
||||
}
|
||||
|
||||
#define __io(a) __io(a)
|
||||
#endif
|
||||
|
|
@ -82,6 +82,7 @@
|
|||
#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
|
||||
|
||||
#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
|
||||
#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x20000)
|
||||
|
||||
#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
|
||||
|
||||
|
|
|
|||
|
|
@ -186,6 +186,12 @@ config SH_TIMER_TMU
|
|||
help
|
||||
This enables build of the TMU timer driver.
|
||||
|
||||
config EM_TIMER_STI
|
||||
bool "STI timer driver"
|
||||
default y
|
||||
help
|
||||
This enables build of the STI timer driver.
|
||||
|
||||
endmenu
|
||||
|
||||
config SH_CLK_CPG
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Debugging macro include header spear13xx machine family
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* DMA information for SPEAr13xx machine family
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* spear13xx machine family generic header file
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* GPIO macros for SPEAr13xx machine family
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* IRQ helper macros for spear13xx machine family
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* spear13xx Machine family specific definition
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* SPEAr3XX machine family specific timex definitions
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Serial port stubs for kernel decompress status messages
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* SPEAr1310 machine source file
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* SPEAr1340 machine source file
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* SPEAr13XX machines common source file
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Debugging macro include header spear3xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Viresh Kumar<viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* SPEAr3XX machine family generic header file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Viresh Kumar<viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* GPIO macros for SPEAr3xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Viresh Kumar<viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* IRQ helper macros for SPEAr3xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Miscellaneous registers definitions for SPEAr3xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* SPEAr3xx Machine family specific definition
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* SPEAr3XX machine family specific timex definitions
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
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