clk: imx: gate2: Add cgr_mask for more flexible number of control bits
On some i.MX8 platforms, there are HW gates that share the same bit. So in order to make this clock type more usable, use a mask to specify how many bits belong to those HW gates. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Abel Vesa
Shawn Guo
Родитель
03681d06a5
Коммит
bcd418a632
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@ -30,6 +30,7 @@ struct clk_gate2 {
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void __iomem *reg;
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u8 bit_idx;
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u8 cgr_val;
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u8 cgr_mask;
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u8 flags;
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spinlock_t *lock;
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unsigned int *share_count;
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@ -43,9 +44,9 @@ static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable)
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u32 reg;
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reg = readl(gate->reg);
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reg &= ~(3 << gate->bit_idx);
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reg &= ~(gate->cgr_mask << gate->bit_idx);
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if (enable)
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reg |= gate->cgr_val << gate->bit_idx;
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reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx;
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writel(reg, gate->reg);
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}
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@ -86,11 +87,12 @@ out:
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx, u8 cgr_val)
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static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx,
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u8 cgr_val, u8 cgr_mask)
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{
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u32 val = readl(reg);
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if (((val >> bit_idx) & 3) == cgr_val)
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if (((val >> bit_idx) & cgr_mask) == cgr_val)
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return 1;
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return 0;
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@ -100,7 +102,8 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
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{
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struct clk_gate2 *gate = to_clk_gate2(hw);
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return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx, gate->cgr_val);
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return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx,
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gate->cgr_val, gate->cgr_mask);
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}
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static void clk_gate2_disable_unused(struct clk_hw *hw)
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@ -125,7 +128,7 @@ static const struct clk_ops clk_gate2_ops = {
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struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
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u8 clk_gate2_flags, spinlock_t *lock,
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unsigned int *share_count)
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{
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@ -142,6 +145,7 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
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gate->reg = reg;
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gate->bit_idx = bit_idx;
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gate->cgr_val = cgr_val;
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gate->cgr_mask = cgr_mask;
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gate->flags = clk_gate2_flags;
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gate->lock = lock;
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gate->share_count = share_count;
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@ -66,9 +66,9 @@ extern struct imx_pll14xx_clk imx_1443x_dram_pll;
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to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
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#define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
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cgr_val, clk_gate_flags, lock, share_count) \
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cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
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to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
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cgr_val, clk_gate_flags, lock, share_count))
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cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
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#define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
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to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
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@ -196,7 +196,7 @@ struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
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struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
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u8 clk_gate_flags, spinlock_t *lock,
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unsigned int *share_count);
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@ -349,14 +349,14 @@ static inline struct clk_hw *imx_clk_hw_gate2(const char *name, const char *pare
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void __iomem *reg, u8 shift)
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{
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return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0x3, 0, &imx_ccm_lock, NULL);
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shift, 0x3, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk_hw *imx_clk_hw_gate2_flags(const char *name, const char *parent,
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void __iomem *reg, u8 shift, unsigned long flags)
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{
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return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
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shift, 0x3, 0, &imx_ccm_lock, NULL);
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shift, 0x3, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk_hw *imx_clk_hw_gate2_shared(const char *name,
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@ -364,7 +364,7 @@ static inline struct clk_hw *imx_clk_hw_gate2_shared(const char *name,
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unsigned int *share_count)
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{
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return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0x3, 0, &imx_ccm_lock, share_count);
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shift, 0x3, 0x3, 0, &imx_ccm_lock, share_count);
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}
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static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name,
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@ -372,7 +372,7 @@ static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name,
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unsigned int *share_count)
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{
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return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
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CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
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CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0x3, 0,
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&imx_ccm_lock, share_count);
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}
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@ -382,15 +382,15 @@ static inline struct clk_hw *imx_dev_clk_hw_gate_shared(struct device *dev,
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unsigned int *share_count)
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{
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return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
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CLK_OPS_PARENT_ENABLE, reg, shift, 0x1, 0,
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&imx_ccm_lock, share_count);
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CLK_OPS_PARENT_ENABLE, reg, shift, 0x1,
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0x1, 0, &imx_ccm_lock, share_count);
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}
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static inline struct clk *imx_clk_gate2_cgr(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, cgr_val, 0, &imx_ccm_lock, NULL);
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shift, cgr_val, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent,
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@ -418,7 +418,7 @@ static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *pare
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{
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return clk_hw_register_gate2(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
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reg, shift, 0x3, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name,
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@ -427,7 +427,7 @@ static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name,
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{
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return clk_hw_register_gate2(NULL, name, parent,
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flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
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reg, shift, 0x3, 0x3, 0, &imx_ccm_lock, NULL);
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}
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#define imx_clk_gate4_flags(name, parent, reg, shift, flags) \
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