drm: bridge: analogix/dp: add some rk3288 special registers setting
RK3288 need some special registers setting, we can separate them out by the dev_type of plat_data. Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
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@ -15,6 +15,8 @@
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <drm/bridge/analogix_dp.h>
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#include "analogix_dp_core.h"
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#include "analogix_dp_reg.h"
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@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
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reg = SEL_24M | TX_DVDD_BIT_1_0625V;
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writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
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if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
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writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
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writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
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writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
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writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
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writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
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}
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reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
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writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
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@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
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bool enable)
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{
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u32 reg;
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u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
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if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
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phy_pd_addr = ANALOGIX_DP_PD;
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switch (block) {
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case AUX_BLOCK:
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if (enable) {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg |= AUX_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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} else {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg &= ~AUX_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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}
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break;
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case CH0_BLOCK:
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if (enable) {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg |= CH0_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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} else {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg &= ~CH0_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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}
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break;
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case CH1_BLOCK:
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if (enable) {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg |= CH1_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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} else {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg &= ~CH1_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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}
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break;
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case CH2_BLOCK:
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if (enable) {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg |= CH2_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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} else {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg &= ~CH2_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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}
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break;
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case CH3_BLOCK:
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if (enable) {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg |= CH3_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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} else {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg &= ~CH3_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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}
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break;
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case ANALOG_TOTAL:
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if (enable) {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg |= DP_PHY_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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} else {
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reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
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reg = readl(dp->reg_base + phy_pd_addr);
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reg &= ~DP_PHY_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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}
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break;
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case POWER_ALL:
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if (enable) {
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reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
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CH1_PD | CH0_PD;
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writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(reg, dp->reg_base + phy_pd_addr);
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} else {
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writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
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writel(0x00, dp->reg_base + phy_pd_addr);
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}
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break;
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default:
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@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
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analogix_dp_reset_aux(dp);
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/* Disable AUX transaction H/W retry */
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reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
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AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
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if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
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reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
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AUX_HW_RETRY_COUNT_SEL(3) |
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AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
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else
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reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
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AUX_HW_RETRY_COUNT_SEL(0) |
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AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
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writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
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/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
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@ -22,6 +22,14 @@
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#define ANALOGIX_DP_VIDEO_CTL_8 0x3C
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#define ANALOGIX_DP_VIDEO_CTL_10 0x44
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#define ANALOGIX_DP_PLL_REG_1 0xfc
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#define ANALOGIX_DP_PLL_REG_2 0x9e4
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#define ANALOGIX_DP_PLL_REG_3 0x9e8
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#define ANALOGIX_DP_PLL_REG_4 0x9ec
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#define ANALOGIX_DP_PLL_REG_5 0xa00
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#define ANALOGIX_DP_PD 0x12c
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#define ANALOGIX_DP_LANE_MAP 0x35C
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#define ANALOGIX_DP_ANALOG_CTL_1 0x370
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@ -154,6 +162,10 @@
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#define VSYNC_POLARITY_CFG (0x1 << 1)
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#define HSYNC_POLARITY_CFG (0x1 << 0)
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/* ANALOGIX_DP_PLL_REG_1 */
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#define REF_CLK_24M (0x1 << 1)
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#define REF_CLK_27M (0x0 << 1)
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/* ANALOGIX_DP_LANE_MAP */
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#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
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#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
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