drm/amdgpu: Handle irqs only based on irq ring, not irq status regs.
This is a translation of the patch ... "drm/radeon: Handle irqs only based on irq ring, not irq status regs." ... for the vblank irq handling, to fix the same problem described in that patch on the new driver. Only compile tested due to lack of suitable hw. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> CC: Michel Dänzer <michel.daenzer@amd.com> CC: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3403,19 +3403,25 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
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switch (entry->src_data) {
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case 0: /* vblank */
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if (disp_int & interrupt_status_offsets[crtc].vblank) {
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if (disp_int & interrupt_status_offsets[crtc].vblank)
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dce_v10_0_crtc_vblank_int_ack(adev, crtc);
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if (amdgpu_irq_enabled(adev, source, irq_type)) {
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drm_handle_vblank(adev->ddev, crtc);
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}
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DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
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else
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DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
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if (amdgpu_irq_enabled(adev, source, irq_type)) {
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drm_handle_vblank(adev->ddev, crtc);
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}
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DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
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break;
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case 1: /* vline */
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if (disp_int & interrupt_status_offsets[crtc].vline) {
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if (disp_int & interrupt_status_offsets[crtc].vline)
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dce_v10_0_crtc_vline_int_ack(adev, crtc);
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DRM_DEBUG("IH: D%d vline\n", crtc + 1);
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}
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else
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DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
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DRM_DEBUG("IH: D%d vline\n", crtc + 1);
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break;
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default:
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DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
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@ -3402,19 +3402,25 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
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switch (entry->src_data) {
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case 0: /* vblank */
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if (disp_int & interrupt_status_offsets[crtc].vblank) {
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if (disp_int & interrupt_status_offsets[crtc].vblank)
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dce_v11_0_crtc_vblank_int_ack(adev, crtc);
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if (amdgpu_irq_enabled(adev, source, irq_type)) {
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drm_handle_vblank(adev->ddev, crtc);
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}
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DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
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else
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DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
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if (amdgpu_irq_enabled(adev, source, irq_type)) {
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drm_handle_vblank(adev->ddev, crtc);
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}
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DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
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break;
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case 1: /* vline */
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if (disp_int & interrupt_status_offsets[crtc].vline) {
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if (disp_int & interrupt_status_offsets[crtc].vline)
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dce_v11_0_crtc_vline_int_ack(adev, crtc);
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DRM_DEBUG("IH: D%d vline\n", crtc + 1);
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}
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else
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DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
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DRM_DEBUG("IH: D%d vline\n", crtc + 1);
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break;
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default:
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DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
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@ -3237,19 +3237,25 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
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switch (entry->src_data) {
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case 0: /* vblank */
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if (disp_int & interrupt_status_offsets[crtc].vblank) {
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if (disp_int & interrupt_status_offsets[crtc].vblank)
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WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
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if (amdgpu_irq_enabled(adev, source, irq_type)) {
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drm_handle_vblank(adev->ddev, crtc);
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}
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DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
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else
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DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
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if (amdgpu_irq_enabled(adev, source, irq_type)) {
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drm_handle_vblank(adev->ddev, crtc);
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}
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DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
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break;
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case 1: /* vline */
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if (disp_int & interrupt_status_offsets[crtc].vline) {
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if (disp_int & interrupt_status_offsets[crtc].vline)
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WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
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DRM_DEBUG("IH: D%d vline\n", crtc + 1);
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}
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else
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DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
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DRM_DEBUG("IH: D%d vline\n", crtc + 1);
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break;
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default:
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DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
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