Reset controller changes for v4.5 v2
- oftree support for getting reset devices by index - fixed return value consistency of of_reset_control_get - added support for STi co-processor resets - added STi status callback - added HiSilicon Hi6220 reset driver - added ath79 system restart support - various fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWX/etAAoJEFDCiBxwnmDrw40QAJJ7oUucjj6zqH4G6lS0EQ+e xmEutp7u7F94DwIuvB9wTXGqdZuLX5Fho/LArMZuBoQVZ/JTtbQ9e/uJLdNQRiLo sDXlD+MaS2TJxTpwC8CQZfrqK/GRLyhMW8AwfVQJYkOuzvaYLswZd45/kytFXKpq SFU91Yy4Yi4uguwT8TCDZmzM4DyLiZ7IFBBGrrj/mwjmc+G4Zv+EHAojwgeeuTXV FcGUFMWoKhyWRQTlWjj76UeVCViqho/YOzGLHY4nG4ZdjgAi+q+nX/HtSL5/qb4z OWkQ5sFV3tsktjr3GTuTN0ffewlOAGdEtHcpMcX/QL3+TR3VFBiV6H6CxRYAyeP2 B6r7Nx8Itf8x1cigkEsM+TxrUccAcN47IulK/vgZReuPa90K2oFuYzVSjQE/2oe5 +sUGFlFdQiLnTW0PCAxMUqY5p1QvNE6/u1p/Qmu8X8pg3GFKX3AnyZTSgMhDOZGQ 3BCftjjICiifkmplvLlnRtmpfqdEgdTEIX807fqep6ZCFizwD6qD8FvbsNufYvgi M+nwYjAXvRNeUM5Ck+/EfBEKwjgY+awPwz4DKD5VQvH2B3Efafydzutxn5e48VuI bMkzbmLoC62JCLTzG89+UQgZDtMWLorzGbnHvroRlkI/LrClKgtFbkdHmRgi1Euz wQ2cx1V1wC7MsmMIjoV0 =TXCk -----END PGP SIGNATURE----- Merge tag 'reset-for-4.5-2' of git://git.pengutronix.de/git/pza/linux into next/drivers Merge "Reset controller changes for v4.5 v2" from Philipp Zabel: - oftree support for getting reset devices by index - fixed return value consistency of of_reset_control_get - added support for STi co-processor resets - added STi status callback - added HiSilicon Hi6220 reset driver - added ath79 system restart support - various fixes * tag 'reset-for-4.5-2' of git://git.pengutronix.de/git/pza/linux: reset: ath79: Add system restart support arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC reset: hi6220: Reset driver for hisilicon hi6220 SoC reset: hisilicon: document hisi-hi6220 reset controllers bindings reset: remove unused device pointer from struct reset_control
This commit is contained in:
Arnd Bergmann
Коммит
bd8f27ba82
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@ -0,0 +1,34 @@
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Hisilicon System Reset Controller
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======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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The reset controller registers are part of the system-ctl block on
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hi6220 SoC.
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Required properties:
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- compatible: may be "hisilicon,hi6220-sysctrl"
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- reg: should be register base and length as documented in the
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datasheet
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- #reset-cells: 1, see below
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Example:
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sys_ctrl: sys_ctrl@f7030000 {
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compatible = "hisilicon,hi6220-sysctrl", "syscon";
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reg = <0x0 0xf7030000 0x0 0x2000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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example:
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uart1: serial@..... {
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...
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resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
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...
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};
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The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>.
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@ -147,6 +147,7 @@
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compatible = "hisilicon,hi6220-sysctrl", "syscon";
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reg = <0x0 0xf7030000 0x0 0x2000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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media_ctrl: media_ctrl@f4410000 {
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@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
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If unsure, say no.
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source "drivers/reset/sti/Kconfig"
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source "drivers/reset/hisilicon/Kconfig"
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@ -4,5 +4,6 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
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obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_ARCH_STI) += sti/
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obj-$(CONFIG_ARCH_HISI) += hisilicon/
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obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
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obj-$(CONFIG_ATH79) += reset-ath79.o
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@ -30,7 +30,6 @@ static LIST_HEAD(reset_controller_list);
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*/
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struct reset_control {
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struct reset_controller_dev *rcdev;
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struct device *dev;
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unsigned int id;
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};
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@ -236,16 +235,10 @@ EXPORT_SYMBOL_GPL(of_reset_control_get);
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*/
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struct reset_control *reset_control_get(struct device *dev, const char *id)
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{
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struct reset_control *rstc;
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if (!dev)
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return ERR_PTR(-EINVAL);
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rstc = of_reset_control_get(dev->of_node, id);
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if (!IS_ERR(rstc))
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rstc->dev = dev;
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return rstc;
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return of_reset_control_get(dev->of_node, id);
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}
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EXPORT_SYMBOL_GPL(reset_control_get);
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@ -0,0 +1,5 @@
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config COMMON_RESET_HI6220
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tristate "Hi6220 Reset Driver"
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depends on (ARCH_HISI && RESET_CONTROLLER)
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help
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Build the Hisilicon Hi6220 reset driver.
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@ -0,0 +1 @@
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obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
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@ -0,0 +1,108 @@
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/*
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* Hisilicon Hi6220 reset controller driver
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*
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* Copyright (c) 2015 Hisilicon Limited.
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*
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* Author: Feng Chen <puck.chen@hisilicon.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/of.h>
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#include <linux/reset-controller.h>
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#include <linux/reset.h>
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#include <linux/platform_device.h>
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#define ASSERT_OFFSET 0x300
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#define DEASSERT_OFFSET 0x304
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#define MAX_INDEX 0x509
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#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
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struct hi6220_reset_data {
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void __iomem *assert_base;
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void __iomem *deassert_base;
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struct reset_controller_dev rc_dev;
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};
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static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
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unsigned long idx)
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{
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struct hi6220_reset_data *data = to_reset_data(rc_dev);
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int bank = idx >> 8;
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int offset = idx & 0xff;
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writel(BIT(offset), data->assert_base + (bank * 0x10));
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return 0;
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}
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static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
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unsigned long idx)
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{
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struct hi6220_reset_data *data = to_reset_data(rc_dev);
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int bank = idx >> 8;
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int offset = idx & 0xff;
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writel(BIT(offset), data->deassert_base + (bank * 0x10));
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return 0;
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}
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static struct reset_control_ops hi6220_reset_ops = {
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.assert = hi6220_reset_assert,
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.deassert = hi6220_reset_deassert,
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};
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static int hi6220_reset_probe(struct platform_device *pdev)
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{
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struct hi6220_reset_data *data;
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struct resource *res;
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void __iomem *src_base;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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src_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(src_base))
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return PTR_ERR(src_base);
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data->assert_base = src_base + ASSERT_OFFSET;
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data->deassert_base = src_base + DEASSERT_OFFSET;
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data->rc_dev.nr_resets = MAX_INDEX;
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data->rc_dev.ops = &hi6220_reset_ops;
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data->rc_dev.of_node = pdev->dev.of_node;
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reset_controller_register(&data->rc_dev);
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return 0;
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}
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static const struct of_device_id hi6220_reset_match[] = {
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{ .compatible = "hisilicon,hi6220-sysctrl" },
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{ },
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};
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static struct platform_driver hi6220_reset_driver = {
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.probe = hi6220_reset_probe,
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.driver = {
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.name = "reset-hi6220",
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.of_match_table = hi6220_reset_match,
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},
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};
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static int __init hi6220_reset_init(void)
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{
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return platform_driver_register(&hi6220_reset_driver);
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}
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postcore_initcall(hi6220_reset_init);
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@ -15,13 +15,17 @@
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/reboot.h>
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struct ath79_reset {
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struct reset_controller_dev rcdev;
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struct notifier_block restart_nb;
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void __iomem *base;
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spinlock_t lock;
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};
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#define FULL_CHIP_RESET 24
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static int ath79_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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@ -72,10 +76,22 @@ static struct reset_control_ops ath79_reset_ops = {
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.status = ath79_reset_status,
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};
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static int ath79_reset_restart_handler(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct ath79_reset *ath79_reset =
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container_of(nb, struct ath79_reset, restart_nb);
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ath79_reset_assert(&ath79_reset->rcdev, FULL_CHIP_RESET);
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return NOTIFY_DONE;
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}
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static int ath79_reset_probe(struct platform_device *pdev)
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{
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struct ath79_reset *ath79_reset;
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struct resource *res;
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int err;
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ath79_reset = devm_kzalloc(&pdev->dev,
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sizeof(*ath79_reset), GFP_KERNEL);
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@ -96,13 +112,25 @@ static int ath79_reset_probe(struct platform_device *pdev)
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ath79_reset->rcdev.of_reset_n_cells = 1;
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ath79_reset->rcdev.nr_resets = 32;
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return reset_controller_register(&ath79_reset->rcdev);
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err = reset_controller_register(&ath79_reset->rcdev);
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if (err)
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return err;
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ath79_reset->restart_nb.notifier_call = ath79_reset_restart_handler;
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ath79_reset->restart_nb.priority = 128;
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err = register_restart_handler(&ath79_reset->restart_nb);
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if (err)
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dev_warn(&pdev->dev, "Failed to register restart handler\n");
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return 0;
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}
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static int ath79_reset_remove(struct platform_device *pdev)
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{
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struct ath79_reset *ath79_reset = platform_get_drvdata(pdev);
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unregister_restart_handler(&ath79_reset->restart_nb);
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reset_controller_unregister(&ath79_reset->rcdev);
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return 0;
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@ -0,0 +1,67 @@
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/**
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* This header provides index for the reset controller
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* based on hi6220 SoC.
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
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#define _DT_BINDINGS_RESET_CONTROLLER_HI6220
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#define PERIPH_RSTDIS0_MMC0 0x000
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#define PERIPH_RSTDIS0_MMC1 0x001
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#define PERIPH_RSTDIS0_MMC2 0x002
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#define PERIPH_RSTDIS0_NANDC 0x003
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#define PERIPH_RSTDIS0_USBOTG_BUS 0x004
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#define PERIPH_RSTDIS0_POR_PICOPHY 0x005
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#define PERIPH_RSTDIS0_USBOTG 0x006
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#define PERIPH_RSTDIS0_USBOTG_32K 0x007
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#define PERIPH_RSTDIS1_HIFI 0x100
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#define PERIPH_RSTDIS1_DIGACODEC 0x105
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#define PERIPH_RSTEN2_IPF 0x200
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#define PERIPH_RSTEN2_SOCP 0x201
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#define PERIPH_RSTEN2_DMAC 0x202
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#define PERIPH_RSTEN2_SECENG 0x203
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#define PERIPH_RSTEN2_ABB 0x204
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#define PERIPH_RSTEN2_HPM0 0x205
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#define PERIPH_RSTEN2_HPM1 0x206
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#define PERIPH_RSTEN2_HPM2 0x207
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#define PERIPH_RSTEN2_HPM3 0x208
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#define PERIPH_RSTEN3_CSSYS 0x300
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#define PERIPH_RSTEN3_I2C0 0x301
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#define PERIPH_RSTEN3_I2C1 0x302
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#define PERIPH_RSTEN3_I2C2 0x303
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#define PERIPH_RSTEN3_I2C3 0x304
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#define PERIPH_RSTEN3_UART1 0x305
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#define PERIPH_RSTEN3_UART2 0x306
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#define PERIPH_RSTEN3_UART3 0x307
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#define PERIPH_RSTEN3_UART4 0x308
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#define PERIPH_RSTEN3_SSP 0x309
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#define PERIPH_RSTEN3_PWM 0x30a
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#define PERIPH_RSTEN3_BLPWM 0x30b
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#define PERIPH_RSTEN3_TSENSOR 0x30c
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#define PERIPH_RSTEN3_DAPB 0x312
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#define PERIPH_RSTEN3_HKADC 0x313
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#define PERIPH_RSTEN3_CODEC_SSI 0x314
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#define PERIPH_RSTEN3_PMUSSI1 0x316
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#define PERIPH_RSTEN8_RS0 0x400
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#define PERIPH_RSTEN8_RS2 0x401
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#define PERIPH_RSTEN8_RS3 0x402
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#define PERIPH_RSTEN8_MS0 0x403
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#define PERIPH_RSTEN8_MS2 0x405
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#define PERIPH_RSTEN8_XG2RAM0 0x406
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#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407
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#define PERIPH_RSTEN8_SRAM 0x408
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#define PERIPH_RSTEN8_HARQ 0x40a
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#define PERIPH_RSTEN8_DDRC 0x40c
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#define PERIPH_RSTEN8_DDRC_APB 0x40d
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#define PERIPH_RSTEN8_DDRPACK_APB 0x40e
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#define PERIPH_RSTEN8_DDRT 0x411
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#define PERIPH_RSDIST9_CARM_DAP 0x500
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#define PERIPH_RSDIST9_CARM_ATB 0x501
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#define PERIPH_RSDIST9_CARM_LBUS 0x502
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#define PERIPH_RSDIST9_CARM_POR 0x503
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#define PERIPH_RSDIST9_CARM_CORE 0x504
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#define PERIPH_RSDIST9_CARM_DBG 0x505
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#define PERIPH_RSDIST9_CARM_L2 0x506
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#define PERIPH_RSDIST9_CARM_SOCDBG 0x507
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#define PERIPH_RSDIST9_CARM_ETM 0x508
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#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
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