thermal: mediatek: add thermal controller offset
One thermal controller can read four sensors at most, so we need to add controller_offset for the project with more than four sensors to reuse the same register settings. Signed-off-by: Michael Kao <michael.kao@mediatek.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Michael Kao
Eduardo Valentin
Родитель
f845147669
Коммит
bd9403943d
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@ -105,6 +105,9 @@
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/* The number of sensing points per bank */
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#define MT8173_NUM_SENSORS_PER_ZONE 4
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/* The number of controller in the MT8173 */
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#define MT8173_NUM_CONTROLLER 1
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/* The calibration coefficient of sensor */
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#define MT8173_CALIBRATION 165
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@ -150,6 +153,9 @@ enum {
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/* The number of sensing points per bank */
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#define MT2701_NUM_SENSORS_PER_ZONE 3
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/* The number of controller in the MT2701 */
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#define MT2701_NUM_CONTROLLER 1
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/* The calibration coefficient of sensor */
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#define MT2701_CALIBRATION 165
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@ -168,6 +174,9 @@ enum {
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/* The number of sensing points per bank */
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#define MT2712_NUM_SENSORS_PER_ZONE 4
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/* The number of controller in the MT2712 */
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#define MT2712_NUM_CONTROLLER 1
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/* The calibration coefficient of sensor */
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#define MT2712_CALIBRATION 165
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@ -176,6 +185,7 @@ enum {
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#define MT7622_NUM_ZONES 1
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#define MT7622_NUM_SENSORS_PER_ZONE 1
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#define MT7622_TS1 0
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#define MT7622_NUM_CONTROLLER 1
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/* The calibration coefficient of sensor */
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#define MT7622_CALIBRATION 165
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@ -201,6 +211,8 @@ struct mtk_thermal_data {
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const int *msr;
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const int *adcpnp;
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const int cali_val;
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const int num_controller;
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const int *controller_offset;
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struct thermal_bank_cfg bank_data[];
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};
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@ -240,6 +252,7 @@ static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
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};
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static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
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static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
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static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
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VTS1, VTS2, VTS3, VTS4, VTSABB
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@ -259,6 +272,7 @@ static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
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};
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static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
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static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
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static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
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VTS1, VTS2, VTS3
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@ -278,6 +292,7 @@ static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
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};
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static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
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static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
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static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
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VTS1, VTS2, VTS3, VTS4
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@ -289,6 +304,7 @@ static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
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static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
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static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
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static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
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static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
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/**
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* The MT8173 thermal controller has four banks. Each bank can read up to
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@ -309,6 +325,8 @@ static const struct mtk_thermal_data mt8173_thermal_data = {
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.num_sensors = MT8173_NUM_SENSORS,
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.vts_index = mt8173_vts_index,
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.cali_val = MT8173_CALIBRATION,
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.num_controller = MT8173_NUM_CONTROLLER,
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.controller_offset = mt8173_tc_offset,
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.bank_data = {
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{
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.num_sensors = 2,
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@ -345,6 +363,8 @@ static const struct mtk_thermal_data mt2701_thermal_data = {
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.num_sensors = MT2701_NUM_SENSORS,
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.vts_index = mt2701_vts_index,
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.cali_val = MT2701_CALIBRATION,
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.num_controller = MT2701_NUM_CONTROLLER,
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.controller_offset = mt2701_tc_offset,
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.bank_data = {
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{
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.num_sensors = 3,
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@ -372,6 +392,8 @@ static const struct mtk_thermal_data mt2712_thermal_data = {
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.num_sensors = MT2712_NUM_SENSORS,
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.vts_index = mt2712_vts_index,
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.cali_val = MT2712_CALIBRATION,
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.num_controller = MT2712_NUM_CONTROLLER,
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.controller_offset = mt2712_tc_offset,
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.bank_data = {
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{
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.num_sensors = 4,
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@ -393,6 +415,8 @@ static const struct mtk_thermal_data mt7622_thermal_data = {
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.num_sensors = MT7622_NUM_SENSORS,
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.vts_index = mt7622_vts_index,
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.cali_val = MT7622_CALIBRATION,
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.num_controller = MT7622_NUM_CONTROLLER,
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.controller_offset = mt7622_tc_offset,
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.bank_data = {
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{
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.num_sensors = 1,
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@ -523,19 +547,23 @@ static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
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};
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static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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u32 apmixed_phys_base, u32 auxadc_phys_base)
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u32 apmixed_phys_base, u32 auxadc_phys_base,
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int ctrl_id)
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{
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struct mtk_thermal_bank *bank = &mt->banks[num];
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const struct mtk_thermal_data *conf = mt->conf;
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int i;
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int offset = mt->conf->controller_offset[ctrl_id];
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void __iomem *controller_base = mt->thermal_base + offset;
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bank->id = num;
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bank->mt = mt;
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mtk_thermal_get_bank(bank);
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/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
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writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
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writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
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/*
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* filt interval is 1 * 46.540us = 46.54us,
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@ -543,21 +571,21 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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*/
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writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
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TEMP_MONCTL2_SENSOR_INTERVAL(429),
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mt->thermal_base + TEMP_MONCTL2);
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controller_base + TEMP_MONCTL2);
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/* poll is set to 10u */
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writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
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mt->thermal_base + TEMP_AHBPOLL);
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controller_base + TEMP_AHBPOLL);
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/* temperature sampling control, 1 sample */
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writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
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writel(0x0, controller_base + TEMP_MSRCTL0);
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/* exceed this polling time, IRQ would be inserted */
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writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
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writel(0xffffffff, controller_base + TEMP_AHBTO);
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/* number of interrupts per event, 1 is enough */
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writel(0x0, mt->thermal_base + TEMP_MONIDET0);
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writel(0x0, mt->thermal_base + TEMP_MONIDET1);
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writel(0x0, controller_base + TEMP_MONIDET0);
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writel(0x0, controller_base + TEMP_MONIDET1);
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/*
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* The MT8173 thermal controller does not have its own ADC. Instead it
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@ -572,44 +600,44 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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* this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
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* automatically by hw
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*/
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writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX);
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writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
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/* AHB address for auxadc mux selection */
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writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
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mt->thermal_base + TEMP_ADCMUXADDR);
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controller_base + TEMP_ADCMUXADDR);
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/* AHB address for pnp sensor mux selection */
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writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
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mt->thermal_base + TEMP_PNPMUXADDR);
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controller_base + TEMP_PNPMUXADDR);
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/* AHB value for auxadc enable */
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writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN);
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writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
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/* AHB address for auxadc enable (channel 0 immediate mode selected) */
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writel(auxadc_phys_base + AUXADC_CON1_SET_V,
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mt->thermal_base + TEMP_ADCENADDR);
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controller_base + TEMP_ADCENADDR);
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/* AHB address for auxadc valid bit */
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writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
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mt->thermal_base + TEMP_ADCVALIDADDR);
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controller_base + TEMP_ADCVALIDADDR);
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/* AHB address for auxadc voltage output */
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writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
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mt->thermal_base + TEMP_ADCVOLTADDR);
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controller_base + TEMP_ADCVOLTADDR);
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/* read valid & voltage are at the same register */
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writel(0x0, mt->thermal_base + TEMP_RDCTRL);
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writel(0x0, controller_base + TEMP_RDCTRL);
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/* indicate where the valid bit is */
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writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
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mt->thermal_base + TEMP_ADCVALIDMASK);
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controller_base + TEMP_ADCVALIDMASK);
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/* no shift */
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writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
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writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
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/* enable auxadc mux write transaction */
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writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
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mt->thermal_base + TEMP_ADCWRITECTRL);
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controller_base + TEMP_ADCWRITECTRL);
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for (i = 0; i < conf->bank_data[num].num_sensors; i++)
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writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
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@ -617,11 +645,11 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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conf->adcpnp[conf->bank_data[num].sensors[i]]);
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writel((1 << conf->bank_data[num].num_sensors) - 1,
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mt->thermal_base + TEMP_MONCTL0);
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controller_base + TEMP_MONCTL0);
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writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
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TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
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mt->thermal_base + TEMP_ADCWRITECTRL);
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controller_base + TEMP_ADCWRITECTRL);
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mtk_thermal_put_bank(bank);
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}
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@ -737,7 +765,7 @@ MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
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static int mtk_thermal_probe(struct platform_device *pdev)
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{
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int ret, i;
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int ret, i, ctrl_id;
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struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
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struct mtk_thermal *mt;
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struct resource *res;
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@ -817,9 +845,10 @@ static int mtk_thermal_probe(struct platform_device *pdev)
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goto err_disable_clk_auxadc;
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}
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for (i = 0; i < mt->conf->num_banks; i++)
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mtk_thermal_init_bank(mt, i, apmixed_phys_base,
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auxadc_phys_base);
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for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
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for (i = 0; i < mt->conf->num_banks; i++)
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mtk_thermal_init_bank(mt, i, apmixed_phys_base,
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auxadc_phys_base, ctrl_id);
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platform_set_drvdata(pdev, mt);
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