Add support for Westmere to i7core_edac driver
This adds new PCI IDs for the Westmere's memory controller devices and modifies the i7core_edac driver to be able to probe both Nehalem and Westmere processors. Signed-off-by: Vernon Mauery <vernux@us.ibm.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -206,6 +206,11 @@ struct pci_id_descr {
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int optional;
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};
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struct pci_id_table {
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struct pci_id_descr *descr;
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int n_devs;
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};
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struct i7core_dev {
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struct list_head list;
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u8 socket;
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@ -262,7 +267,7 @@ static DEFINE_MUTEX(i7core_edac_lock);
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.func = (function), \
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.dev_id = (device_id)
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struct pci_id_descr pci_dev_descr_i7core[] = {
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struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
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/* Memory controller */
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{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
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{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
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@ -321,6 +326,44 @@ struct pci_id_descr pci_dev_descr_lynnfield[] = {
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{ PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
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};
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struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
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/* Memory controller */
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{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
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{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
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/* Exists only for RDIMM */
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{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
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{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
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/* Channel 0 */
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{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
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{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
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{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
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{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
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/* Channel 1 */
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{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
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{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
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{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
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{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
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/* Channel 2 */
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{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
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{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
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{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
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{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
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/* Generic Non-core registers */
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{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
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};
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#define PCI_ID_TABLE_ENTRY(A) { A, ARRAY_SIZE(A) }
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struct pci_id_table pci_dev_table[] = {
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PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
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PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
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PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
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};
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/*
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* pci_device_id table for which devices we are looking for
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*/
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@ -1170,7 +1213,7 @@ static void i7core_put_all_devices(void)
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i7core_put_devices(i7core_dev);
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}
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static void __init i7core_xeon_pci_fixup(int dev_id)
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static void __init i7core_xeon_pci_fixup(struct pci_id_table *table)
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{
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struct pci_dev *pdev = NULL;
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int i;
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@ -1179,10 +1222,13 @@ static void __init i7core_xeon_pci_fixup(int dev_id)
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* aren't announced by acpi. So, we need to use a legacy scan probing
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* to detect them
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*/
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
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if (unlikely(!pdev)) {
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for (i = 0; i < MAX_SOCKET_BUSES; i++)
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pcibios_scan_specific_bus(255-i);
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while (table && table->descr) {
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
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if (unlikely(!pdev)) {
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for (i = 0; i < MAX_SOCKET_BUSES; i++)
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pcibios_scan_specific_bus(255-i);
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}
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table++;
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}
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}
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@ -1213,15 +1259,10 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno,
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
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if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev) {
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if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
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*prev);
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if (!pdev)
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2,
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*prev);
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}
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if (!pdev) {
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if (*prev) {
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@ -1232,6 +1273,9 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno,
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if (dev_descr->optional)
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return 0;
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if (devno == 0)
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return -ENODEV;
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i7core_printk(KERN_ERR,
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"Device not found: dev %02x.%d PCI ID %04x:%04x\n",
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dev_descr->dev, dev_descr->func,
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@ -1307,24 +1351,34 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno,
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return 0;
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}
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static int i7core_get_devices(struct pci_id_descr dev_descr[], unsigned n_devs)
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static int i7core_get_devices(struct pci_id_table *table)
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{
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int i, rc;
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struct pci_dev *pdev = NULL;
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struct pci_id_descr *dev_descr;
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for (i = 0; i < n_devs; i++) {
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pdev = NULL;
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do {
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rc = i7core_get_onedevice(&pdev, i, &dev_descr[i],
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n_devs);
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if (rc < 0) {
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i7core_put_all_devices();
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return -ENODEV;
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}
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} while (pdev);
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while (table && table->descr) {
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dev_descr = table->descr;
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for (i = 0; i < table->n_devs; i++) {
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pdev = NULL;
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do {
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rc = i7core_get_onedevice(&pdev, i, &dev_descr[i],
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table->n_devs);
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if (rc < 0) {
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if (i == 0) {
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i = table->n_devs;
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break;
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}
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i7core_put_all_devices();
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return -ENODEV;
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}
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} while (pdev);
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}
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table++;
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}
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return 0;
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return 0;
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}
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static int mci_bind_devs(struct mem_ctl_info *mci,
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@ -1884,18 +1938,7 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
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/* get the pci devices we want to reserve for our use */
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mutex_lock(&i7core_edac_lock);
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if (pdev->device == PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0) {
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printk(KERN_INFO "i7core_edac: detected a "
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"Lynnfield processor\n");
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rc = i7core_get_devices(pci_dev_descr_lynnfield,
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ARRAY_SIZE(pci_dev_descr_lynnfield));
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} else {
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printk(KERN_INFO "i7core_edac: detected a "
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"Nehalem/Nehalem-EP processor\n");
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rc = i7core_get_devices(pci_dev_descr_i7core,
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ARRAY_SIZE(pci_dev_descr_i7core));
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}
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rc = i7core_get_devices(pci_dev_table);
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if (unlikely(rc < 0))
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goto fail0;
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@ -1994,7 +2037,7 @@ static int __init i7core_init(void)
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/* Ensure that the OPSTATE is set correctly for POLL or NMI */
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opstate_init();
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i7core_xeon_pci_fixup(pci_dev_descr_i7core[0].dev_id);
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i7core_xeon_pci_fixup(pci_dev_table);
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pci_rc = pci_register_driver(&i7core_driver);
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@ -2567,6 +2567,22 @@
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR 0x2ca9
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK 0x2caa
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC 0x2cab
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2 0x2d98
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2 0x2d99
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2 0x2d9a
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2 0x2d9c
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2 0x2da0
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2 0x2da1
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2 0x2da2
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2 0x2da3
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2 0x2da8
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2 0x2da9
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2 0x2daa
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2 0x2dab
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2 0x2db0
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2 0x2db1
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2 0x2db2
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#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2 0x2db3
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#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340
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#define PCI_DEVICE_ID_INTEL_IOAT_TBG4 0x3429
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#define PCI_DEVICE_ID_INTEL_IOAT_TBG5 0x342a
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