iommu/amd: Tidy up DMA ops init
Now that DMA ops are part of the core API via iommu-dma, fold the vestigial remains of the IOMMU_DMA_OPS init state into the IOMMU API phase, and clean up a few other leftovers. This should also close the race window wherein bus_set_iommu() effectively makes the DMA ops state visible before its nominal initialisation - it seems this was previously fairly benign, but since commita250c23f15
("iommu: remove DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE") it can now lead to the strict flush queue policy inadvertently being picked for default domains allocated during that window, with a corresponding unexpected perfomance impact. Reported-by: Jussi Maki <joamaki@gmail.com> Tested-by: Jussi Maki <joamaki@gmail.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Fixes:a250c23f15
("iommu: remove DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE") Link: https://lore.kernel.org/r/665db61e23ff8d54ac5eb391bef520b3a803fcb9.1622727974.git.robin.murphy@arm.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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be227f8e99
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@ -11,8 +11,6 @@
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#include "amd_iommu_types.h"
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extern int amd_iommu_init_dma_ops(void);
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extern int amd_iommu_init_passthrough(void);
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extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
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extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
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extern void amd_iommu_apply_erratum_63(u16 devid);
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@ -231,7 +231,6 @@ enum iommu_init_state {
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IOMMU_ENABLED,
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IOMMU_PCI_INIT,
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IOMMU_INTERRUPTS_EN,
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IOMMU_DMA_OPS,
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IOMMU_INITIALIZED,
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IOMMU_NOT_FOUND,
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IOMMU_INIT_ERROR,
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@ -2895,10 +2894,6 @@ static int __init state_next(void)
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init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
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break;
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case IOMMU_INTERRUPTS_EN:
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ret = amd_iommu_init_dma_ops();
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init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
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break;
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case IOMMU_DMA_OPS:
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init_state = IOMMU_INITIALIZED;
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break;
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case IOMMU_INITIALIZED:
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@ -30,7 +30,6 @@
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#include <linux/msi.h>
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#include <linux/irqdomain.h>
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#include <linux/percpu.h>
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#include <linux/iova.h>
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#include <linux/io-pgtable.h>
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#include <asm/irq_remapping.h>
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#include <asm/io_apic.h>
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@ -1773,13 +1772,22 @@ void amd_iommu_domain_update(struct protection_domain *domain)
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amd_iommu_domain_flush_complete(domain);
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}
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static void __init amd_iommu_init_dma_ops(void)
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{
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swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
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if (amd_iommu_unmap_flush)
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pr_info("IO/TLB flush on unmap enabled\n");
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else
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pr_info("Lazy IO/TLB flushing enabled\n");
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iommu_set_dma_strict(amd_iommu_unmap_flush);
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}
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int __init amd_iommu_init_api(void)
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{
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int ret, err = 0;
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int err = 0;
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ret = iova_cache_get();
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if (ret)
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return ret;
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amd_iommu_init_dma_ops();
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err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
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if (err)
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@ -1796,19 +1804,6 @@ int __init amd_iommu_init_api(void)
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return 0;
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}
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int __init amd_iommu_init_dma_ops(void)
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{
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swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
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if (amd_iommu_unmap_flush)
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pr_info("IO/TLB flush on unmap enabled\n");
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else
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pr_info("Lazy IO/TLB flushing enabled\n");
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iommu_set_dma_strict(amd_iommu_unmap_flush);
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return 0;
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}
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/*****************************************************************************
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*
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* The following functions belong to the exported interface of AMD IOMMU
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