bna: Brocade 1860 IOC PLL, Reg Defs and ASIC Mode Changes
Add logic to set ASIC specfic interface in IOC, HW interface initialization APIs, mode based initialization and MSI-X resource allocation for 1860 with no asic block. Add new h/w specific register definitions and setup registers used by IOC logic. Use normal kernel declaration style, c99 initializers and const for mailbox structures. Remove unneeded parentheses. Signed-off-by: Gurunatha Karaje <gkaraje@brocade.com> Signed-off-by: Rasesh Mody <rmody@brocade.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Родитель
3869f80605
Коммит
be3a84d136
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@ -1981,7 +1981,13 @@ bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
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BUG_ON(1);
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}
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bfa_nw_ioc_set_ct_hwif(ioc);
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/**
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* Set asic specific interfaces.
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*/
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if (ioc->asic_gen == BFI_ASIC_GEN_CT)
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bfa_nw_ioc_set_ct_hwif(ioc);
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else
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bfa_nw_ioc_set_ct2_hwif(ioc);
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bfa_ioc_map_port(ioc);
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bfa_ioc_reg_init(ioc);
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@ -72,6 +72,7 @@ struct bfa_ioc_regs {
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void __iomem *hfn_mbox;
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void __iomem *lpu_mbox_cmd;
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void __iomem *lpu_mbox;
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void __iomem *lpu_read_stat;
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void __iomem *pss_ctl_reg;
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void __iomem *pss_err_status_reg;
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void __iomem *app_pll_fast_ctl_reg;
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@ -287,6 +288,7 @@ void bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
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} while (0)
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void bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc);
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void bfa_nw_ioc_set_ct2_hwif(struct bfa_ioc *ioc);
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void bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa,
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struct bfa_ioc_cbfn *cbfn);
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@ -37,7 +37,9 @@
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static bool bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);
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static void bfa_ioc_ct2_reg_init(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);
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static void bfa_ioc_ct2_map_port(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);
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static void bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
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@ -48,6 +50,9 @@ static void bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc);
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static bool bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc);
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static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb,
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enum bfi_asic_mode asic_mode);
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static enum bfa_status bfa_ioc_ct2_pll_init(void __iomem *rb,
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enum bfi_asic_mode asic_mode);
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static bool bfa_ioc_ct2_lpu_read_stat(struct bfa_ioc *ioc);
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static const struct bfa_ioc_hwif nw_hwif_ct = {
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.ioc_pll_init = bfa_ioc_ct_pll_init,
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@ -65,6 +70,23 @@ static const struct bfa_ioc_hwif nw_hwif_ct = {
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.ioc_sync_complete = bfa_ioc_ct_sync_complete,
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};
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static const struct bfa_ioc_hwif nw_hwif_ct2 = {
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.ioc_pll_init = bfa_ioc_ct2_pll_init,
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.ioc_firmware_lock = bfa_ioc_ct_firmware_lock,
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.ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock,
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.ioc_reg_init = bfa_ioc_ct2_reg_init,
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.ioc_map_port = bfa_ioc_ct2_map_port,
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.ioc_lpu_read_stat = bfa_ioc_ct2_lpu_read_stat,
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.ioc_isr_mode_set = NULL,
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.ioc_notify_fail = bfa_ioc_ct_notify_fail,
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.ioc_ownership_reset = bfa_ioc_ct_ownership_reset,
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.ioc_sync_start = bfa_ioc_ct_sync_start,
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.ioc_sync_join = bfa_ioc_ct_sync_join,
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.ioc_sync_leave = bfa_ioc_ct_sync_leave,
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.ioc_sync_ack = bfa_ioc_ct_sync_ack,
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.ioc_sync_complete = bfa_ioc_ct_sync_complete,
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};
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/**
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* Called from bfa_ioc_attach() to map asic specific calls.
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*/
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@ -74,6 +96,12 @@ bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc)
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ioc->ioc_hwif = &nw_hwif_ct;
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}
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void
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bfa_nw_ioc_set_ct2_hwif(struct bfa_ioc *ioc)
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{
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ioc->ioc_hwif = &nw_hwif_ct2;
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}
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/**
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* Return true if firmware of current driver matches the running firmware.
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*/
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@ -170,7 +198,11 @@ bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc)
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/**
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* Host to LPU mailbox message addresses
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*/
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static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } ct_fnreg[] = {
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static const struct {
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u32 hfn_mbox;
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u32 lpu_mbox;
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u32 hfn_pgn;
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} ct_fnreg[] = {
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{ HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
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{ HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
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{ HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
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@ -180,7 +212,10 @@ static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } ct_fnreg[] = {
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/**
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* Host <-> LPU mailbox command/status registers - port 0
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*/
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static struct { u32 hfn, lpu; } ct_p0reg[] = {
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static const struct {
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u32 hfn;
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u32 lpu;
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} ct_p0reg[] = {
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{ HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
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{ HOSTFN1_LPU0_CMD_STAT, LPU0_HOSTFN1_CMD_STAT },
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{ HOSTFN2_LPU0_CMD_STAT, LPU0_HOSTFN2_CMD_STAT },
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@ -190,13 +225,32 @@ static struct { u32 hfn, lpu; } ct_p0reg[] = {
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/**
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* Host <-> LPU mailbox command/status registers - port 1
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*/
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static struct { u32 hfn, lpu; } ct_p1reg[] = {
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static const struct {
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u32 hfn;
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u32 lpu;
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} ct_p1reg[] = {
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{ HOSTFN0_LPU1_CMD_STAT, LPU1_HOSTFN0_CMD_STAT },
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{ HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT },
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{ HOSTFN2_LPU1_CMD_STAT, LPU1_HOSTFN2_CMD_STAT },
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{ HOSTFN3_LPU1_CMD_STAT, LPU1_HOSTFN3_CMD_STAT }
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};
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static const struct {
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u32 hfn_mbox;
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u32 lpu_mbox;
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u32 hfn_pgn;
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u32 hfn;
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u32 lpu;
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u32 lpu_read;
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} ct2_reg[] = {
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{ CT2_HOSTFN_LPU0_MBOX0, CT2_LPU0_HOSTFN_MBOX0, CT2_HOSTFN_PAGE_NUM,
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CT2_HOSTFN_LPU0_CMD_STAT, CT2_LPU0_HOSTFN_CMD_STAT,
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CT2_HOSTFN_LPU0_READ_STAT},
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{ CT2_HOSTFN_LPU1_MBOX0, CT2_LPU1_HOSTFN_MBOX0, CT2_HOSTFN_PAGE_NUM,
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CT2_HOSTFN_LPU1_CMD_STAT, CT2_LPU1_HOSTFN_CMD_STAT,
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CT2_HOSTFN_LPU1_READ_STAT},
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};
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static void
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bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
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{
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@ -218,8 +272,8 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
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ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
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ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
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} else {
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ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
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ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
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ioc->ioc_regs.heartbeat = rb + BFA_IOC1_HBEAT_REG;
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ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC1_STATE_REG;
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ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
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ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn;
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ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu;
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@ -230,24 +284,24 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
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/*
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* PSS control registers
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*/
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ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
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ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
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ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
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ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
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ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG;
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ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG;
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ioc->ioc_regs.app_pll_fast_ctl_reg = rb + APP_PLL_LCLK_CTL_REG;
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ioc->ioc_regs.app_pll_slow_ctl_reg = rb + APP_PLL_SCLK_CTL_REG;
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/*
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* IOC semaphore registers and serialization
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*/
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ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
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ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
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ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
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ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
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ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);
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ioc->ioc_regs.ioc_sem_reg = rb + HOST_SEM0_REG;
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ioc->ioc_regs.ioc_usage_sem_reg = rb + HOST_SEM1_REG;
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ioc->ioc_regs.ioc_init_sem_reg = rb + HOST_SEM2_REG;
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ioc->ioc_regs.ioc_usage_reg = rb + BFA_FW_USE_COUNT;
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ioc->ioc_regs.ioc_fail_sync = rb + BFA_IOC_FAIL_SYNC;
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/**
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* sram memory access
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*/
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ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
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ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START;
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ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
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/*
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@ -256,6 +310,64 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
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ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
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}
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static void
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bfa_ioc_ct2_reg_init(struct bfa_ioc *ioc)
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{
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void __iomem *rb;
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int port = bfa_ioc_portid(ioc);
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rb = bfa_ioc_bar0(ioc);
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ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox;
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ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox;
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ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn;
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ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn;
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ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu;
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ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read;
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if (port == 0) {
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ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG;
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ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;
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ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG;
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ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
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ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
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} else {
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ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC1_HBEAT_REG;
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ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG;
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ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;
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ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
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ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
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}
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/*
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* PSS control registers
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*/
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ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG;
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ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG;
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ioc->ioc_regs.app_pll_fast_ctl_reg = rb + CT2_APP_PLL_LCLK_CTL_REG;
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ioc->ioc_regs.app_pll_slow_ctl_reg = rb + CT2_APP_PLL_SCLK_CTL_REG;
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/*
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* IOC semaphore registers and serialization
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*/
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ioc->ioc_regs.ioc_sem_reg = rb + CT2_HOST_SEM0_REG;
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ioc->ioc_regs.ioc_usage_sem_reg = rb + CT2_HOST_SEM1_REG;
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ioc->ioc_regs.ioc_init_sem_reg = rb + CT2_HOST_SEM2_REG;
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ioc->ioc_regs.ioc_usage_reg = rb + CT2_BFA_FW_USE_COUNT;
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ioc->ioc_regs.ioc_fail_sync = rb + CT2_BFA_IOC_FAIL_SYNC;
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/**
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* sram memory access
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*/
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ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START;
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ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
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/*
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* err set reg : for notification of hb failure in fcmode
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*/
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ioc->ioc_regs.err_set = rb + ERR_SET_REG;
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}
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/**
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* Initialize IOC to port mapping.
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*/
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@ -276,6 +388,16 @@ bfa_ioc_ct_map_port(struct bfa_ioc *ioc)
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}
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static void
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bfa_ioc_ct2_map_port(struct bfa_ioc *ioc)
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{
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void __iomem *rb = ioc->pcidev.pci_bar_kva;
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u32 r32;
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r32 = readl(rb + CT2_HOSTFN_PERSONALITY0);
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ioc->port_id = ((r32 & __FC_LL_PORT_MAP__MK) >> __FC_LL_PORT_MAP__SH);
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}
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/**
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* Set interrupt mode for a function: INTX or MSIX
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*/
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@ -307,6 +429,50 @@ bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix)
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writel(r32, rb + FNC_PERS_REG);
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}
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static bool
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bfa_ioc_ct2_lpu_read_stat(struct bfa_ioc *ioc)
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{
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u32 r32;
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r32 = readl(ioc->ioc_regs.lpu_read_stat);
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if (r32) {
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writel(1, ioc->ioc_regs.lpu_read_stat);
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return true;
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}
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return false;
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}
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/**
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* MSI-X resource allocation for 1860 with no asic block
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*/
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#define HOSTFN_MSIX_DEFAULT 64
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#define HOSTFN_MSIX_VT_INDEX_MBOX_ERR 0x30138
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#define HOSTFN_MSIX_VT_OFST_NUMVT 0x3013c
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#define __MSIX_VT_NUMVT__MK 0x003ff800
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#define __MSIX_VT_NUMVT__SH 11
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#define __MSIX_VT_NUMVT_(_v) ((_v) << __MSIX_VT_NUMVT__SH)
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#define __MSIX_VT_OFST_ 0x000007ff
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void
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bfa_ioc_ct2_poweron(struct bfa_ioc *ioc)
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{
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void __iomem *rb = ioc->pcidev.pci_bar_kva;
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u32 r32;
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r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT);
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if (r32 & __MSIX_VT_NUMVT__MK) {
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writel(r32 & __MSIX_VT_OFST_,
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rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);
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return;
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}
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writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) |
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HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc),
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rb + HOSTFN_MSIX_VT_OFST_NUMVT);
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writel(HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc),
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rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);
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}
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/**
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* Cleanup hw semaphore and usecnt registers
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*/
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@ -499,3 +665,207 @@ bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
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writel(0, (rb + MBIST_CTL_REG));
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return BFA_STATUS_OK;
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}
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static void
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bfa_ioc_ct2_sclk_init(void __iomem *rb)
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{
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u32 r32;
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/*
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* put s_clk PLL and PLL FSM in reset
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*/
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r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
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r32 &= ~(__APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN);
|
||||
r32 |= (__APP_PLL_SCLK_ENARST | __APP_PLL_SCLK_BYPASS |
|
||||
__APP_PLL_SCLK_LOGIC_SOFT_RESET);
|
||||
writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* Ignore mode and program for the max clock (which is FC16)
|
||||
* Firmware/NFC will do the PLL init appropiately
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2);
|
||||
writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* while doing PLL init dont clock gate ethernet subsystem
|
||||
*/
|
||||
r32 = readl((rb + CT2_CHIP_MISC_PRG));
|
||||
writel((r32 | __ETH_CLK_ENABLE_PORT0),
|
||||
(rb + CT2_CHIP_MISC_PRG));
|
||||
|
||||
r32 = readl((rb + CT2_PCIE_MISC_REG));
|
||||
writel((r32 | __ETH_CLK_ENABLE_PORT1),
|
||||
(rb + CT2_PCIE_MISC_REG));
|
||||
|
||||
/*
|
||||
* set sclk value
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
r32 &= (__P_SCLK_PLL_LOCK | __APP_PLL_SCLK_REFCLK_SEL |
|
||||
__APP_PLL_SCLK_CLK_DIV2);
|
||||
writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* poll for s_clk lock or delay 1ms
|
||||
*/
|
||||
udelay(1000);
|
||||
|
||||
/*
|
||||
* Dont do clock gating for ethernet subsystem, firmware/NFC will
|
||||
* do this appropriately
|
||||
*/
|
||||
}
|
||||
|
||||
static void
|
||||
bfa_ioc_ct2_lclk_init(void __iomem *rb)
|
||||
{
|
||||
u32 r32;
|
||||
|
||||
/*
|
||||
* put l_clk PLL and PLL FSM in reset
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
r32 &= ~(__APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN);
|
||||
r32 |= (__APP_PLL_LCLK_ENARST | __APP_PLL_LCLK_BYPASS |
|
||||
__APP_PLL_LCLK_LOGIC_SOFT_RESET);
|
||||
writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* set LPU speed (set for FC16 which will work for other modes)
|
||||
*/
|
||||
r32 = readl((rb + CT2_CHIP_MISC_PRG));
|
||||
writel(r32, (rb + CT2_CHIP_MISC_PRG));
|
||||
|
||||
/*
|
||||
* set LPU half speed (set for FC16 which will work for other modes)
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* set lclk for mode (set for FC16)
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
r32 &= (__P_LCLK_PLL_LOCK | __APP_LPUCLK_HALFSPEED);
|
||||
r32 |= 0x20c1731b;
|
||||
writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* poll for s_clk lock or delay 1ms
|
||||
*/
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
static void
|
||||
bfa_ioc_ct2_mem_init(void __iomem *rb)
|
||||
{
|
||||
u32 r32;
|
||||
|
||||
r32 = readl((rb + PSS_CTL_REG));
|
||||
r32 &= ~__PSS_LMEM_RESET;
|
||||
writel(r32, (rb + PSS_CTL_REG));
|
||||
udelay(1000);
|
||||
|
||||
writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));
|
||||
udelay(1000);
|
||||
writel(0, (rb + CT2_MBIST_CTL_REG));
|
||||
}
|
||||
|
||||
static void
|
||||
bfa_ioc_ct2_mac_reset(void __iomem *rb)
|
||||
{
|
||||
volatile u32 r32;
|
||||
|
||||
bfa_ioc_ct2_sclk_init(rb);
|
||||
bfa_ioc_ct2_lclk_init(rb);
|
||||
|
||||
/*
|
||||
* release soft reset on s_clk & l_clk
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
writel((r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET),
|
||||
(rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* release soft reset on s_clk & l_clk
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
writel((r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET),
|
||||
(rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
|
||||
/* put port0, port1 MAC & AHB in reset */
|
||||
writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),
|
||||
(rb + CT2_CSI_MAC_CONTROL_REG(0)));
|
||||
writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),
|
||||
(rb + CT2_CSI_MAC_CONTROL_REG(1)));
|
||||
}
|
||||
|
||||
#define CT2_NFC_MAX_DELAY 1000
|
||||
static enum bfa_status
|
||||
bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
|
||||
{
|
||||
volatile u32 wgn, r32;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Initialize PLL if not already done by NFC
|
||||
*/
|
||||
wgn = readl(rb + CT2_WGN_STATUS);
|
||||
if (!(wgn & __GLBL_PF_VF_CFG_RDY)) {
|
||||
writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG));
|
||||
for (i = 0; i < CT2_NFC_MAX_DELAY; i++) {
|
||||
r32 = readl(rb + CT2_NFC_CSR_SET_REG);
|
||||
if (r32 & __NFC_CONTROLLER_HALTED)
|
||||
break;
|
||||
udelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Mask the interrupts and clear any
|
||||
* pending interrupts left by BIOS/EFI
|
||||
*/
|
||||
|
||||
writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));
|
||||
writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));
|
||||
|
||||
r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
|
||||
if (r32 == 1) {
|
||||
writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));
|
||||
readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
|
||||
}
|
||||
r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
|
||||
if (r32 == 1) {
|
||||
writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));
|
||||
readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
|
||||
}
|
||||
|
||||
bfa_ioc_ct2_mac_reset(rb);
|
||||
bfa_ioc_ct2_sclk_init(rb);
|
||||
bfa_ioc_ct2_lclk_init(rb);
|
||||
|
||||
/*
|
||||
* release soft reset on s_clk & l_clk
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
writel((r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET),
|
||||
(rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* Announce flash device presence, if flash was corrupted.
|
||||
*/
|
||||
if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {
|
||||
r32 = readl((rb + PSS_GPIO_OUT_REG));
|
||||
writel((r32 & ~1), (rb + PSS_GPIO_OUT_REG));
|
||||
r32 = readl((rb + PSS_GPIO_OE_REG));
|
||||
writel((r32 | 1), (rb + PSS_GPIO_OE_REG));
|
||||
}
|
||||
|
||||
bfa_ioc_ct2_mem_init(rb);
|
||||
|
||||
writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));
|
||||
writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));
|
||||
return BFA_STATUS_OK;
|
||||
}
|
||||
|
|
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