i2c: mediatek: Add i2c ac-timing adjust support
This patch adds a algorithm to calculate some ac-timing parameters which can fully meet I2C Spec. Signed-off-by: Qii Wang <qii.wang@mediatek.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Qii Wang
Wolfram Sang
Родитель
7943f1d178
Коммит
be5ce0e97c
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@ -40,12 +40,11 @@
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#define I2C_SOFT_RST 0x0001
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#define I2C_FIFO_ADDR_CLR 0x0001
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#define I2C_DELAY_LEN 0x0002
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#define I2C_ST_START_CON 0x8001
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#define I2C_FS_START_CON 0x1800
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#define I2C_TIME_CLR_VALUE 0x0000
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#define I2C_TIME_DEFAULT_VALUE 0x0003
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#define I2C_WRRD_TRANAC_VALUE 0x0002
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#define I2C_RD_TRANAC_VALUE 0x0001
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#define I2C_SCL_MIS_COMP_VALUE 0x0000
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#define I2C_DMA_CON_TX 0x0000
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#define I2C_DMA_CON_RX 0x0001
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@ -55,10 +54,13 @@
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#define I2C_DMA_HARD_RST 0x0002
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#define I2C_DMA_4G_MODE 0x0001
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#define I2C_DEFAULT_CLK_DIV 5
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#define MAX_SAMPLE_CNT_DIV 8
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#define MAX_STEP_CNT_DIV 64
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#define MAX_CLOCK_DIV 256
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#define MAX_HS_STEP_CNT_DIV 8
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#define I2C_STANDARD_MODE_BUFFER (1000 / 2)
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#define I2C_FAST_MODE_BUFFER (300 / 2)
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#define I2C_FAST_MODE_PLUS_BUFFER (20 / 2)
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#define I2C_CONTROL_RS (0x1 << 1)
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#define I2C_CONTROL_DMA_EN (0x1 << 2)
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@ -123,6 +125,12 @@ enum I2C_REGS_OFFSET {
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OFFSET_TRANSFER_LEN_AUX,
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OFFSET_CLOCK_DIV,
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OFFSET_LTIMING,
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OFFSET_SCL_HIGH_LOW_RATIO,
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OFFSET_HS_SCL_HIGH_LOW_RATIO,
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OFFSET_SCL_MIS_COMP_POINT,
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OFFSET_STA_STO_AC_TIMING,
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OFFSET_HS_STA_STO_AC_TIMING,
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OFFSET_SDA_TIMING,
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};
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static const u16 mt_i2c_regs_v1[] = {
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@ -150,6 +158,12 @@ static const u16 mt_i2c_regs_v1[] = {
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[OFFSET_DEBUGCTRL] = 0x68,
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[OFFSET_TRANSFER_LEN_AUX] = 0x6c,
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[OFFSET_CLOCK_DIV] = 0x70,
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[OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
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[OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
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[OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
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[OFFSET_STA_STO_AC_TIMING] = 0x80,
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[OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
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[OFFSET_SDA_TIMING] = 0x88,
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};
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static const u16 mt_i2c_regs_v2[] = {
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@ -168,9 +182,11 @@ static const u16 mt_i2c_regs_v2[] = {
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[OFFSET_HS] = 0x30,
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[OFFSET_IO_CONFIG] = 0x34,
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[OFFSET_FIFO_ADDR_CLR] = 0x38,
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[OFFSET_SDA_TIMING] = 0x3c,
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[OFFSET_TRANSFER_LEN_AUX] = 0x44,
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[OFFSET_CLOCK_DIV] = 0x48,
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[OFFSET_SOFTRESET] = 0x50,
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[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
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[OFFSET_DEBUGSTAT] = 0xe0,
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[OFFSET_DEBUGCTRL] = 0xe8,
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[OFFSET_FIFO_STAT] = 0xf4,
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@ -191,6 +207,19 @@ struct mtk_i2c_compatible {
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unsigned char ltiming_adjust: 1;
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};
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struct mtk_i2c_ac_timing {
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u16 htiming;
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u16 ltiming;
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u16 hs;
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u16 ext;
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u16 inter_clk_div;
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u16 scl_hl_ratio;
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u16 hs_scl_hl_ratio;
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u16 sta_stop;
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u16 hs_sta_stop;
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u16 sda_timing;
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};
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struct mtk_i2c {
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struct i2c_adapter adap; /* i2c host adapter */
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struct device *dev;
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@ -215,9 +244,46 @@ struct mtk_i2c {
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u16 ltiming_reg;
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unsigned char auto_restart;
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bool ignore_restart_irq;
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struct mtk_i2c_ac_timing ac_timing;
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const struct mtk_i2c_compatible *dev_comp;
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};
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/**
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* struct i2c_spec_values:
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* min_low_ns: min LOW period of the SCL clock
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* min_su_sta_ns: min set-up time for a repeated START condition
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* max_hd_dat_ns: max data hold time
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* min_su_dat_ns: min data set-up time
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*/
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struct i2c_spec_values {
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unsigned int min_low_ns;
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unsigned int min_high_ns;
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unsigned int min_su_sta_ns;
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unsigned int max_hd_dat_ns;
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unsigned int min_su_dat_ns;
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};
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static const struct i2c_spec_values standard_mode_spec = {
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.min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
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.min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
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.max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
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.min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
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};
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static const struct i2c_spec_values fast_mode_spec = {
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.min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
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.min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
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.max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
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.min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
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};
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static const struct i2c_spec_values fast_mode_plus_spec = {
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.min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
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.min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
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.max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
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.min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
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};
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static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
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.flags = I2C_AQ_COMB_WRITE_THEN_READ,
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.max_num_msgs = 1,
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@ -397,14 +463,38 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
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if (i2c->dev_comp->dcm)
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mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
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if (i2c->dev_comp->timing_adjust)
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mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
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mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
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mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
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if (i2c->dev_comp->ltiming_adjust)
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mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
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if (i2c->dev_comp->timing_adjust) {
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mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF);
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mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
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OFFSET_CLOCK_DIV);
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mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
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OFFSET_SCL_MIS_COMP_POINT);
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mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
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OFFSET_SDA_TIMING);
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if (i2c->dev_comp->ltiming_adjust) {
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mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
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OFFSET_TIMING);
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mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
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mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
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OFFSET_LTIMING);
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} else {
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mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
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OFFSET_SCL_HIGH_LOW_RATIO);
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mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
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OFFSET_HS_SCL_HIGH_LOW_RATIO);
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mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
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OFFSET_STA_STO_AC_TIMING);
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mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
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OFFSET_HS_STA_STO_AC_TIMING);
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}
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}
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/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
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if (i2c->have_pmic)
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mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
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@ -422,6 +512,126 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
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writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
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}
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static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
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{
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if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
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return &standard_mode_spec;
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else if (speed <= I2C_MAX_FAST_MODE_FREQ)
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return &fast_mode_spec;
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else
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return &fast_mode_plus_spec;
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}
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static int mtk_i2c_max_step_cnt(unsigned int target_speed)
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{
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if (target_speed > I2C_MAX_FAST_MODE_FREQ)
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return MAX_HS_STEP_CNT_DIV;
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else
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return MAX_STEP_CNT_DIV;
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}
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/*
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* Check and Calculate i2c ac-timing
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*
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* Hardware design:
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* sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
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* xxx_cnt_div = spec->min_xxx_ns / sample_ns
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*
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* Sample_ns is rounded down for xxx_cnt_div would be greater
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* than the smallest spec.
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* The sda_timing is chosen as the middle value between
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* the largest and smallest.
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*/
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static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
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unsigned int clk_src,
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unsigned int check_speed,
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unsigned int step_cnt,
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unsigned int sample_cnt)
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{
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const struct i2c_spec_values *spec;
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unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
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unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
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unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
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clk_src);
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if (!i2c->dev_comp->timing_adjust)
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return 0;
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if (i2c->dev_comp->ltiming_adjust)
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max_sta_cnt = 0x100;
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spec = mtk_i2c_get_spec(check_speed);
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if (i2c->dev_comp->ltiming_adjust)
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clk_ns = 1000000000 / clk_src;
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else
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clk_ns = sample_ns / 2;
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su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
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if (su_sta_cnt > max_sta_cnt)
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return -1;
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low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
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max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
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if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
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if (low_cnt > step_cnt) {
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high_cnt = 2 * step_cnt - low_cnt;
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} else {
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high_cnt = step_cnt;
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low_cnt = step_cnt;
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}
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} else {
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return -2;
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}
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sda_max = spec->max_hd_dat_ns / sample_ns;
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if (sda_max > low_cnt)
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sda_max = 0;
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sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
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if (sda_min < low_cnt)
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sda_min = 0;
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if (sda_min > sda_max)
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return -3;
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if (check_speed > I2C_MAX_FAST_MODE_FREQ) {
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if (i2c->dev_comp->ltiming_adjust) {
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i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
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(sample_cnt << 12) | (high_cnt << 8);
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i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
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i2c->ac_timing.ltiming |= (sample_cnt << 12) |
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(low_cnt << 9);
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i2c->ac_timing.ext &= ~GENMASK(7, 1);
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i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
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} else {
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i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
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(high_cnt << 6) | low_cnt;
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i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
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su_sta_cnt;
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}
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i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
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i2c->ac_timing.sda_timing |= (1 << 12) |
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((sda_max + sda_min) / 2) << 6;
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} else {
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if (i2c->dev_comp->ltiming_adjust) {
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i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
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i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
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i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
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} else {
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i2c->ac_timing.scl_hl_ratio = (1 << 12) |
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(high_cnt << 6) | low_cnt;
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i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
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su_sta_cnt;
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}
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i2c->ac_timing.sda_timing = (1 << 12) |
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(sda_max + sda_min) / 2;
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}
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return 0;
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}
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/*
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* Calculate i2c port speed
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*
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@ -446,15 +656,12 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
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unsigned int opt_div;
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unsigned int best_mul;
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unsigned int cnt_mul;
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int ret = -EINVAL;
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if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
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target_speed = I2C_MAX_FAST_MODE_PLUS_FREQ;
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if (target_speed > I2C_MAX_FAST_MODE_FREQ)
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max_step_cnt = MAX_HS_STEP_CNT_DIV;
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else
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max_step_cnt = MAX_STEP_CNT_DIV;
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max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
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base_step_cnt = max_step_cnt;
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/* Find the best combination */
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opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
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@ -473,6 +680,11 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
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continue;
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if (cnt_mul < best_mul) {
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ret = mtk_i2c_check_ac_timing(i2c, clk_src,
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target_speed, step_cnt - 1, sample_cnt - 1);
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if (ret)
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continue;
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best_mul = cnt_mul;
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base_sample_cnt = sample_cnt;
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base_step_cnt = step_cnt;
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@ -481,6 +693,9 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
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}
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}
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if (ret)
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return -EINVAL;
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sample_cnt = base_sample_cnt;
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step_cnt = base_step_cnt;
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@ -506,47 +721,68 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
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unsigned int l_step_cnt;
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unsigned int l_sample_cnt;
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unsigned int target_speed;
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unsigned int clk_div;
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unsigned int max_clk_div;
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int ret;
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clk_src = parent_clk / i2c->clk_src_div;
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target_speed = i2c->speed_hz;
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parent_clk /= i2c->clk_src_div;
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if (target_speed > I2C_MAX_FAST_MODE_FREQ) {
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/* Set master code speed register */
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ret = mtk_i2c_calculate_speed(i2c, clk_src, I2C_MAX_FAST_MODE_FREQ,
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&l_step_cnt, &l_sample_cnt);
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if (ret < 0)
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return ret;
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if (i2c->dev_comp->timing_adjust)
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max_clk_div = MAX_CLOCK_DIV;
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else
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max_clk_div = 1;
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i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
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for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
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clk_src = parent_clk / clk_div;
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/* Set the high speed mode register */
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ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
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&step_cnt, &sample_cnt);
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if (ret < 0)
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return ret;
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if (target_speed > I2C_MAX_FAST_MODE_FREQ) {
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/* Set master code speed register */
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ret = mtk_i2c_calculate_speed(i2c, clk_src,
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I2C_MAX_FAST_MODE_FREQ,
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&l_step_cnt,
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&l_sample_cnt);
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if (ret < 0)
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continue;
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i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
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(sample_cnt << 12) | (step_cnt << 8);
|
||||
i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
|
||||
|
||||
if (i2c->dev_comp->ltiming_adjust)
|
||||
i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
|
||||
(sample_cnt << 12) | (step_cnt << 9);
|
||||
} else {
|
||||
ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
|
||||
&step_cnt, &sample_cnt);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
/* Set the high speed mode register */
|
||||
ret = mtk_i2c_calculate_speed(i2c, clk_src,
|
||||
target_speed, &step_cnt,
|
||||
&sample_cnt);
|
||||
if (ret < 0)
|
||||
continue;
|
||||
|
||||
i2c->timing_reg = (sample_cnt << 8) | step_cnt;
|
||||
i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
|
||||
(sample_cnt << 12) | (step_cnt << 8);
|
||||
|
||||
/* Disable the high speed transaction */
|
||||
i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
|
||||
if (i2c->dev_comp->ltiming_adjust)
|
||||
i2c->ltiming_reg =
|
||||
(l_sample_cnt << 6) | l_step_cnt |
|
||||
(sample_cnt << 12) | (step_cnt << 9);
|
||||
} else {
|
||||
ret = mtk_i2c_calculate_speed(i2c, clk_src,
|
||||
target_speed, &l_step_cnt,
|
||||
&l_sample_cnt);
|
||||
if (ret < 0)
|
||||
continue;
|
||||
|
||||
if (i2c->dev_comp->ltiming_adjust)
|
||||
i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
|
||||
i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
|
||||
|
||||
/* Disable the high speed transaction */
|
||||
i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
|
||||
|
||||
if (i2c->dev_comp->ltiming_adjust)
|
||||
i2c->ltiming_reg =
|
||||
(l_sample_cnt << 6) | l_step_cnt;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
i2c->ac_timing.inter_clk_div = clk_div - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -586,12 +822,6 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
|
|||
|
||||
mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
|
||||
|
||||
/* set start condition */
|
||||
if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
|
||||
mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
|
||||
else
|
||||
mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);
|
||||
|
||||
addr_reg = i2c_8bit_addr_from_msg(msgs);
|
||||
mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
|
||||
|
||||
|
|
@ -948,9 +1178,6 @@ static int mtk_i2c_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
if (i2c->dev_comp->timing_adjust)
|
||||
i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV;
|
||||
|
||||
if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
|||
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