drm/mediatek: dpi: Add output bus formats to driver data
For each SoC, dpi support different output bus formats, so add these information into driver data. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
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@ -123,6 +123,8 @@ struct mtk_dpi_conf {
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u32 reg_h_fre_con;
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u32 max_clock_khz;
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bool edge_sel_en;
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const u32 *output_fmts;
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u32 num_output_fmts;
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};
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static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
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@ -702,10 +704,21 @@ static unsigned int mt8183_calculate_factor(int clock)
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return 2;
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}
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static const u32 mt8173_output_fmts[] = {
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MEDIA_BUS_FMT_RGB888_1X24,
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};
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static const u32 mt8183_output_fmts[] = {
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MEDIA_BUS_FMT_RGB888_2X12_LE,
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MEDIA_BUS_FMT_RGB888_2X12_BE,
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};
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static const struct mtk_dpi_conf mt8173_conf = {
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.cal_factor = mt8173_calculate_factor,
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.reg_h_fre_con = 0xe0,
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.max_clock_khz = 300000,
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.output_fmts = mt8173_output_fmts,
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.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
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};
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static const struct mtk_dpi_conf mt2701_conf = {
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@ -713,18 +726,24 @@ static const struct mtk_dpi_conf mt2701_conf = {
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.reg_h_fre_con = 0xb0,
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.edge_sel_en = true,
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.max_clock_khz = 150000,
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.output_fmts = mt8173_output_fmts,
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.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
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};
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static const struct mtk_dpi_conf mt8183_conf = {
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.cal_factor = mt8183_calculate_factor,
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.reg_h_fre_con = 0xe0,
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.max_clock_khz = 100000,
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.output_fmts = mt8183_output_fmts,
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.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
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};
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static const struct mtk_dpi_conf mt8192_conf = {
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.cal_factor = mt8183_calculate_factor,
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.reg_h_fre_con = 0xe0,
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.max_clock_khz = 150000,
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.output_fmts = mt8173_output_fmts,
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.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
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};
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static int mtk_dpi_probe(struct platform_device *pdev)
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