ARM: integrator: move AP timer to clocksource
This moves the timer/clocksource implementation for the Integrator/AP down to drivers/clocksource and augments the driver a little to use CLOCKSOURCE_OF_DECLARE(). Remove the static mapping of the timer blocks while we're at it. Tested on the Integrator/AP. Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
Родитель
9713497b6c
Коммит
beb5818bd0
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@ -27,13 +27,9 @@
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#include <linux/syscore_ops.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/kmi.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/mtd/physmap.h>
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#include <linux/clk.h>
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#include <linux/platform_data/clk-integrator.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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@ -41,8 +37,6 @@
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#include <linux/stat.h>
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#include <linux/sys_soc.h>
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#include <linux/termios.h>
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#include <linux/sched_clock.h>
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#include <linux/clk-provider.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/setup.h>
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@ -89,11 +83,6 @@ static void __iomem *ebi_base;
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static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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@ -257,188 +246,10 @@ struct amba_pl010_data ap_uart_data = {
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.set_mctrl = integrator_uart_set_mctrl,
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};
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
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#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
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#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
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static unsigned long timer_reload;
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static u64 notrace integrator_read_sched_clock(void)
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{
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return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
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}
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static void integrator_clocksource_init(unsigned long inrate,
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void __iomem *base)
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{
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u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
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unsigned long rate = inrate;
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if (rate >= 1500000) {
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rate /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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writel(0xffff, base + TIMER_LOAD);
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writel(ctrl, base + TIMER_CTRL);
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clocksource_mmio_init(base + TIMER_VALUE, "timer2",
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rate, 200, 16, clocksource_mmio_readl_down);
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sched_clock_register(integrator_read_sched_clock, 16, rate);
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}
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static void __iomem * clkevt_base;
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
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{
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u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
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/* Disable timer */
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writel(ctrl, clkevt_base + TIMER_CTRL);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* Enable the timer and start the periodic tick */
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writel(timer_reload, clkevt_base + TIMER_LOAD);
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ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Leave the timer disabled, .set_next_event will enable it */
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ctrl &= ~TIMER_CTRL_PERIODIC;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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default:
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/* Just leave in disabled state */
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break;
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}
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}
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static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
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{
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unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
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writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device integrator_clockevent = {
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.name = "timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = clkevt_set_mode,
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.set_next_event = clkevt_set_next_event,
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.rating = 300,
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};
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static struct irqaction integrator_timer_irq = {
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.name = "timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = integrator_timer_interrupt,
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.dev_id = &integrator_clockevent,
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};
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static void integrator_clockevent_init(unsigned long inrate,
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void __iomem *base, int irq)
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{
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unsigned long rate = inrate;
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unsigned int ctrl = 0;
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clkevt_base = base;
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/* Calculate and program a divisor */
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if (rate > 0x100000 * HZ) {
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rate /= 256;
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ctrl |= TIMER_CTRL_DIV256;
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} else if (rate > 0x10000 * HZ) {
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rate /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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timer_reload = rate / HZ;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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setup_irq(irq, &integrator_timer_irq);
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clockevents_config_and_register(&integrator_clockevent,
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rate,
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1,
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0xffffU);
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}
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void __init ap_init_early(void)
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{
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}
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static void __init ap_of_timer_init(void)
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{
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struct device_node *node;
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const char *path;
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void __iomem *base;
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int err;
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int irq;
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struct clk *clk;
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unsigned long rate;
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of_clk_init(NULL);
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err = of_property_read_string(of_aliases,
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"arm,timer-primary", &path);
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if (WARN_ON(err))
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return;
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node = of_find_node_by_path(path);
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base = of_iomap(node, 0);
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if (WARN_ON(!base))
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return;
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clk = of_clk_get(node, 0);
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BUG_ON(IS_ERR(clk));
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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writel(0, base + TIMER_CTRL);
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integrator_clocksource_init(rate, base);
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err = of_property_read_string(of_aliases,
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"arm,timer-secondary", &path);
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if (WARN_ON(err))
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return;
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node = of_find_node_by_path(path);
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base = of_iomap(node, 0);
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if (WARN_ON(!base))
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return;
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irq = irq_of_parse_and_map(node, 0);
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clk = of_clk_get(node, 0);
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BUG_ON(IS_ERR(clk));
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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writel(0, base + TIMER_CTRL);
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integrator_clockevent_init(rate, base, irq);
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}
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static void __init ap_init_irq_of(void)
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{
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cm_init();
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@ -553,7 +364,6 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
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.map_io = ap_map_io,
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.init_early = ap_init_early,
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.init_irq = ap_init_irq_of,
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.init_time = ap_of_timer_init,
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.init_machine = ap_init_of,
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.restart = integrator_restart,
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.dt_compat = ap_dt_board_compat,
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@ -45,4 +45,5 @@ obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
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obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
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obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o
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obj-$(CONFIG_ARCH_KEYSTONE) += timer-keystone.o
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obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o
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obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
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@ -0,0 +1,210 @@
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/*
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* Integrator/AP timer driver
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* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
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* Copyright (c) 2014, Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/sched_clock.h>
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#include <asm/hardware/arm_timer.h>
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static void __iomem * sched_clk_base;
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static u64 notrace integrator_read_sched_clock(void)
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{
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return -readl(sched_clk_base + TIMER_VALUE);
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}
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static void integrator_clocksource_init(unsigned long inrate,
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void __iomem *base)
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{
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u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
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unsigned long rate = inrate;
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if (rate >= 1500000) {
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rate /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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writel(0xffff, base + TIMER_LOAD);
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writel(ctrl, base + TIMER_CTRL);
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clocksource_mmio_init(base + TIMER_VALUE, "timer2",
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rate, 200, 16, clocksource_mmio_readl_down);
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sched_clk_base = base;
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sched_clock_register(integrator_read_sched_clock, 16, rate);
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}
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static unsigned long timer_reload;
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static void __iomem * clkevt_base;
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
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{
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u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
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/* Disable timer */
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writel(ctrl, clkevt_base + TIMER_CTRL);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* Enable the timer and start the periodic tick */
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writel(timer_reload, clkevt_base + TIMER_LOAD);
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ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Leave the timer disabled, .set_next_event will enable it */
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ctrl &= ~TIMER_CTRL_PERIODIC;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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default:
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/* Just leave in disabled state */
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break;
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}
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}
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static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
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{
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unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
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writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device integrator_clockevent = {
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.name = "timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = clkevt_set_mode,
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.set_next_event = clkevt_set_next_event,
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.rating = 300,
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};
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static struct irqaction integrator_timer_irq = {
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.name = "timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = integrator_timer_interrupt,
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.dev_id = &integrator_clockevent,
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};
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static void integrator_clockevent_init(unsigned long inrate,
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void __iomem *base, int irq)
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{
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unsigned long rate = inrate;
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unsigned int ctrl = 0;
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clkevt_base = base;
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/* Calculate and program a divisor */
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if (rate > 0x100000 * HZ) {
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rate /= 256;
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ctrl |= TIMER_CTRL_DIV256;
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} else if (rate > 0x10000 * HZ) {
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rate /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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timer_reload = rate / HZ;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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setup_irq(irq, &integrator_timer_irq);
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clockevents_config_and_register(&integrator_clockevent,
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rate,
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1,
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0xffffU);
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}
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static void __init integrator_ap_timer_init_of(struct device_node *node)
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{
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const char *path;
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void __iomem *base;
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int err;
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int irq;
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struct clk *clk;
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unsigned long rate;
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struct device_node *pri_node;
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struct device_node *sec_node;
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base = of_io_request_and_map(node, 0, "integrator-timer");
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if (!base)
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return;
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("No clock for %s\n", node->name);
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return;
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}
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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writel(0, base + TIMER_CTRL);
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err = of_property_read_string(of_aliases,
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"arm,timer-primary", &path);
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if (WARN_ON(err))
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return;
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pri_node = of_find_node_by_path(path);
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err = of_property_read_string(of_aliases,
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"arm,timer-secondary", &path);
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if (WARN_ON(err))
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return;
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sec_node = of_find_node_by_path(path);
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if (node == pri_node) {
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/* The primary timer lacks IRQ, use as clocksource */
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integrator_clocksource_init(rate, base);
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return;
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}
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if (node == sec_node) {
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/* The secondary timer will drive the clock event */
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irq = irq_of_parse_and_map(node, 0);
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integrator_clockevent_init(rate, base, irq);
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return;
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}
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pr_info("Timer @%p unused\n", base);
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clk_disable_unprepare(clk);
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}
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CLOCKSOURCE_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
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integrator_ap_timer_init_of);
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