sh: hd64461: Fix up I/O base register offsets.
hd64461 is mapped in a fixed location, so the I/O base itself is fairly meaningless as a configuration item. Additionally, this makes it impossible to share hd64461 code alongside generic drivers (in the case of sh_dac_audio), so simply make it commonly defined and permit the mach_is_foo() logic to work out the proper semantics. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
Родитель
9304d0ccf1
Коммит
bec36eca6f
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@ -34,11 +34,6 @@ config HD64461_IRQ
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Do not change this unless you know what you are doing.
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config HD64461_IOBASE
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hex "HD64461 start address"
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depends on HD64461
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default "0xb0000000"
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config HD64461_ENABLER
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bool "HD64461 PCMCIA enabler"
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depends on HD64461
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@ -13,13 +13,15 @@
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#define HD64461_PCC_WINDOW 0x01000000
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/* Area 6 - Slot 0 - memory and/or IO card */
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#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000)
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#define HD64461_IOBASE 0xb0000000
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#define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x))
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#define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
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#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
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#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
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#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
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/* Area 5 - Slot 1 - memory card only */
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#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000)
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#define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
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#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
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#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
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@ -41,19 +43,19 @@
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#define HD64461_STBCR_SURTST 0x0001
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/* System Configuration Register */
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#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02)
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#define HD64461_SYSCR HD64461_IO_OFFSET(0x02)
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/* CPU Data Bus Control Register */
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#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04)
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#define HD64461_SCPUCR HD64461_IO_OFFSET(0x04)
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/* Base Address Register */
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#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000)
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#define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000)
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/* Line increment address */
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#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002)
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#define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002)
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/* Controls LCD controller */
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#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004)
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#define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004)
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/* LCCDR control bits */
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#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
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@ -64,30 +66,30 @@
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#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
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/* Controls LCD (1) */
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#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010)
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#define HD64461_LDR1 HD64461_IO_OFFSET(0x1010)
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#define HD64461_LDR1_DON 0x01 /* Display On */
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#define HD64461_LDR1_DINV 0x80 /* Display Invert */
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/* Controls LCD (2) */
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#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012)
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#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */
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#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */
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#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */
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#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */
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#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */
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#define HD64461_LDR2 HD64461_IO_OFFSET(0x1012)
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#define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */
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#define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */
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#define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */
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#define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */
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#define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */
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/* Controls LCD (3) */
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#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e)
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#define HD64461_LDR3 HD64461_IO_OFFSET(0x101e)
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/* Palette Registers */
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#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */
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#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */
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#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */
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#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */
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#define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */
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#define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */
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#define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */
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#define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */
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#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */
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#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */
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#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */
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#define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */
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#define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */
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#define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
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#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
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#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
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@ -97,41 +99,41 @@
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#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
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/* Line Drawing Registers */
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#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */
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#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */
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#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */
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#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */
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#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */
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#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */
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#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */
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#define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
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#define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
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#define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */
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#define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */
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#define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */
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#define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
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#define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */
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/* BitBLT Registers */
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#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */
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#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */
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#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */
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#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */
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#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */
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#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */
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#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */
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#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */
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#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */
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#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */
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#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */
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#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */
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#define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
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#define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
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#define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
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#define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
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#define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */
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#define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */
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#define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
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#define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
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#define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
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#define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
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#define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */
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#define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */
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/* PC Card Controller Registers */
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/* Maps to Physical Area 6 */
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#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */
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#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */
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#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */
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#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */
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#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */
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#define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */
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#define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */
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#define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */
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#define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */
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#define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */
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/* Maps to Physical Area 5 */
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#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */
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#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */
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#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */
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#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */
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#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */
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#define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */
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#define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */
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#define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */
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#define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */
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#define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */
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/* PCC Interface Status Register */
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#define HD64461_PCCISR_READY 0x80 /* card ready */
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@ -189,41 +191,41 @@
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#define HD64461_PCCSCR_SWP 0x01 /* write protect */
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/* PCC0 Output Pins Control Register */
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#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a)
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#define HD64461_P0OCR HD64461_IO_OFFSET(0x202a)
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/* PCC1 Output Pins Control Register */
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#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c)
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#define HD64461_P1OCR HD64461_IO_OFFSET(0x202c)
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/* PC Card General Control Register */
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#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e)
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#define HD64461_PGCR HD64461_IO_OFFSET(0x202e)
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/* Port Control Registers */
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#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */
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#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */
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#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */
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#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */
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#define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */
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#define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */
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#define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */
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#define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */
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/* Port Control Data Registers */
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#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */
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#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */
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#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */
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#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */
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#define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */
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#define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */
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#define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */
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#define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */
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/* Interrupt Control Registers */
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#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */
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#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */
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#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */
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#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */
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#define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */
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#define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */
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#define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */
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#define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */
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/* Interrupt Status Registers */
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#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */
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#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */
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#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */
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#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */
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#define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */
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#define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */
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#define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */
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#define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */
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/* Interrupt Request Register & Interrupt Mask Register */
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#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000)
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#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002)
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#define HD64461_NIRR HD64461_IO_OFFSET(0x5000)
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#define HD64461_NIMR HD64461_IO_OFFSET(0x5002)
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#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
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#define OFFCHIP_IRQ_BASE 64
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