[MIPS] Tidy up cache attributes
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Chris Dearman
Ralf Baechle
Родитель
962f480e0f
Коммит
bec5052743
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@ -39,7 +39,7 @@
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#define _PAGE_WRITE (1<<8) /* implemented in software */
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#define _PAGE_ACCESSED (1<<9) /* implemented in software */
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#define _PAGE_MODIFIED (1<<10) /* implemented in software */
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#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */
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#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */
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#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */
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#define _PAGE_GLOBAL (1<<0)
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@ -47,15 +47,9 @@
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#define _PAGE_SILENT_READ (1<<1) /* synonym */
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#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1<<2)
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#define _CACHE_SHIFT 3
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#define _CACHE_MASK (7<<3)
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/* MIPS32 defines only values 2 and 3. The rest are implementation
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* dependent.
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*/
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#define _CACHE_UNCACHED (2<<3)
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#define _CACHE_CACHABLE_NONCOHERENT (3<<3)
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#define _CACHE_CACHABLE_COW (3<<3) /* Au1x */
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#else
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#define _PAGE_PRESENT (1<<0) /* implemented in software */
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@ -74,55 +68,66 @@
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#define _PAGE_SILENT_WRITE (1<<10)
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#define _CACHE_UNCACHED (1<<11)
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#define _CACHE_MASK (1<<11)
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#define _CACHE_CACHABLE_NONCOHERENT 0
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#else
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#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
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#define _PAGE_GLOBAL (1<<6)
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#define _PAGE_VALID (1<<7)
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#define _PAGE_SILENT_READ (1<<7) /* synonym */
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#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1<<8)
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#define _CACHE_SHIFT 9
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#define _CACHE_MASK (7<<9)
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#ifdef CONFIG_CPU_SB1
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#endif
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#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
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/*
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* Cache attributes
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*/
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define _CACHE_CACHABLE_NONCOHERENT 0
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#elif defined(CONFIG_CPU_SB1)
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/* No penalty for being coherent on the SB1, so just
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use it for "noncoherent" spaces, too. Shouldn't hurt. */
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#define _CACHE_UNCACHED (2<<9)
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#define _CACHE_CACHABLE_COW (5<<9)
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#define _CACHE_CACHABLE_NONCOHERENT (5<<9)
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#define _CACHE_UNCACHED_ACCELERATED (7<<9)
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#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
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#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
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#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
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#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
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#elif defined(CONFIG_CPU_RM9000)
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#define _CACHE_WT (0 << 9)
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#define _CACHE_WTWA (1 << 9)
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#define _CACHE_UC_B (2 << 9)
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#define _CACHE_WB (3 << 9)
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#define _CACHE_CWBEA (4 << 9)
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#define _CACHE_CWB (5 << 9)
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#define _CACHE_UCNB (6 << 9)
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#define _CACHE_FPC (7 << 9)
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#define _CACHE_WT (0<<_CACHE_SHIFT)
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#define _CACHE_WTWA (1<<_CACHE_SHIFT)
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#define _CACHE_UC_B (2<<_CACHE_SHIFT)
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#define _CACHE_WB (3<<_CACHE_SHIFT)
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#define _CACHE_CWBEA (4<<_CACHE_SHIFT)
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#define _CACHE_CWB (5<<_CACHE_SHIFT)
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#define _CACHE_UCNB (6<<_CACHE_SHIFT)
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#define _CACHE_FPC (7<<_CACHE_SHIFT)
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#define _CACHE_UNCACHED _CACHE_UC_B
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#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
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#define _CACHE_UNCACHED _CACHE_UC_B
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#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
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#else
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#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */
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#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */
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#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */
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#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */
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#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */
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#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */
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#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */
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#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */
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#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
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#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */
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#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */
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#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */
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#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */
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#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */
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#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
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#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */
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#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */
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#endif
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#endif
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#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
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#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
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#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
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@ -135,14 +140,12 @@
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#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
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#elif defined(CONFIG_CPU_RM9000)
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#define PAGE_CACHABLE_DEFAULT _CACHE_CWB
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#elif defined(CONFIG_SOC_AU1X00)
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#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
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#else
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#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
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#endif
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
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#else
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#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
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#endif
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#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
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#endif /* _ASM_PGTABLE_BITS_H */
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