hpsa: slightly optimize SA5_performant_completed
Reviewed-by: Scott Teel <scott.teel@pmcs.com> Signed-off-by: Don Brace <don.brace@pmcs.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
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34f0c6277c
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bee266a6d5
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@ -412,19 +412,19 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
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unsigned long register_value = FIFO_EMPTY;
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/* msi auto clears the interrupt pending bit. */
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if (!(h->msi_vector || h->msix_vector)) {
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if (unlikely(!(h->msi_vector || h->msix_vector))) {
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/* flush the controller write of the reply queue by reading
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* outbound doorbell status register.
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*/
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register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
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(void) readl(h->vaddr + SA5_OUTDB_STATUS);
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writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
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/* Do a read in order to flush the write to the controller
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* (as per spec.)
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*/
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register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
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(void) readl(h->vaddr + SA5_OUTDB_STATUS);
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}
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if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
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if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
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register_value = rq->head[rq->current_entry];
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rq->current_entry++;
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atomic_dec(&h->commands_outstanding);
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