igb: add locking to reads of the i2c interface
The current implementation of sgmii support isn't correctly locking the interfaces for reads/writes. This change pulls the read/write functionality out of 82575.c and moves it to phy.c. In addition it replaces the implementation in 82575.c with one that uses locking around the relocated i2c interface calls. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexander Duyck
David S. Miller
Родитель
008c3422d4
Коммит
bf6f7a928d
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@ -277,45 +277,23 @@ static void igb_release_phy_82575(struct e1000_hw *hw)
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static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
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u16 *data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, i2ccmd = 0;
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s32 ret_val = -E1000_ERR_PARAM;
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if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
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hw_dbg("PHY Address %u is out of range\n", offset);
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return -E1000_ERR_PARAM;
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goto out;
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}
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/*
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* Set up Op-code, Phy Address, and register address in the I2CCMD
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* register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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*/
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i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
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(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
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(E1000_I2CCMD_OPCODE_READ));
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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goto out;
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wr32(E1000_I2CCMD, i2ccmd);
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ret_val = igb_read_phy_reg_i2c(hw, offset, data);
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/* Poll the ready bit to see if the I2C read completed */
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for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
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udelay(50);
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i2ccmd = rd32(E1000_I2CCMD);
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if (i2ccmd & E1000_I2CCMD_READY)
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break;
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}
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if (!(i2ccmd & E1000_I2CCMD_READY)) {
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hw_dbg("I2CCMD Read did not complete\n");
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return -E1000_ERR_PHY;
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}
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if (i2ccmd & E1000_I2CCMD_ERROR) {
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hw_dbg("I2CCMD Error bit set\n");
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return -E1000_ERR_PHY;
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}
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hw->phy.ops.release(hw);
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/* Need to byte-swap the 16-bit value. */
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*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
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return 0;
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out:
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return ret_val;
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}
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/**
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@ -330,47 +308,24 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
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static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
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u16 data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, i2ccmd = 0;
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u16 phy_data_swapped;
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s32 ret_val = -E1000_ERR_PARAM;
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if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
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hw_dbg("PHY Address %d is out of range\n", offset);
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return -E1000_ERR_PARAM;
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goto out;
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}
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/* Swap the data bytes for the I2C interface */
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phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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goto out;
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/*
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* Set up Op-code, Phy Address, and register address in the I2CCMD
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* register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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*/
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i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
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(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
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E1000_I2CCMD_OPCODE_WRITE |
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phy_data_swapped);
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ret_val = igb_write_phy_reg_i2c(hw, offset, data);
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wr32(E1000_I2CCMD, i2ccmd);
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hw->phy.ops.release(hw);
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/* Poll the ready bit to see if the I2C read completed */
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for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
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udelay(50);
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i2ccmd = rd32(E1000_I2CCMD);
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if (i2ccmd & E1000_I2CCMD_READY)
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break;
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}
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if (!(i2ccmd & E1000_I2CCMD_READY)) {
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hw_dbg("I2CCMD Write did not complete\n");
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return -E1000_ERR_PHY;
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}
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if (i2ccmd & E1000_I2CCMD_ERROR) {
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hw_dbg("I2CCMD Error bit set\n");
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return -E1000_ERR_PHY;
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}
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return 0;
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out:
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return ret_val;
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}
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/**
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@ -238,6 +238,103 @@ out:
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return ret_val;
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}
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/**
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* igb_read_phy_reg_i2c - Read PHY register using i2c
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* @hw: pointer to the HW structure
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* @offset: register offset to be read
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* @data: pointer to the read data
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*
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* Reads the PHY register at offset using the i2c interface and stores the
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* retrieved information in data.
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**/
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s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, i2ccmd = 0;
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/*
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* Set up Op-code, Phy Address, and register address in the I2CCMD
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* register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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*/
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i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
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(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
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(E1000_I2CCMD_OPCODE_READ));
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wr32(E1000_I2CCMD, i2ccmd);
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/* Poll the ready bit to see if the I2C read completed */
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for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
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udelay(50);
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i2ccmd = rd32(E1000_I2CCMD);
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if (i2ccmd & E1000_I2CCMD_READY)
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break;
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}
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if (!(i2ccmd & E1000_I2CCMD_READY)) {
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hw_dbg("I2CCMD Read did not complete\n");
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return -E1000_ERR_PHY;
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}
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if (i2ccmd & E1000_I2CCMD_ERROR) {
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hw_dbg("I2CCMD Error bit set\n");
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return -E1000_ERR_PHY;
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}
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/* Need to byte-swap the 16-bit value. */
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*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
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return 0;
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}
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/**
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* igb_write_phy_reg_i2c - Write PHY register using i2c
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* @hw: pointer to the HW structure
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* @offset: register offset to write to
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* @data: data to write at register offset
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*
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* Writes the data to PHY register at the offset using the i2c interface.
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**/
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s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, i2ccmd = 0;
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u16 phy_data_swapped;
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/* Swap the data bytes for the I2C interface */
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phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
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/*
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* Set up Op-code, Phy Address, and register address in the I2CCMD
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* register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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*/
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i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
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(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
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E1000_I2CCMD_OPCODE_WRITE |
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phy_data_swapped);
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wr32(E1000_I2CCMD, i2ccmd);
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/* Poll the ready bit to see if the I2C read completed */
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for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
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udelay(50);
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i2ccmd = rd32(E1000_I2CCMD);
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if (i2ccmd & E1000_I2CCMD_READY)
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break;
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}
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if (!(i2ccmd & E1000_I2CCMD_READY)) {
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hw_dbg("I2CCMD Write did not complete\n");
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return -E1000_ERR_PHY;
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}
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if (i2ccmd & E1000_I2CCMD_ERROR) {
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hw_dbg("I2CCMD Error bit set\n");
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return -E1000_ERR_PHY;
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}
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return 0;
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}
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/**
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* igb_read_phy_reg_igp - Read igp PHY register
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* @hw: pointer to the HW structure
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@ -61,6 +61,8 @@ s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
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s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
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u32 usec_interval, bool *success);
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s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
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s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
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/* IGP01E1000 Specific Registers */
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#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
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