drm/i915/xehp: Xe_HP forcewake support
Implement Xe_HP forcewake handling. While we're at it, let's reorder to the forcewake assignment if/else ladder to match our usual driver conventions. Co-authored-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-6-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper
Родитель
ddabf72176
Коммит
bfac1e2b6e
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@ -3357,6 +3357,10 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
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i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
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execlists->ctrl_reg = uncore->regs +
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i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
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engine->fw_domain = intel_uncore_forcewake_for_reg(engine->uncore,
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RING_EXECLIST_CONTROL(engine->mmio_base),
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FW_REG_WRITE);
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} else {
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execlists->submit_reg = uncore->regs +
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i915_mmio_reg_offset(RING_ELSP(base));
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@ -24,6 +24,8 @@
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#include <linux/pm_runtime.h>
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#include <asm/iosf_mbi.h>
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#include "gt/intel_lrc_reg.h" /* for shadow reg list */
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "i915_vgpu.h"
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@ -68,8 +70,14 @@ static const char * const forcewake_domain_names[] = {
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"vdbox1",
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"vdbox2",
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"vdbox3",
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"vdbox4",
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"vdbox5",
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"vdbox6",
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"vdbox7",
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"vebox0",
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"vebox1",
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"vebox2",
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"vebox3",
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};
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const char *
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@ -952,30 +960,80 @@ static const i915_reg_t gen8_shadowed_regs[] = {
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};
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static const i915_reg_t gen11_shadowed_regs[] = {
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RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
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GEN6_RPNSWREQ, /* 0xA008 */
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GEN6_RC_VIDEO_FREQ, /* 0xA00C */
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RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
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RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
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RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
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RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
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RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
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RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
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RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
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RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
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RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */
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GEN6_RPNSWREQ, /* 0xA008 */
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GEN6_RC_VIDEO_FREQ, /* 0xA00C */
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RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
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RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */
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RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */
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RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE), /* 0x1C4550 */
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RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
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RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */
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RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE), /* 0x1D0550 */
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RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE), /* 0x1D4550 */
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RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
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RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE), /* 0x1D8550 */
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/* TODO: Other registers are not yet used */
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};
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static const i915_reg_t gen12_shadowed_regs[] = {
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RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
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GEN6_RPNSWREQ, /* 0xA008 */
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GEN6_RC_VIDEO_FREQ, /* 0xA00C */
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RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
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RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
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RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
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RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
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RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
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RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
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RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
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RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
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RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */
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GEN6_RPNSWREQ, /* 0xA008 */
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GEN6_RC_VIDEO_FREQ, /* 0xA00C */
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RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
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RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */
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RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */
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RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE), /* 0x1C4550 */
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RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
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RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */
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RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE), /* 0x1D0550 */
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RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE), /* 0x1D4550 */
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RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
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RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE), /* 0x1D8550 */
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/* TODO: Other registers are not yet used */
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};
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static const i915_reg_t xehp_shadowed_regs[] = {
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RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
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RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */
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GEN6_RPNSWREQ, /* 0xA008 */
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GEN6_RC_VIDEO_FREQ, /* 0xA00C */
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RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
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RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */
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RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */
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RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE), /* 0x1C4550 */
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RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
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RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */
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RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE), /* 0x1D0550 */
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RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
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RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE), /* 0x1D4550 */
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RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
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RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE), /* 0x1D8550 */
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RING_TAIL(XEHP_BSD5_RING_BASE), /* 0x1E0000 (base) */
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RING_EXECLIST_CONTROL(XEHP_BSD5_RING_BASE), /* 0x1E0550 */
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RING_TAIL(XEHP_BSD6_RING_BASE), /* 0x1E4000 (base) */
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RING_EXECLIST_CONTROL(XEHP_BSD6_RING_BASE), /* 0x1E4550 */
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RING_TAIL(XEHP_VEBOX3_RING_BASE), /* 0x1E8000 (base) */
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RING_EXECLIST_CONTROL(XEHP_VEBOX3_RING_BASE), /* 0x1E8550 */
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RING_TAIL(XEHP_BSD7_RING_BASE), /* 0x1F0000 (base) */
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RING_EXECLIST_CONTROL(XEHP_BSD7_RING_BASE), /* 0x1F0550 */
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RING_TAIL(XEHP_BSD8_RING_BASE), /* 0x1F4000 (base) */
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RING_EXECLIST_CONTROL(XEHP_BSD8_RING_BASE), /* 0x1F4550 */
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RING_TAIL(XEHP_VEBOX4_RING_BASE), /* 0x1F8000 (base) */
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RING_EXECLIST_CONTROL(XEHP_VEBOX4_RING_BASE), /* 0x1F8550 */
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/* TODO: Other registers are not yet used */
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};
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@ -991,17 +1049,18 @@ static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
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return 0;
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}
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#define __is_genX_shadowed(x) \
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static bool is_gen##x##_shadowed(u32 offset) \
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#define __is_X_shadowed(x) \
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static bool is_##x##_shadowed(u32 offset) \
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{ \
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const i915_reg_t *regs = gen##x##_shadowed_regs; \
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return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
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const i915_reg_t *regs = x##_shadowed_regs; \
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return BSEARCH(offset, regs, ARRAY_SIZE(x##_shadowed_regs), \
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mmio_reg_cmp); \
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}
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__is_genX_shadowed(8)
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__is_genX_shadowed(11)
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__is_genX_shadowed(12)
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__is_X_shadowed(gen8)
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__is_X_shadowed(gen11)
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__is_X_shadowed(gen12)
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__is_X_shadowed(xehp)
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static enum forcewake_domains
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gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
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@ -1065,6 +1124,15 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
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__fwd; \
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})
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#define __xehp_fwtable_reg_write_fw_domains(uncore, offset) \
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({ \
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enum forcewake_domains __fwd = 0; \
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const u32 __offset = (offset); \
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if (!is_xehp_shadowed(__offset)) \
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__fwd = find_fw_domain(uncore, __offset); \
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__fwd; \
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})
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/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
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static const struct intel_forcewake_range __gen9_fw_ranges[] = {
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GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
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@ -1249,6 +1317,145 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
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0x1d3f00 - 0x1d3fff: VD2 */
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};
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/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
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static const struct intel_forcewake_range __xehp_fw_ranges[] = {
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GEN_FW_RANGE(0x0, 0x1fff, 0), /*
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0x0 - 0xaff: reserved
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0xb00 - 0x1fff: always on */
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GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
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GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT),
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GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*
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0x4b00 - 0x4fff: reserved
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0x5000 - 0x51ff: always on */
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GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
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GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
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GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
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GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
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0x8160 - 0x817f: reserved
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0x8180 - 0x81ff: always on */
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GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
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GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
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GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
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0x8500 - 0x87ff: gt
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0x8800 - 0x8fff: reserved
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0x9000 - 0x947f: gt
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0x9480 - 0x94cf: reserved */
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GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
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GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
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0x9560 - 0x95ff: always on
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0x9600 - 0x97ff: reserved */
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GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
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0x9800 - 0xb4ff: gt
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0xb500 - 0xbfff: reserved
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0xc000 - 0xcfff: gt */
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GEN_FW_RANGE(0xd000, 0xd7ff, 0),
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GEN_FW_RANGE(0xd800, 0xdbff, FORCEWAKE_GT),
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GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
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GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
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0xdd00 - 0xddff: gt
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0xde00 - 0xde7f: reserved */
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GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
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0xde80 - 0xdfff: render
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0xe000 - 0xe0ff: reserved
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0xe100 - 0xe8ff: render */
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GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /*
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0xe900 - 0xe9ff: gt
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0xea00 - 0xefff: reserved
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0xf000 - 0xffff: gt */
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GEN_FW_RANGE(0x10000, 0x13fff, 0), /*
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0x10000 - 0x11fff: reserved
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0x12000 - 0x127ff: always on
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0x12800 - 0x13fff: reserved */
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GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0),
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GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2),
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GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4),
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GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6),
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GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /*
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0x14800 - 0x14fff: render
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0x15000 - 0x16dff: reserved
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0x16e00 - 0x1ffff: render */
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GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*
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0x20000 - 0x20fff: VD0
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0x21000 - 0x21fff: reserved */
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GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
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GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
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0x24000 - 0x2407f: always on
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0x24080 - 0x2417f: reserved */
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GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
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0x24180 - 0x241ff: gt
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0x24200 - 0x249ff: reserved */
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GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
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0x24a00 - 0x24a7f: render
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0x24a80 - 0x251ff: reserved */
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GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /*
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0x25200 - 0x252ff: gt
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0x25300 - 0x25fff: reserved */
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GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
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0x26000 - 0x27fff: render
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0x28000 - 0x29fff: reserved
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0x2a000 - 0x2ffff: undocumented */
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GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
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GEN_FW_RANGE(0x40000, 0x1bffff, 0),
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GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
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0x1c0000 - 0x1c2bff: VD0
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0x1c2c00 - 0x1c2cff: reserved
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0x1c2d00 - 0x1c2dff: VD0
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0x1c2e00 - 0x1c3eff: reserved
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0x1c3f00 - 0x1c3fff: VD0 */
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GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /*
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0x1c4000 - 0x1c6bff: VD1
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0x1c6c00 - 0x1c6cff: reserved
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0x1c6d00 - 0x1c6dff: VD1
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0x1c6e00 - 0x1c7fff: reserved */
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GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
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0x1c8000 - 0x1ca0ff: VE0
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0x1ca100 - 0x1cbfff: reserved */
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GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0),
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GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2),
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GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4),
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GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6),
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GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
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0x1d0000 - 0x1d2bff: VD2
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0x1d2c00 - 0x1d2cff: reserved
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0x1d2d00 - 0x1d2dff: VD2
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0x1d2e00 - 0x1d3eff: reserved
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0x1d3f00 - 0x1d3fff: VD2 */
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GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /*
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0x1d4000 - 0x1d6bff: VD3
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0x1d6c00 - 0x1d6cff: reserved
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0x1d6d00 - 0x1d6dff: VD3
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0x1d6e00 - 0x1d7fff: reserved */
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GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /*
|
||||
0x1d8000 - 0x1da0ff: VE1
|
||||
0x1da100 - 0x1dffff: reserved */
|
||||
GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /*
|
||||
0x1e0000 - 0x1e2bff: VD4
|
||||
0x1e2c00 - 0x1e2cff: reserved
|
||||
0x1e2d00 - 0x1e2dff: VD4
|
||||
0x1e2e00 - 0x1e3eff: reserved
|
||||
0x1e3f00 - 0x1e3fff: VD4 */
|
||||
GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /*
|
||||
0x1e4000 - 0x1e6bff: VD5
|
||||
0x1e6c00 - 0x1e6cff: reserved
|
||||
0x1e6d00 - 0x1e6dff: VD5
|
||||
0x1e6e00 - 0x1e7fff: reserved */
|
||||
GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /*
|
||||
0x1e8000 - 0x1ea0ff: VE2
|
||||
0x1ea100 - 0x1effff: reserved */
|
||||
GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /*
|
||||
0x1f0000 - 0x1f2bff: VD6
|
||||
0x1f2c00 - 0x1f2cff: reserved
|
||||
0x1f2d00 - 0x1f2dff: VD6
|
||||
0x1f2e00 - 0x1f3eff: reserved
|
||||
0x1f3f00 - 0x1f3fff: VD6 */
|
||||
GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /*
|
||||
0x1f4000 - 0x1f6bff: VD7
|
||||
0x1f6c00 - 0x1f6cff: reserved
|
||||
0x1f6d00 - 0x1f6dff: VD7
|
||||
0x1f6e00 - 0x1f7fff: reserved */
|
||||
GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
|
||||
};
|
||||
|
||||
static void
|
||||
ilk_dummy_write(struct intel_uncore *uncore)
|
||||
{
|
||||
|
|
@ -1502,6 +1709,7 @@ __gen_write(func, 8) \
|
|||
__gen_write(func, 16) \
|
||||
__gen_write(func, 32)
|
||||
|
||||
__gen_reg_write_funcs(xehp_fwtable);
|
||||
__gen_reg_write_funcs(gen12_fwtable);
|
||||
__gen_reg_write_funcs(gen11_fwtable);
|
||||
__gen_reg_write_funcs(fwtable);
|
||||
|
|
@ -1582,8 +1790,14 @@ static int __fw_domain_init(struct intel_uncore *uncore,
|
|||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2));
|
||||
BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3));
|
||||
|
||||
d->mask = BIT(domain_id);
|
||||
|
||||
|
|
@ -1870,36 +2084,36 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
|
|||
return ret;
|
||||
forcewake_early_sanitize(uncore, 0);
|
||||
|
||||
if (IS_GRAPHICS_VER(i915, 6, 7)) {
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
|
||||
|
||||
if (IS_VALLEYVIEW(i915)) {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
|
||||
} else {
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
|
||||
}
|
||||
} else if (GRAPHICS_VER(i915) == 8) {
|
||||
if (IS_CHERRYVIEW(i915)) {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
|
||||
} else {
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
|
||||
}
|
||||
} else if (IS_GRAPHICS_VER(i915, 9, 10)) {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
|
||||
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
|
||||
} else if (GRAPHICS_VER(i915) >= 12) {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
|
||||
} else if (GRAPHICS_VER(i915) == 11) {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
|
||||
} else {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
|
||||
} else if (IS_GRAPHICS_VER(i915, 9, 10)) {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
|
||||
} else if (IS_CHERRYVIEW(i915)) {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
|
||||
} else if (GRAPHICS_VER(i915) == 8) {
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
|
||||
} else if (IS_VALLEYVIEW(i915)) {
|
||||
ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
|
||||
} else if (IS_GRAPHICS_VER(i915, 6, 7)) {
|
||||
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
|
||||
ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
|
||||
}
|
||||
|
||||
uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
|
||||
|
|
@ -1988,6 +2202,22 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
|
|||
if (HAS_ENGINE(gt, _VCS(i)))
|
||||
continue;
|
||||
|
||||
/*
|
||||
* Starting with XeHP, the power well for an even-numbered
|
||||
* VDBOX is also used for shared units within the
|
||||
* media slice such as SFC. So even if the engine
|
||||
* itself is fused off, we still need to initialize
|
||||
* the forcewake domain if any of the other engines
|
||||
* in the same media slice are present.
|
||||
*/
|
||||
if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) {
|
||||
if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1)))
|
||||
continue;
|
||||
|
||||
if (HAS_ENGINE(gt, _VECS(i / 2)))
|
||||
continue;
|
||||
}
|
||||
|
||||
if (fw_domains & BIT(domain_id))
|
||||
fw_domain_fini(uncore, domain_id);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -52,8 +52,14 @@ enum forcewake_domain_id {
|
|||
FW_DOMAIN_ID_MEDIA_VDBOX1,
|
||||
FW_DOMAIN_ID_MEDIA_VDBOX2,
|
||||
FW_DOMAIN_ID_MEDIA_VDBOX3,
|
||||
FW_DOMAIN_ID_MEDIA_VDBOX4,
|
||||
FW_DOMAIN_ID_MEDIA_VDBOX5,
|
||||
FW_DOMAIN_ID_MEDIA_VDBOX6,
|
||||
FW_DOMAIN_ID_MEDIA_VDBOX7,
|
||||
FW_DOMAIN_ID_MEDIA_VEBOX0,
|
||||
FW_DOMAIN_ID_MEDIA_VEBOX1,
|
||||
FW_DOMAIN_ID_MEDIA_VEBOX2,
|
||||
FW_DOMAIN_ID_MEDIA_VEBOX3,
|
||||
|
||||
FW_DOMAIN_ID_COUNT
|
||||
};
|
||||
|
|
@ -66,10 +72,16 @@ enum forcewake_domains {
|
|||
FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
|
||||
FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
|
||||
FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
|
||||
FORCEWAKE_MEDIA_VDBOX4 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX4),
|
||||
FORCEWAKE_MEDIA_VDBOX5 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX5),
|
||||
FORCEWAKE_MEDIA_VDBOX6 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX6),
|
||||
FORCEWAKE_MEDIA_VDBOX7 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX7),
|
||||
FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
|
||||
FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
|
||||
FORCEWAKE_MEDIA_VEBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX2),
|
||||
FORCEWAKE_MEDIA_VEBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX3),
|
||||
|
||||
FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
|
||||
FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1,
|
||||
};
|
||||
|
||||
struct intel_uncore_funcs {
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ static int intel_shadow_table_check(void)
|
|||
{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
|
||||
{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
|
||||
{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
|
||||
{ xehp_shadowed_regs, ARRAY_SIZE(xehp_shadowed_regs) },
|
||||
};
|
||||
const i915_reg_t *reg;
|
||||
unsigned int i, j;
|
||||
|
|
@ -103,6 +104,7 @@ int intel_uncore_mock_selftests(void)
|
|||
{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
|
||||
{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
|
||||
{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
|
||||
{ __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
|
||||
};
|
||||
int err, i;
|
||||
|
||||
|
|
|
|||
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