clk: samsung: exynos5250: Correct parent list of audio muxes
According to SoC documentation, input 5 of mout_audio muxes is connected to xxti (named fin_pll in the driver). This patch corrects defined parent arrays to match SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
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@ -208,19 +208,19 @@ PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
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"none", "none", "none",
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"none" };
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PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
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"sclk_uhostphy", "sclk_hdmiphy",
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"sclk_uhostphy", "fin_pll",
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"mout_mpll_user", "mout_epll", "mout_vpll",
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"mout_cpll", "none", "none",
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"none", "none", "none",
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"none" };
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PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
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"sclk_uhostphy", "sclk_hdmiphy",
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"sclk_uhostphy", "fin_pll",
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"mout_mpll_user", "mout_epll", "mout_vpll",
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"mout_cpll", "none", "none",
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"none", "none", "none",
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"none" };
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PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
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"sclk_uhostphy", "sclk_hdmiphy",
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"sclk_uhostphy", "fin_pll",
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"mout_mpll_user", "mout_epll", "mout_vpll",
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"mout_cpll", "none", "none",
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"none", "none", "none",
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