KVM: PPC: Book3S HV P9: inline kvmhv_load_hv_regs_and_go into __kvmhv_vcpu_entry_p9
Now the initial C implementation is done, inline more HV code to make rearranging things easier. And rename __kvmhv_vcpu_entry_p9 to drop the leading underscores as it's now C, and is now a more complete vcpu entry. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210528090752.3542186-16-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin
Michael Ellerman
Родитель
89d35b2391
Коммит
c00366e237
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@ -153,7 +153,7 @@ static inline bool kvmhv_vcpu_is_radix(struct kvm_vcpu *vcpu)
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return radix;
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return radix;
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}
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}
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int __kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu);
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int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr);
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#define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
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#define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
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#endif
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#endif
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@ -3501,192 +3501,6 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)
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trace_kvmppc_run_core(vc, 1);
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trace_kvmppc_run_core(vc, 1);
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}
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}
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static void switch_mmu_to_guest_radix(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr)
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{
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struct kvmppc_vcore *vc = vcpu->arch.vcore;
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struct kvm_nested_guest *nested = vcpu->arch.nested;
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u32 lpid;
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lpid = nested ? nested->shadow_lpid : kvm->arch.lpid;
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/*
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* All the isync()s are overkill but trivially follow the ISA
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* requirements. Some can likely be replaced with justification
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* comment for why they are not needed.
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*/
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isync();
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mtspr(SPRN_LPID, lpid);
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isync();
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mtspr(SPRN_LPCR, lpcr);
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isync();
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mtspr(SPRN_PID, vcpu->arch.pid);
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isync();
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/* TLBIEL must have LPIDR set, so set guest LPID before flushing. */
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kvmppc_check_need_tlb_flush(kvm, vc->pcpu, nested);
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}
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static void switch_mmu_to_host_radix(struct kvm *kvm, u32 pid)
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{
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isync();
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mtspr(SPRN_PID, pid);
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isync();
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mtspr(SPRN_LPID, kvm->arch.host_lpid);
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isync();
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mtspr(SPRN_LPCR, kvm->arch.host_lpcr);
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isync();
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}
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/*
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* Load up hypervisor-mode registers on P9.
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*/
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static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu *vcpu, u64 time_limit,
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unsigned long lpcr)
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{
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struct kvm *kvm = vcpu->kvm;
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struct kvmppc_vcore *vc = vcpu->arch.vcore;
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s64 hdec;
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u64 tb, purr, spurr;
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int trap;
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unsigned long host_hfscr = mfspr(SPRN_HFSCR);
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unsigned long host_ciabr = mfspr(SPRN_CIABR);
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unsigned long host_dawr0 = mfspr(SPRN_DAWR0);
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unsigned long host_dawrx0 = mfspr(SPRN_DAWRX0);
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unsigned long host_psscr = mfspr(SPRN_PSSCR);
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unsigned long host_pidr = mfspr(SPRN_PID);
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unsigned long host_dawr1 = 0;
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unsigned long host_dawrx1 = 0;
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if (cpu_has_feature(CPU_FTR_DAWR1)) {
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host_dawr1 = mfspr(SPRN_DAWR1);
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host_dawrx1 = mfspr(SPRN_DAWRX1);
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}
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hdec = time_limit - mftb();
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if (hdec < 0)
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return BOOK3S_INTERRUPT_HV_DECREMENTER;
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if (vc->tb_offset) {
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u64 new_tb = mftb() + vc->tb_offset;
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mtspr(SPRN_TBU40, new_tb);
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tb = mftb();
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if ((tb & 0xffffff) < (new_tb & 0xffffff))
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mtspr(SPRN_TBU40, new_tb + 0x1000000);
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vc->tb_offset_applied = vc->tb_offset;
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}
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if (vc->pcr)
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mtspr(SPRN_PCR, vc->pcr | PCR_MASK);
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mtspr(SPRN_DPDES, vc->dpdes);
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mtspr(SPRN_VTB, vc->vtb);
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local_paca->kvm_hstate.host_purr = mfspr(SPRN_PURR);
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local_paca->kvm_hstate.host_spurr = mfspr(SPRN_SPURR);
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mtspr(SPRN_PURR, vcpu->arch.purr);
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mtspr(SPRN_SPURR, vcpu->arch.spurr);
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if (dawr_enabled()) {
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mtspr(SPRN_DAWR0, vcpu->arch.dawr0);
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mtspr(SPRN_DAWRX0, vcpu->arch.dawrx0);
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if (cpu_has_feature(CPU_FTR_DAWR1)) {
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mtspr(SPRN_DAWR1, vcpu->arch.dawr1);
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mtspr(SPRN_DAWRX1, vcpu->arch.dawrx1);
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}
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}
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mtspr(SPRN_CIABR, vcpu->arch.ciabr);
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mtspr(SPRN_IC, vcpu->arch.ic);
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mtspr(SPRN_PSSCR, vcpu->arch.psscr | PSSCR_EC |
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(local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
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mtspr(SPRN_HFSCR, vcpu->arch.hfscr);
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mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0);
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mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1);
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mtspr(SPRN_SPRG2, vcpu->arch.shregs.sprg2);
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mtspr(SPRN_SPRG3, vcpu->arch.shregs.sprg3);
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mtspr(SPRN_AMOR, ~0UL);
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switch_mmu_to_guest_radix(kvm, vcpu, lpcr);
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/*
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* P9 suppresses the HDEC exception when LPCR[HDICE] = 0,
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* so set guest LPCR (with HDICE) before writing HDEC.
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*/
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mtspr(SPRN_HDEC, hdec);
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mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0);
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mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1);
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trap = __kvmhv_vcpu_entry_p9(vcpu);
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/* Advance host PURR/SPURR by the amount used by guest */
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purr = mfspr(SPRN_PURR);
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spurr = mfspr(SPRN_SPURR);
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mtspr(SPRN_PURR, local_paca->kvm_hstate.host_purr +
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purr - vcpu->arch.purr);
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mtspr(SPRN_SPURR, local_paca->kvm_hstate.host_spurr +
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spurr - vcpu->arch.spurr);
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vcpu->arch.purr = purr;
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vcpu->arch.spurr = spurr;
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vcpu->arch.ic = mfspr(SPRN_IC);
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vcpu->arch.pid = mfspr(SPRN_PID);
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vcpu->arch.psscr = mfspr(SPRN_PSSCR) & PSSCR_GUEST_VIS;
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vcpu->arch.shregs.sprg0 = mfspr(SPRN_SPRG0);
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vcpu->arch.shregs.sprg1 = mfspr(SPRN_SPRG1);
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vcpu->arch.shregs.sprg2 = mfspr(SPRN_SPRG2);
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vcpu->arch.shregs.sprg3 = mfspr(SPRN_SPRG3);
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/* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */
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mtspr(SPRN_PSSCR, host_psscr |
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(local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
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mtspr(SPRN_HFSCR, host_hfscr);
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mtspr(SPRN_CIABR, host_ciabr);
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mtspr(SPRN_DAWR0, host_dawr0);
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mtspr(SPRN_DAWRX0, host_dawrx0);
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if (cpu_has_feature(CPU_FTR_DAWR1)) {
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mtspr(SPRN_DAWR1, host_dawr1);
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mtspr(SPRN_DAWRX1, host_dawrx1);
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}
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/*
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* Since this is radix, do a eieio; tlbsync; ptesync sequence in
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* case we interrupted the guest between a tlbie and a ptesync.
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*/
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asm volatile("eieio; tlbsync; ptesync");
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/*
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* cp_abort is required if the processor supports local copy-paste
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* to clear the copy buffer that was under control of the guest.
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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asm volatile(PPC_CP_ABORT);
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vc->dpdes = mfspr(SPRN_DPDES);
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vc->vtb = mfspr(SPRN_VTB);
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mtspr(SPRN_DPDES, 0);
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if (vc->pcr)
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mtspr(SPRN_PCR, PCR_MASK);
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if (vc->tb_offset_applied) {
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u64 new_tb = mftb() - vc->tb_offset_applied;
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mtspr(SPRN_TBU40, new_tb);
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tb = mftb();
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if ((tb & 0xffffff) < (new_tb & 0xffffff))
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mtspr(SPRN_TBU40, new_tb + 0x1000000);
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vc->tb_offset_applied = 0;
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}
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mtspr(SPRN_HDEC, 0x7fffffff);
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switch_mmu_to_host_radix(kvm, host_pidr);
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return trap;
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}
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static inline bool hcall_is_xics(unsigned long req)
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static inline bool hcall_is_xics(unsigned long req)
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{
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{
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return req == H_EOI || req == H_CPPR || req == H_IPI ||
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return req == H_EOI || req == H_CPPR || req == H_IPI ||
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@ -3784,7 +3598,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
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* We need to save and restore the guest visible part of the
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* We need to save and restore the guest visible part of the
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* psscr (i.e. using SPRN_PSSCR_PR) since the hypervisor
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* psscr (i.e. using SPRN_PSSCR_PR) since the hypervisor
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* doesn't do this for us. Note only required if pseries since
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* doesn't do this for us. Note only required if pseries since
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* this is done in kvmhv_load_hv_regs_and_go() below otherwise.
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* this is done in kvmhv_vcpu_entry_p9() below otherwise.
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*/
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*/
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unsigned long host_psscr;
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unsigned long host_psscr;
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/* call our hypervisor to load up HV regs and go */
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/* call our hypervisor to load up HV regs and go */
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@ -3822,7 +3636,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
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}
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}
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} else {
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} else {
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kvmppc_xive_push_vcpu(vcpu);
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kvmppc_xive_push_vcpu(vcpu);
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trap = kvmhv_load_hv_regs_and_go(vcpu, time_limit, lpcr);
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trap = kvmhv_vcpu_entry_p9(vcpu, time_limit, lpcr);
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if (trap == BOOK3S_INTERRUPT_SYSCALL && !vcpu->arch.nested &&
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if (trap == BOOK3S_INTERRUPT_SYSCALL && !vcpu->arch.nested &&
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!(vcpu->arch.shregs.msr & MSR_PR)) {
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!(vcpu->arch.shregs.msr & MSR_PR)) {
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unsigned long req = kvmppc_get_gpr(vcpu, 3);
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unsigned long req = kvmppc_get_gpr(vcpu, 3);
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@ -79,11 +79,121 @@ static void radix_clear_slb(void)
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clear_slb_entry(i);
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clear_slb_entry(i);
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}
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}
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int __kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu)
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static void switch_mmu_to_guest_radix(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr)
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{
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{
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struct kvmppc_vcore *vc = vcpu->arch.vcore;
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struct kvm_nested_guest *nested = vcpu->arch.nested;
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u32 lpid;
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lpid = nested ? nested->shadow_lpid : kvm->arch.lpid;
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/*
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* All the isync()s are overkill but trivially follow the ISA
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* requirements. Some can likely be replaced with justification
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* comment for why they are not needed.
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*/
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isync();
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mtspr(SPRN_LPID, lpid);
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isync();
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mtspr(SPRN_LPCR, lpcr);
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isync();
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mtspr(SPRN_PID, vcpu->arch.pid);
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isync();
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/* TLBIEL must have LPIDR set, so set guest LPID before flushing. */
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kvmppc_check_need_tlb_flush(kvm, vc->pcpu, nested);
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}
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static void switch_mmu_to_host_radix(struct kvm *kvm, u32 pid)
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{
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isync();
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mtspr(SPRN_PID, pid);
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isync();
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mtspr(SPRN_LPID, kvm->arch.host_lpid);
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isync();
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mtspr(SPRN_LPCR, kvm->arch.host_lpcr);
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isync();
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}
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int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr)
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{
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struct kvm *kvm = vcpu->kvm;
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struct kvmppc_vcore *vc = vcpu->arch.vcore;
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s64 hdec;
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u64 tb, purr, spurr;
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u64 *exsave;
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u64 *exsave;
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unsigned long msr = mfmsr();
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unsigned long msr = mfmsr();
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int trap;
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int trap;
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unsigned long host_hfscr = mfspr(SPRN_HFSCR);
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unsigned long host_ciabr = mfspr(SPRN_CIABR);
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unsigned long host_dawr0 = mfspr(SPRN_DAWR0);
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unsigned long host_dawrx0 = mfspr(SPRN_DAWRX0);
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unsigned long host_psscr = mfspr(SPRN_PSSCR);
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unsigned long host_pidr = mfspr(SPRN_PID);
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unsigned long host_dawr1 = 0;
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unsigned long host_dawrx1 = 0;
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if (cpu_has_feature(CPU_FTR_DAWR1)) {
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host_dawr1 = mfspr(SPRN_DAWR1);
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host_dawrx1 = mfspr(SPRN_DAWRX1);
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}
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hdec = time_limit - mftb();
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if (hdec < 0)
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return BOOK3S_INTERRUPT_HV_DECREMENTER;
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if (vc->tb_offset) {
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u64 new_tb = mftb() + vc->tb_offset;
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mtspr(SPRN_TBU40, new_tb);
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tb = mftb();
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if ((tb & 0xffffff) < (new_tb & 0xffffff))
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mtspr(SPRN_TBU40, new_tb + 0x1000000);
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vc->tb_offset_applied = vc->tb_offset;
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}
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if (vc->pcr)
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mtspr(SPRN_PCR, vc->pcr | PCR_MASK);
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mtspr(SPRN_DPDES, vc->dpdes);
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mtspr(SPRN_VTB, vc->vtb);
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local_paca->kvm_hstate.host_purr = mfspr(SPRN_PURR);
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local_paca->kvm_hstate.host_spurr = mfspr(SPRN_SPURR);
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mtspr(SPRN_PURR, vcpu->arch.purr);
|
||||||
|
mtspr(SPRN_SPURR, vcpu->arch.spurr);
|
||||||
|
|
||||||
|
if (dawr_enabled()) {
|
||||||
|
mtspr(SPRN_DAWR0, vcpu->arch.dawr0);
|
||||||
|
mtspr(SPRN_DAWRX0, vcpu->arch.dawrx0);
|
||||||
|
if (cpu_has_feature(CPU_FTR_DAWR1)) {
|
||||||
|
mtspr(SPRN_DAWR1, vcpu->arch.dawr1);
|
||||||
|
mtspr(SPRN_DAWRX1, vcpu->arch.dawrx1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
mtspr(SPRN_CIABR, vcpu->arch.ciabr);
|
||||||
|
mtspr(SPRN_IC, vcpu->arch.ic);
|
||||||
|
|
||||||
|
mtspr(SPRN_PSSCR, vcpu->arch.psscr | PSSCR_EC |
|
||||||
|
(local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
|
||||||
|
|
||||||
|
mtspr(SPRN_HFSCR, vcpu->arch.hfscr);
|
||||||
|
|
||||||
|
mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0);
|
||||||
|
mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1);
|
||||||
|
mtspr(SPRN_SPRG2, vcpu->arch.shregs.sprg2);
|
||||||
|
mtspr(SPRN_SPRG3, vcpu->arch.shregs.sprg3);
|
||||||
|
|
||||||
|
mtspr(SPRN_AMOR, ~0UL);
|
||||||
|
|
||||||
|
switch_mmu_to_guest_radix(kvm, vcpu, lpcr);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* P9 suppresses the HDEC exception when LPCR[HDICE] = 0,
|
||||||
|
* so set guest LPCR (with HDICE) before writing HDEC.
|
||||||
|
*/
|
||||||
|
mtspr(SPRN_HDEC, hdec);
|
||||||
|
|
||||||
|
mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0);
|
||||||
|
mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1);
|
||||||
|
|
||||||
start_timing(vcpu, &vcpu->arch.rm_entry);
|
start_timing(vcpu, &vcpu->arch.rm_entry);
|
||||||
|
|
||||||
|
|
@ -202,6 +312,69 @@ int __kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu)
|
||||||
|
|
||||||
end_timing(vcpu);
|
end_timing(vcpu);
|
||||||
|
|
||||||
|
/* Advance host PURR/SPURR by the amount used by guest */
|
||||||
|
purr = mfspr(SPRN_PURR);
|
||||||
|
spurr = mfspr(SPRN_SPURR);
|
||||||
|
mtspr(SPRN_PURR, local_paca->kvm_hstate.host_purr +
|
||||||
|
purr - vcpu->arch.purr);
|
||||||
|
mtspr(SPRN_SPURR, local_paca->kvm_hstate.host_spurr +
|
||||||
|
spurr - vcpu->arch.spurr);
|
||||||
|
vcpu->arch.purr = purr;
|
||||||
|
vcpu->arch.spurr = spurr;
|
||||||
|
|
||||||
|
vcpu->arch.ic = mfspr(SPRN_IC);
|
||||||
|
vcpu->arch.pid = mfspr(SPRN_PID);
|
||||||
|
vcpu->arch.psscr = mfspr(SPRN_PSSCR) & PSSCR_GUEST_VIS;
|
||||||
|
|
||||||
|
vcpu->arch.shregs.sprg0 = mfspr(SPRN_SPRG0);
|
||||||
|
vcpu->arch.shregs.sprg1 = mfspr(SPRN_SPRG1);
|
||||||
|
vcpu->arch.shregs.sprg2 = mfspr(SPRN_SPRG2);
|
||||||
|
vcpu->arch.shregs.sprg3 = mfspr(SPRN_SPRG3);
|
||||||
|
|
||||||
|
/* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */
|
||||||
|
mtspr(SPRN_PSSCR, host_psscr |
|
||||||
|
(local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
|
||||||
|
mtspr(SPRN_HFSCR, host_hfscr);
|
||||||
|
mtspr(SPRN_CIABR, host_ciabr);
|
||||||
|
mtspr(SPRN_DAWR0, host_dawr0);
|
||||||
|
mtspr(SPRN_DAWRX0, host_dawrx0);
|
||||||
|
if (cpu_has_feature(CPU_FTR_DAWR1)) {
|
||||||
|
mtspr(SPRN_DAWR1, host_dawr1);
|
||||||
|
mtspr(SPRN_DAWRX1, host_dawrx1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Since this is radix, do a eieio; tlbsync; ptesync sequence in
|
||||||
|
* case we interrupted the guest between a tlbie and a ptesync.
|
||||||
|
*/
|
||||||
|
asm volatile("eieio; tlbsync; ptesync");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* cp_abort is required if the processor supports local copy-paste
|
||||||
|
* to clear the copy buffer that was under control of the guest.
|
||||||
|
*/
|
||||||
|
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
||||||
|
asm volatile(PPC_CP_ABORT);
|
||||||
|
|
||||||
|
vc->dpdes = mfspr(SPRN_DPDES);
|
||||||
|
vc->vtb = mfspr(SPRN_VTB);
|
||||||
|
mtspr(SPRN_DPDES, 0);
|
||||||
|
if (vc->pcr)
|
||||||
|
mtspr(SPRN_PCR, PCR_MASK);
|
||||||
|
|
||||||
|
if (vc->tb_offset_applied) {
|
||||||
|
u64 new_tb = mftb() - vc->tb_offset_applied;
|
||||||
|
mtspr(SPRN_TBU40, new_tb);
|
||||||
|
tb = mftb();
|
||||||
|
if ((tb & 0xffffff) < (new_tb & 0xffffff))
|
||||||
|
mtspr(SPRN_TBU40, new_tb + 0x1000000);
|
||||||
|
vc->tb_offset_applied = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
mtspr(SPRN_HDEC, 0x7fffffff);
|
||||||
|
|
||||||
|
switch_mmu_to_host_radix(kvm, host_pidr);
|
||||||
|
|
||||||
return trap;
|
return trap;
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(__kvmhv_vcpu_entry_p9);
|
EXPORT_SYMBOL_GPL(kvmhv_vcpu_entry_p9);
|
||||||
|
|
|
||||||
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