irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
All the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Tested-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Barry Song <baohua.song@csr.com>
This commit is contained in:
Catalin Marinas
Родитель
aec0095653
Коммит
c0114709ed
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@ -20,7 +20,6 @@
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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@ -75,13 +74,6 @@ static DEFINE_SPINLOCK(boot_lock);
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static void __cpuinit exynos_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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@ -17,7 +17,6 @@
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/smp_scu.h>
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@ -25,11 +24,6 @@
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extern void secondary_startup(void);
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static void __cpuinit highbank_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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highbank_set_cpu_jump(cpu, secondary_startup);
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@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
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struct smp_operations highbank_smp_ops __initdata = {
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.smp_init_cpus = highbank_smp_init_cpus,
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.smp_prepare_cpus = highbank_smp_prepare_cpus,
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.smp_secondary_init = highbank_secondary_init,
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.smp_boot_secondary = highbank_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = highbank_cpu_die,
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@ -12,7 +12,6 @@
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/page.h>
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#include <asm/smp_scu.h>
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#include <asm/mach/map.h>
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@ -52,16 +51,6 @@ void imx_scu_standby_enable(void)
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writel_relaxed(val, scu_base);
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}
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static void __cpuinit imx_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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}
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static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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imx_set_cpu_jump(cpu, v7_secondary_startup);
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@ -96,7 +85,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
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struct smp_operations imx_smp_ops __initdata = {
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.smp_init_cpus = imx_smp_init_cpus,
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.smp_prepare_cpus = imx_smp_prepare_cpus,
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.smp_secondary_init = imx_secondary_init,
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.smp_boot_secondary = imx_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = imx_cpu_die,
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@ -15,7 +15,6 @@
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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@ -41,13 +40,6 @@ static inline int get_core_count(void)
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static void __cpuinit msm_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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@ -66,13 +66,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
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omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
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4, 0, 0, 0, 0, 0);
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/*
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* If any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* Synchronise with the boot thread.
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*/
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@ -11,7 +11,6 @@
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/page.h>
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#include <asm/mach/map.h>
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#include <asm/smp_plat.h>
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@ -48,13 +47,6 @@ void __init sirfsoc_map_scu(void)
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static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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@ -23,7 +23,6 @@
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/common.h>
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#include <mach/emev2.h>
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#include <asm/smp_plat.h>
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@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
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}
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static void __cpuinit emev2_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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cpu = cpu_logical_map(cpu);
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@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)
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struct smp_operations emev2_smp_ops __initdata = {
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.smp_init_cpus = emev2_smp_init_cpus,
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.smp_prepare_cpus = emev2_smp_prepare_cpus,
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.smp_secondary_init = emev2_secondary_init,
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.smp_boot_secondary = emev2_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_kill = emev2_cpu_kill,
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@ -23,7 +23,6 @@
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/common.h>
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#include <mach/r8a7779.h>
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#include <asm/smp_plat.h>
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@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
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}
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static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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struct r8a7779_pm_ch *ch = NULL;
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@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)
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struct smp_operations r8a7779_smp_ops __initdata = {
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.smp_init_cpus = r8a7779_smp_init_cpus,
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.smp_prepare_cpus = r8a7779_smp_prepare_cpus,
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.smp_secondary_init = r8a7779_secondary_init,
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.smp_boot_secondary = r8a7779_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_kill = r8a7779_cpu_kill,
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@ -23,7 +23,6 @@
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/common.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)
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return scu_get_core_count(scu_base);
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}
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static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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cpu = cpu_logical_map(cpu);
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@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)
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struct smp_operations sh73a0_smp_ops __initdata = {
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.smp_init_cpus = sh73a0_smp_init_cpus,
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.smp_prepare_cpus = sh73a0_smp_prepare_cpus,
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.smp_secondary_init = sh73a0_secondary_init,
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.smp_boot_secondary = sh73a0_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_kill = sh73a0_cpu_kill,
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@ -22,7 +22,6 @@
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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@ -33,16 +32,6 @@
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extern void __iomem *sys_manager_base_addr;
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extern void __iomem *rst_manager_base_addr;
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static void __cpuinit socfpga_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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}
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static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
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@ -109,7 +98,6 @@ static void socfpga_cpu_die(unsigned int cpu)
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struct smp_operations socfpga_smp_ops __initdata = {
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.smp_init_cpus = socfpga_smp_init_cpus,
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.smp_prepare_cpus = socfpga_smp_prepare_cpus,
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.smp_secondary_init = socfpga_secondary_init,
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.smp_boot_secondary = socfpga_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = socfpga_cpu_die,
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@ -15,7 +15,6 @@
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#include <linux/jiffies.h>
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#include <linux/io.h>
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#include <linux/smp.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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#include <mach/spear.h>
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@ -27,13 +26,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
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static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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@ -18,7 +18,6 @@
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/clk/tegra.h>
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#include <asm/cacheflush.h>
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@ -44,13 +43,6 @@ static cpumask_t tegra_cpu_init_mask;
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static void __cpuinit tegra_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
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}
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@ -16,7 +16,6 @@
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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@ -57,13 +56,6 @@ static DEFINE_SPINLOCK(boot_lock);
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static void __cpuinit ux500_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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@ -21,8 +21,6 @@
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#include <linux/smp.h>
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#include <linux/of.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/psci.h>
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#include <asm/smp_plat.h>
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@ -45,14 +43,8 @@ static int __cpuinit virt_boot_secondary(unsigned int cpu,
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return -ENODEV;
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}
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static void __cpuinit virt_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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struct smp_operations __initdata virt_smp_ops = {
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.smp_init_cpus = virt_smp_init_cpus,
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.smp_prepare_cpus = virt_smp_prepare_cpus,
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.smp_secondary_init = virt_secondary_init,
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.smp_boot_secondary = virt_boot_secondary,
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};
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@ -14,7 +14,6 @@
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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@ -36,13 +35,6 @@ static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit versatile_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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@ -28,6 +28,7 @@
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/smp.h>
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#include <linux/cpu.h>
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#include <linux/cpu_pm.h>
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#include <linux/cpumask.h>
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#include <linux/io.h>
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@ -699,6 +700,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
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return 0;
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}
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#ifdef CONFIG_SMP
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static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
|
||||
unsigned long action, void *hcpu)
|
||||
{
|
||||
if (action == CPU_STARTING)
|
||||
gic_cpu_init(&gic_data[0]);
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Notifier for enabling the GIC CPU interface. Set an arbitrarily high
|
||||
* priority because the GIC needs to be up before the ARM generic timers.
|
||||
*/
|
||||
static struct notifier_block __cpuinitdata gic_cpu_notifier = {
|
||||
.notifier_call = gic_secondary_init,
|
||||
.priority = 100,
|
||||
};
|
||||
#endif
|
||||
|
||||
const struct irq_domain_ops gic_irq_domain_ops = {
|
||||
.map = gic_irq_domain_map,
|
||||
.xlate = gic_irq_domain_xlate,
|
||||
|
|
@ -789,6 +809,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|||
|
||||
#ifdef CONFIG_SMP
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
register_cpu_notifier(&gic_cpu_notifier);
|
||||
#endif
|
||||
|
||||
set_handle_irq(gic_handle_irq);
|
||||
|
|
@ -799,13 +820,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|||
gic_pm_init(gic);
|
||||
}
|
||||
|
||||
void __cpuinit gic_secondary_init(unsigned int gic_nr)
|
||||
{
|
||||
BUG_ON(gic_nr >= MAX_GIC_NR);
|
||||
|
||||
gic_cpu_init(&gic_data[gic_nr]);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static int gic_cnt __initdata = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -65,7 +65,6 @@ extern struct irq_chip gic_arch_extn;
|
|||
|
||||
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
|
||||
u32 offset, struct device_node *);
|
||||
void gic_secondary_init(unsigned int);
|
||||
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
|
||||
|
||||
static inline void gic_init(unsigned int nr, int start,
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче