arm64: mte: system register definitions
Add Memory Tagging Extension system register definitions together with the relevant bitfields. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Co-developed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org>
This commit is contained in:
Vincenzo Frascino
Catalin Marinas
Родитель
f75aef392f
Коммит
c058b1c4a5
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@ -12,6 +12,7 @@
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#include <asm/types.h>
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/* Hyp Configuration Register (HCR) bits */
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#define HCR_ATA (UL(1) << 56)
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#define HCR_FWB (UL(1) << 46)
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#define HCR_API (UL(1) << 41)
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#define HCR_APK (UL(1) << 40)
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@ -91,10 +91,12 @@
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#define PSTATE_PAN pstate_field(0, 4)
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#define PSTATE_UAO pstate_field(0, 3)
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#define PSTATE_SSBS pstate_field(3, 1)
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#define PSTATE_TCO pstate_field(3, 4)
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#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
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#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
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#define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
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#define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
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#define __SYS_BARRIER_INSN(CRm, op2, Rt) \
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__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
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@ -181,6 +183,8 @@
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#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
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#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
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#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
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#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
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#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
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#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
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@ -218,6 +222,8 @@
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#define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
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#define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
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#define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
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#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
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#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
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#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
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#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
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@ -368,6 +374,7 @@
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#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
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#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
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#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
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#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
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#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
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@ -460,6 +467,7 @@
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#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
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#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
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#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
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#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
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#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
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#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
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@ -516,6 +524,7 @@
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#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
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#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
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#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
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#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
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#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
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#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
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#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
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@ -531,6 +540,15 @@
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/* Common SCTLR_ELx flags. */
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#define SCTLR_ELx_DSSBS (BIT(44))
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#define SCTLR_ELx_ATA (BIT(43))
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#define SCTLR_ELx_TCF_SHIFT 40
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#define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT)
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#define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT)
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#define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT)
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#define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT)
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#define SCTLR_ELx_ITFSB (BIT(37))
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#define SCTLR_ELx_ENIA (BIT(31))
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#define SCTLR_ELx_ENIB (BIT(30))
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#define SCTLR_ELx_ENDA (BIT(27))
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@ -559,6 +577,14 @@
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#endif
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/* SCTLR_EL1 specific flags. */
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#define SCTLR_EL1_ATA0 (BIT(42))
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#define SCTLR_EL1_TCF0_SHIFT 38
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#define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
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#define SCTLR_EL1_BT1 (BIT(36))
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#define SCTLR_EL1_BT0 (BIT(35))
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#define SCTLR_EL1_UCI (BIT(26))
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@ -595,6 +621,7 @@
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#define MAIR_ATTR_DEVICE_GRE UL(0x0c)
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#define MAIR_ATTR_NORMAL_NC UL(0x44)
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#define MAIR_ATTR_NORMAL_WT UL(0xbb)
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#define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
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#define MAIR_ATTR_NORMAL UL(0xff)
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#define MAIR_ATTR_MASK UL(0xff)
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@ -686,6 +713,10 @@
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#define ID_AA64PFR1_SSBS_PSTATE_INSNS 2
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#define ID_AA64PFR1_BT_BTI 0x1
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#define ID_AA64PFR1_MTE_NI 0x0
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#define ID_AA64PFR1_MTE_EL0 0x1
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#define ID_AA64PFR1_MTE 0x2
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/* id_aa64zfr0 */
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#define ID_AA64ZFR0_F64MM_SHIFT 56
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#define ID_AA64ZFR0_F32MM_SHIFT 52
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@ -920,6 +951,28 @@
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#define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
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#define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
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/* TCR EL1 Bit Definitions */
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#define SYS_TCR_EL1_TCMA1 (BIT(58))
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#define SYS_TCR_EL1_TCMA0 (BIT(57))
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/* GCR_EL1 Definitions */
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#define SYS_GCR_EL1_RRND (BIT(16))
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#define SYS_GCR_EL1_EXCL_MASK 0xffffUL
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/* RGSR_EL1 Definitions */
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#define SYS_RGSR_EL1_TAG_MASK 0xfUL
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#define SYS_RGSR_EL1_SEED_SHIFT 8
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#define SYS_RGSR_EL1_SEED_MASK 0xffffUL
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/* GMID_EL1 field definitions */
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#define SYS_GMID_EL1_BS_SHIFT 0
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#define SYS_GMID_EL1_BS_SIZE 4
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/* TFSR{,E0}_EL1 bit definitions */
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#define SYS_TFSR_EL1_TF0_SHIFT 0
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#define SYS_TFSR_EL1_TF1_SHIFT 1
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#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
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#define SYS_TFSR_EL1_TF1 (UK(2) << SYS_TFSR_EL1_TF1_SHIFT)
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/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
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#define SYS_MPIDR_SAFE_VAL (BIT(31))
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@ -51,6 +51,7 @@
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#define PSR_PAN_BIT 0x00400000
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#define PSR_UAO_BIT 0x00800000
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#define PSR_DIT_BIT 0x01000000
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#define PSR_TCO_BIT 0x02000000
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#define PSR_V_BIT 0x10000000
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#define PSR_C_BIT 0x20000000
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#define PSR_Z_BIT 0x40000000
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@ -1793,7 +1793,7 @@ void syscall_trace_exit(struct pt_regs *regs)
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* We also reserve IL for the kernel; SS is handled dynamically.
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*/
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#define SPSR_EL1_AARCH64_RES0_BITS \
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(GENMASK_ULL(63, 32) | GENMASK_ULL(27, 25) | GENMASK_ULL(23, 22) | \
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(GENMASK_ULL(63, 32) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | \
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GENMASK_ULL(20, 13) | GENMASK_ULL(5, 5))
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#define SPSR_EL1_AARCH32_RES0_BITS \
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(GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20))
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