[media] omap3isp: lane shifter support
To use the lane shifter, set different pixel formats at each end of the link at the CCDC input. Signed-off-by: Michael Jones <michael.jones@matrix-vision.de> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Michael Jones
Mauro Carvalho Chehab
Родитель
5782f97b55
Коммит
c09af044db
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@ -286,7 +286,8 @@ static void isp_power_settings(struct isp_device *isp, int idle)
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*/
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void omap3isp_configure_bridge(struct isp_device *isp,
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enum ccdc_input_entity input,
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const struct isp_parallel_platform_data *pdata)
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const struct isp_parallel_platform_data *pdata,
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unsigned int shift)
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{
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u32 ispctrl_val;
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@ -299,9 +300,9 @@ void omap3isp_configure_bridge(struct isp_device *isp,
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switch (input) {
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case CCDC_INPUT_PARALLEL:
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ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
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ispctrl_val |= pdata->data_lane_shift << ISPCTRL_SHIFT_SHIFT;
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ispctrl_val |= pdata->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
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ispctrl_val |= pdata->bridge << ISPCTRL_PAR_BRIDGE_SHIFT;
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shift += pdata->data_lane_shift * 2;
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break;
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case CCDC_INPUT_CSI2A:
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@ -320,6 +321,8 @@ void omap3isp_configure_bridge(struct isp_device *isp,
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return;
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}
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ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
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ispctrl_val &= ~ISPCTRL_SYNC_DETECT_MASK;
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ispctrl_val |= ISPCTRL_SYNC_DETECT_VSRISE;
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@ -132,7 +132,6 @@ struct isp_reg {
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/**
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* struct isp_parallel_platform_data - Parallel interface platform data
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* @width: Parallel bus width in bits (8, 10, 11 or 12)
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* @data_lane_shift: Data lane shifter
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* 0 - CAMEXT[13:0] -> CAM[13:0]
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* 1 - CAMEXT[13:2] -> CAM[11:0]
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@ -146,7 +145,6 @@ struct isp_reg {
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* ISPCTRL_PAR_BRIDGE_BENDIAN - Big endian
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*/
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struct isp_parallel_platform_data {
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unsigned int width;
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unsigned int data_lane_shift:2;
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unsigned int clk_pol:1;
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unsigned int bridge:4;
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@ -312,7 +310,8 @@ int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
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enum isp_pipeline_stream_state state);
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void omap3isp_configure_bridge(struct isp_device *isp,
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enum ccdc_input_entity input,
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const struct isp_parallel_platform_data *pdata);
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const struct isp_parallel_platform_data *pdata,
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unsigned int shift);
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#define ISP_XCLK_NONE 0
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#define ISP_XCLK_A 1
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@ -1116,21 +1116,38 @@ static void ccdc_configure(struct isp_ccdc_device *ccdc)
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struct isp_parallel_platform_data *pdata = NULL;
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struct v4l2_subdev *sensor;
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struct v4l2_mbus_framefmt *format;
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const struct isp_format_info *fmt_info;
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struct v4l2_subdev_format fmt_src;
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unsigned int depth_out;
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unsigned int depth_in = 0;
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struct media_pad *pad;
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unsigned long flags;
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unsigned int shift;
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u32 syn_mode;
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u32 ccdc_pattern;
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if (ccdc->input == CCDC_INPUT_PARALLEL) {
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pad = media_entity_remote_source(&ccdc->pads[CCDC_PAD_SINK]);
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sensor = media_entity_to_v4l2_subdev(pad->entity);
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pad = media_entity_remote_source(&ccdc->pads[CCDC_PAD_SINK]);
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sensor = media_entity_to_v4l2_subdev(pad->entity);
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if (ccdc->input == CCDC_INPUT_PARALLEL)
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pdata = &((struct isp_v4l2_subdevs_group *)sensor->host_priv)
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->bus.parallel;
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/* Compute shift value for lane shifter to configure the bridge. */
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fmt_src.pad = pad->index;
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fmt_src.which = V4L2_SUBDEV_FORMAT_ACTIVE;
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if (!v4l2_subdev_call(sensor, pad, get_fmt, NULL, &fmt_src)) {
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fmt_info = omap3isp_video_format_info(fmt_src.format.code);
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depth_in = fmt_info->bpp;
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}
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omap3isp_configure_bridge(isp, ccdc->input, pdata);
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fmt_info = omap3isp_video_format_info
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(isp->isp_ccdc.formats[CCDC_PAD_SINK].code);
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depth_out = fmt_info->bpp;
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ccdc->syncif.datsz = pdata ? pdata->width : 10;
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shift = depth_in - depth_out;
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omap3isp_configure_bridge(isp, ccdc->input, pdata, shift);
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ccdc->syncif.datsz = depth_out;
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ccdc_config_sync_if(ccdc, &ccdc->syncif);
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/* CCDC_PAD_SINK */
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@ -47,41 +47,59 @@
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static struct isp_format_info formats[] = {
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{ V4L2_MBUS_FMT_Y8_1X8, V4L2_MBUS_FMT_Y8_1X8,
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V4L2_MBUS_FMT_Y8_1X8, V4L2_PIX_FMT_GREY, 8, },
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V4L2_MBUS_FMT_Y8_1X8, V4L2_MBUS_FMT_Y8_1X8,
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V4L2_PIX_FMT_GREY, 8, },
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{ V4L2_MBUS_FMT_Y10_1X10, V4L2_MBUS_FMT_Y10_1X10,
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V4L2_MBUS_FMT_Y10_1X10, V4L2_PIX_FMT_Y10, 10, },
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V4L2_MBUS_FMT_Y10_1X10, V4L2_MBUS_FMT_Y8_1X8,
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V4L2_PIX_FMT_Y10, 10, },
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{ V4L2_MBUS_FMT_Y12_1X12, V4L2_MBUS_FMT_Y10_1X10,
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V4L2_MBUS_FMT_Y12_1X12, V4L2_PIX_FMT_Y12, 12, },
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V4L2_MBUS_FMT_Y12_1X12, V4L2_MBUS_FMT_Y8_1X8,
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V4L2_PIX_FMT_Y12, 12, },
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{ V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_MBUS_FMT_SBGGR8_1X8,
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V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_PIX_FMT_SBGGR8, 8, },
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V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_MBUS_FMT_SBGGR8_1X8,
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V4L2_PIX_FMT_SBGGR8, 8, },
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{ V4L2_MBUS_FMT_SGBRG8_1X8, V4L2_MBUS_FMT_SGBRG8_1X8,
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V4L2_MBUS_FMT_SGBRG8_1X8, V4L2_PIX_FMT_SGBRG8, 8, },
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V4L2_MBUS_FMT_SGBRG8_1X8, V4L2_MBUS_FMT_SGBRG8_1X8,
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V4L2_PIX_FMT_SGBRG8, 8, },
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{ V4L2_MBUS_FMT_SGRBG8_1X8, V4L2_MBUS_FMT_SGRBG8_1X8,
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V4L2_MBUS_FMT_SGRBG8_1X8, V4L2_PIX_FMT_SGRBG8, 8, },
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V4L2_MBUS_FMT_SGRBG8_1X8, V4L2_MBUS_FMT_SGRBG8_1X8,
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V4L2_PIX_FMT_SGRBG8, 8, },
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{ V4L2_MBUS_FMT_SRGGB8_1X8, V4L2_MBUS_FMT_SRGGB8_1X8,
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V4L2_MBUS_FMT_SRGGB8_1X8, V4L2_PIX_FMT_SRGGB8, 8, },
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V4L2_MBUS_FMT_SRGGB8_1X8, V4L2_MBUS_FMT_SRGGB8_1X8,
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V4L2_PIX_FMT_SRGGB8, 8, },
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{ V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8, V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8,
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V4L2_MBUS_FMT_SGRBG10_1X10, V4L2_PIX_FMT_SGRBG10DPCM8, 8, },
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V4L2_MBUS_FMT_SGRBG10_1X10, 0,
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V4L2_PIX_FMT_SGRBG10DPCM8, 8, },
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{ V4L2_MBUS_FMT_SBGGR10_1X10, V4L2_MBUS_FMT_SBGGR10_1X10,
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V4L2_MBUS_FMT_SBGGR10_1X10, V4L2_PIX_FMT_SBGGR10, 10, },
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V4L2_MBUS_FMT_SBGGR10_1X10, V4L2_MBUS_FMT_SBGGR8_1X8,
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V4L2_PIX_FMT_SBGGR10, 10, },
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{ V4L2_MBUS_FMT_SGBRG10_1X10, V4L2_MBUS_FMT_SGBRG10_1X10,
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V4L2_MBUS_FMT_SGBRG10_1X10, V4L2_PIX_FMT_SGBRG10, 10, },
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V4L2_MBUS_FMT_SGBRG10_1X10, V4L2_MBUS_FMT_SGBRG8_1X8,
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V4L2_PIX_FMT_SGBRG10, 10, },
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{ V4L2_MBUS_FMT_SGRBG10_1X10, V4L2_MBUS_FMT_SGRBG10_1X10,
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V4L2_MBUS_FMT_SGRBG10_1X10, V4L2_PIX_FMT_SGRBG10, 10, },
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V4L2_MBUS_FMT_SGRBG10_1X10, V4L2_MBUS_FMT_SGRBG8_1X8,
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V4L2_PIX_FMT_SGRBG10, 10, },
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{ V4L2_MBUS_FMT_SRGGB10_1X10, V4L2_MBUS_FMT_SRGGB10_1X10,
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V4L2_MBUS_FMT_SRGGB10_1X10, V4L2_PIX_FMT_SRGGB10, 10, },
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V4L2_MBUS_FMT_SRGGB10_1X10, V4L2_MBUS_FMT_SRGGB8_1X8,
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V4L2_PIX_FMT_SRGGB10, 10, },
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{ V4L2_MBUS_FMT_SBGGR12_1X12, V4L2_MBUS_FMT_SBGGR10_1X10,
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V4L2_MBUS_FMT_SBGGR12_1X12, V4L2_PIX_FMT_SBGGR12, 12, },
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V4L2_MBUS_FMT_SBGGR12_1X12, V4L2_MBUS_FMT_SBGGR8_1X8,
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V4L2_PIX_FMT_SBGGR12, 12, },
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{ V4L2_MBUS_FMT_SGBRG12_1X12, V4L2_MBUS_FMT_SGBRG10_1X10,
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V4L2_MBUS_FMT_SGBRG12_1X12, V4L2_PIX_FMT_SGBRG12, 12, },
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V4L2_MBUS_FMT_SGBRG12_1X12, V4L2_MBUS_FMT_SGBRG8_1X8,
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V4L2_PIX_FMT_SGBRG12, 12, },
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{ V4L2_MBUS_FMT_SGRBG12_1X12, V4L2_MBUS_FMT_SGRBG10_1X10,
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V4L2_MBUS_FMT_SGRBG12_1X12, V4L2_PIX_FMT_SGRBG12, 12, },
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V4L2_MBUS_FMT_SGRBG12_1X12, V4L2_MBUS_FMT_SGRBG8_1X8,
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V4L2_PIX_FMT_SGRBG12, 12, },
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{ V4L2_MBUS_FMT_SRGGB12_1X12, V4L2_MBUS_FMT_SRGGB10_1X10,
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V4L2_MBUS_FMT_SRGGB12_1X12, V4L2_PIX_FMT_SRGGB12, 12, },
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V4L2_MBUS_FMT_SRGGB12_1X12, V4L2_MBUS_FMT_SRGGB8_1X8,
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V4L2_PIX_FMT_SRGGB12, 12, },
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{ V4L2_MBUS_FMT_UYVY8_1X16, V4L2_MBUS_FMT_UYVY8_1X16,
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V4L2_MBUS_FMT_UYVY8_1X16, V4L2_PIX_FMT_UYVY, 16, },
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V4L2_MBUS_FMT_UYVY8_1X16, 0,
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V4L2_PIX_FMT_UYVY, 16, },
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{ V4L2_MBUS_FMT_YUYV8_1X16, V4L2_MBUS_FMT_YUYV8_1X16,
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V4L2_MBUS_FMT_YUYV8_1X16, V4L2_PIX_FMT_YUYV, 16, },
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V4L2_MBUS_FMT_YUYV8_1X16, 0,
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V4L2_PIX_FMT_YUYV, 16, },
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};
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const struct isp_format_info *
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@ -97,6 +115,37 @@ omap3isp_video_format_info(enum v4l2_mbus_pixelcode code)
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return NULL;
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}
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/*
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* Decide whether desired output pixel code can be obtained with
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* the lane shifter by shifting the input pixel code.
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* @in: input pixelcode to shifter
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* @out: output pixelcode from shifter
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* @additional_shift: # of bits the sensor's LSB is offset from CAMEXT[0]
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*
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* return true if the combination is possible
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* return false otherwise
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*/
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static bool isp_video_is_shiftable(enum v4l2_mbus_pixelcode in,
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enum v4l2_mbus_pixelcode out,
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unsigned int additional_shift)
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{
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const struct isp_format_info *in_info, *out_info;
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if (in == out)
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return true;
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in_info = omap3isp_video_format_info(in);
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out_info = omap3isp_video_format_info(out);
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if ((in_info->flavor == 0) || (out_info->flavor == 0))
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return false;
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if (in_info->flavor != out_info->flavor)
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return false;
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return in_info->bpp - out_info->bpp + additional_shift <= 6;
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}
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/*
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* isp_video_mbus_to_pix - Convert v4l2_mbus_framefmt to v4l2_pix_format
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* @video: ISP video instance
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@ -247,6 +296,7 @@ static int isp_video_validate_pipeline(struct isp_pipeline *pipe)
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return -EPIPE;
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while (1) {
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unsigned int shifter_link;
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/* Retrieve the sink format */
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pad = &subdev->entity.pads[0];
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if (!(pad->flags & MEDIA_PAD_FL_SINK))
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@ -275,6 +325,10 @@ static int isp_video_validate_pipeline(struct isp_pipeline *pipe)
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return -ENOSPC;
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}
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/* If sink pad is on CCDC, the link has the lane shifter
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* in the middle of it. */
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shifter_link = subdev == &isp->isp_ccdc.subdev;
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/* Retrieve the source format */
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pad = media_entity_remote_source(pad);
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if (pad == NULL ||
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@ -290,10 +344,24 @@ static int isp_video_validate_pipeline(struct isp_pipeline *pipe)
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return -EPIPE;
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/* Check if the two ends match */
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if (fmt_source.format.code != fmt_sink.format.code ||
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fmt_source.format.width != fmt_sink.format.width ||
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if (fmt_source.format.width != fmt_sink.format.width ||
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fmt_source.format.height != fmt_sink.format.height)
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return -EPIPE;
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if (shifter_link) {
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unsigned int parallel_shift = 0;
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if (isp->isp_ccdc.input == CCDC_INPUT_PARALLEL) {
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struct isp_parallel_platform_data *pdata =
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&((struct isp_v4l2_subdevs_group *)
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subdev->host_priv)->bus.parallel;
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parallel_shift = pdata->data_lane_shift * 2;
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}
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if (!isp_video_is_shiftable(fmt_source.format.code,
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fmt_sink.format.code,
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parallel_shift))
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return -EPIPE;
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} else if (fmt_source.format.code != fmt_sink.format.code)
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return -EPIPE;
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}
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return 0;
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@ -49,6 +49,8 @@ struct v4l2_pix_format;
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* bits. Identical to @code if the format is 10 bits wide or less.
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* @uncompressed: V4L2 media bus format code for the corresponding uncompressed
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* format. Identical to @code if the format is not DPCM compressed.
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* @flavor: V4L2 media bus format code for the same pixel layout but
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* shifted to be 8 bits per pixel. =0 if format is not shiftable.
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* @pixelformat: V4L2 pixel format FCC identifier
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* @bpp: Bits per pixel
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*/
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@ -56,6 +58,7 @@ struct isp_format_info {
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enum v4l2_mbus_pixelcode code;
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enum v4l2_mbus_pixelcode truncated;
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enum v4l2_mbus_pixelcode uncompressed;
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enum v4l2_mbus_pixelcode flavor;
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u32 pixelformat;
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unsigned int bpp;
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};
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