drm/nvc0/ibus: initial implementation of subdev
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
Родитель
2f951a5db5
Коммит
c0abf5c9fa
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@ -76,6 +76,7 @@ nouveau-y += core/subdev/gpio/nvd0.o
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nouveau-y += core/subdev/i2c/base.o
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nouveau-y += core/subdev/i2c/aux.o
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nouveau-y += core/subdev/i2c/bit.o
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nouveau-y += core/subdev/ibus/nvc0.o
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nouveau-y += core/subdev/ibus/nve0.o
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nouveau-y += core/subdev/instmem/base.o
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nouveau-y += core/subdev/instmem/nv04.o
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@ -28,6 +28,7 @@ nouveau_ibus(void *obj)
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#define _nouveau_ibus_init _nouveau_subdev_init
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#define _nouveau_ibus_fini _nouveau_subdev_fini
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extern struct nouveau_oclass nvc0_ibus_oclass;
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extern struct nouveau_oclass nve0_ibus_oclass;
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#endif
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@ -34,6 +34,7 @@
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#include <subdev/timer.h>
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#include <subdev/fb.h>
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#include <subdev/ltcg.h>
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#include <subdev/ibus.h>
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#include <subdev/instmem.h>
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#include <subdev/vm.h>
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#include <subdev/bar.h>
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@ -65,6 +66,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
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@ -92,6 +94,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
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@ -119,6 +122,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
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@ -146,6 +150,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
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@ -173,6 +178,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
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@ -200,6 +206,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
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@ -227,6 +234,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
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@ -254,6 +262,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
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@ -0,0 +1,123 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <subdev/ibus.h>
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struct nvc0_ibus_priv {
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struct nouveau_ibus base;
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};
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static void
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nvc0_ibus_intr_hub(struct nvc0_ibus_priv *priv, int i)
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{
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u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0400));
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u32 data = nv_rd32(priv, 0x122124 + (i * 0x0400));
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u32 stat = nv_rd32(priv, 0x122128 + (i * 0x0400));
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nv_error(priv, "HUB%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
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nv_mask(priv, 0x122128 + (i * 0x0400), 0x00000200, 0x00000000);
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}
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static void
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nvc0_ibus_intr_rop(struct nvc0_ibus_priv *priv, int i)
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{
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u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0400));
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u32 data = nv_rd32(priv, 0x124124 + (i * 0x0400));
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u32 stat = nv_rd32(priv, 0x124128 + (i * 0x0400));
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nv_error(priv, "ROP%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
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nv_mask(priv, 0x124128 + (i * 0x0400), 0x00000200, 0x00000000);
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}
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static void
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nvc0_ibus_intr_gpc(struct nvc0_ibus_priv *priv, int i)
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{
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u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0400));
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u32 data = nv_rd32(priv, 0x128124 + (i * 0x0400));
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u32 stat = nv_rd32(priv, 0x128128 + (i * 0x0400));
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nv_error(priv, "GPC%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
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nv_mask(priv, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000);
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}
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static void
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nvc0_ibus_intr(struct nouveau_subdev *subdev)
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{
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struct nvc0_ibus_priv *priv = (void *)subdev;
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u32 intr0 = nv_rd32(priv, 0x121c58);
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u32 intr1 = nv_rd32(priv, 0x121c5c);
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u32 hubnr = nv_rd32(priv, 0x121c70);
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u32 ropnr = nv_rd32(priv, 0x121c74);
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u32 gpcnr = nv_rd32(priv, 0x121c78);
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u32 i;
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for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) {
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u32 stat = 0x00000100 << i;
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if (intr0 & stat) {
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nvc0_ibus_intr_hub(priv, i);
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intr0 &= ~stat;
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}
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}
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for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) {
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u32 stat = 0x00010000 << i;
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if (intr0 & stat) {
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nvc0_ibus_intr_rop(priv, i);
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intr0 &= ~stat;
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}
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}
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for (i = 0; intr1 && i < gpcnr; i++) {
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u32 stat = 0x00000001 << i;
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if (intr1 & stat) {
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nvc0_ibus_intr_gpc(priv, i);
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intr1 &= ~stat;
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}
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}
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}
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static int
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nvc0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nvc0_ibus_priv *priv;
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int ret;
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ret = nouveau_ibus_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->intr = nvc0_ibus_intr;
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return 0;
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}
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struct nouveau_oclass
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nvc0_ibus_oclass = {
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.handle = NV_SUBDEV(IBUS, 0xc0),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nvc0_ibus_ctor,
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.dtor = _nouveau_ibus_dtor,
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.init = _nouveau_ibus_init,
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.fini = _nouveau_ibus_fini,
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},
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};
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