ath9k: remove superfluous check on changing channel
When we try to change the channel in ath9k its because either the configuration indicates we *have* changed channels or HT configuration has changed. In both cases we want to do a reset. Either way mac80211 will inform us when we want to actually change the channel so trust those calls. Although in the patch it may seem as I am doing more code changes I am not, all I am doing is removing the initial branch conditional and shifting the code to the left. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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c0d7c7af0a
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@ -268,61 +268,56 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
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if (sc->sc_flags & SC_OP_INVALID)
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if (sc->sc_flags & SC_OP_INVALID)
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return -EIO;
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return -EIO;
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if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
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/*
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hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
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* This is only performed if the channel settings have
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(sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
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* actually changed.
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(sc->sc_flags & SC_OP_FULL_RESET)) {
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*
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/*
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* To switch channels clear any pending DMA operations;
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* This is only performed if the channel settings have
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* wait long enough for the RX fifo to drain, reset the
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* actually changed.
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* hardware at the new frequency, and then re-enable
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*
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* the relevant bits of the h/w.
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* To switch channels clear any pending DMA operations;
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*/
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* wait long enough for the RX fifo to drain, reset the
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ath9k_hw_set_interrupts(ah, 0);
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* hardware at the new frequency, and then re-enable
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ath_draintxq(sc, false);
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* the relevant bits of the h/w.
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stopped = ath_stoprecv(sc);
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*/
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ath9k_hw_set_interrupts(ah, 0);
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ath_draintxq(sc, false);
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stopped = ath_stoprecv(sc);
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/* XXX: do not flush receive queue here. We don't want
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/* XXX: do not flush receive queue here. We don't want
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* to flush data frames already in queue because of
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* to flush data frames already in queue because of
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* changing channel. */
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* changing channel. */
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if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
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if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
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fastcc = false;
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fastcc = false;
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DPRINTF(sc, ATH_DBG_CONFIG,
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DPRINTF(sc, ATH_DBG_CONFIG,
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"(%u MHz) -> (%u MHz), chanwidth: %d\n",
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"(%u MHz) -> (%u MHz), chanwidth: %d\n",
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sc->sc_ah->ah_curchan->channel,
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sc->sc_ah->ah_curchan->channel,
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channel->center_freq, sc->tx_chan_width);
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channel->center_freq, sc->tx_chan_width);
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spin_lock_bh(&sc->sc_resetlock);
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spin_lock_bh(&sc->sc_resetlock);
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r = ath9k_hw_reset(ah, hchan, fastcc);
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r = ath9k_hw_reset(ah, hchan, fastcc);
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if (r) {
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if (r) {
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DPRINTF(sc, ATH_DBG_FATAL,
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DPRINTF(sc, ATH_DBG_FATAL,
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"Unable to reset channel (%u Mhz) "
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"Unable to reset channel (%u Mhz) "
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"reset status %u\n",
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"reset status %u\n",
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channel->center_freq, r);
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channel->center_freq, r);
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spin_unlock_bh(&sc->sc_resetlock);
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return r;
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}
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spin_unlock_bh(&sc->sc_resetlock);
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spin_unlock_bh(&sc->sc_resetlock);
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return r;
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sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
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sc->sc_flags &= ~SC_OP_FULL_RESET;
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if (ath_startrecv(sc) != 0) {
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DPRINTF(sc, ATH_DBG_FATAL,
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"Unable to restart recv logic\n");
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return -EIO;
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}
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ath_cache_conf_rate(sc, &hw->conf);
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ath_update_txpow(sc);
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ath9k_hw_set_interrupts(ah, sc->sc_imask);
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}
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}
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spin_unlock_bh(&sc->sc_resetlock);
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sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
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sc->sc_flags &= ~SC_OP_FULL_RESET;
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if (ath_startrecv(sc) != 0) {
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DPRINTF(sc, ATH_DBG_FATAL,
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"Unable to restart recv logic\n");
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return -EIO;
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}
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ath_cache_conf_rate(sc, &hw->conf);
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ath_update_txpow(sc);
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ath9k_hw_set_interrupts(ah, sc->sc_imask);
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return 0;
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return 0;
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}
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}
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