ath9k: remove superfluous check on changing channel

When we try to change the channel in ath9k its because
either the configuration indicates we *have* changed
channels or HT configuration has changed. In both cases
we want to do a reset. Either way mac80211 will inform us
when we want to actually change the channel so trust those
calls.

Although in the patch it may seem as I am doing more code
changes I am not, all I am doing is removing the initial
branch conditional and shifting the code to the left.

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez 2008-12-23 15:58:50 -08:00 коммит произвёл John W. Linville
Родитель 0de57d991b
Коммит c0d7c7af0a
1 изменённых файлов: 43 добавлений и 48 удалений

Просмотреть файл

@ -268,61 +268,56 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
if (sc->sc_flags & SC_OP_INVALID) if (sc->sc_flags & SC_OP_INVALID)
return -EIO; return -EIO;
if (hchan->channel != sc->sc_ah->ah_curchan->channel || /*
hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags || * This is only performed if the channel settings have
(sc->sc_flags & SC_OP_CHAINMASK_UPDATE) || * actually changed.
(sc->sc_flags & SC_OP_FULL_RESET)) { *
/* * To switch channels clear any pending DMA operations;
* This is only performed if the channel settings have * wait long enough for the RX fifo to drain, reset the
* actually changed. * hardware at the new frequency, and then re-enable
* * the relevant bits of the h/w.
* To switch channels clear any pending DMA operations; */
* wait long enough for the RX fifo to drain, reset the ath9k_hw_set_interrupts(ah, 0);
* hardware at the new frequency, and then re-enable ath_draintxq(sc, false);
* the relevant bits of the h/w. stopped = ath_stoprecv(sc);
*/
ath9k_hw_set_interrupts(ah, 0);
ath_draintxq(sc, false);
stopped = ath_stoprecv(sc);
/* XXX: do not flush receive queue here. We don't want /* XXX: do not flush receive queue here. We don't want
* to flush data frames already in queue because of * to flush data frames already in queue because of
* changing channel. */ * changing channel. */
if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
fastcc = false; fastcc = false;
DPRINTF(sc, ATH_DBG_CONFIG, DPRINTF(sc, ATH_DBG_CONFIG,
"(%u MHz) -> (%u MHz), chanwidth: %d\n", "(%u MHz) -> (%u MHz), chanwidth: %d\n",
sc->sc_ah->ah_curchan->channel, sc->sc_ah->ah_curchan->channel,
channel->center_freq, sc->tx_chan_width); channel->center_freq, sc->tx_chan_width);
spin_lock_bh(&sc->sc_resetlock); spin_lock_bh(&sc->sc_resetlock);
r = ath9k_hw_reset(ah, hchan, fastcc); r = ath9k_hw_reset(ah, hchan, fastcc);
if (r) { if (r) {
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"Unable to reset channel (%u Mhz) " "Unable to reset channel (%u Mhz) "
"reset status %u\n", "reset status %u\n",
channel->center_freq, r); channel->center_freq, r);
spin_unlock_bh(&sc->sc_resetlock);
return r;
}
spin_unlock_bh(&sc->sc_resetlock); spin_unlock_bh(&sc->sc_resetlock);
return r;
sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
sc->sc_flags &= ~SC_OP_FULL_RESET;
if (ath_startrecv(sc) != 0) {
DPRINTF(sc, ATH_DBG_FATAL,
"Unable to restart recv logic\n");
return -EIO;
}
ath_cache_conf_rate(sc, &hw->conf);
ath_update_txpow(sc);
ath9k_hw_set_interrupts(ah, sc->sc_imask);
} }
spin_unlock_bh(&sc->sc_resetlock);
sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
sc->sc_flags &= ~SC_OP_FULL_RESET;
if (ath_startrecv(sc) != 0) {
DPRINTF(sc, ATH_DBG_FATAL,
"Unable to restart recv logic\n");
return -EIO;
}
ath_cache_conf_rate(sc, &hw->conf);
ath_update_txpow(sc);
ath9k_hw_set_interrupts(ah, sc->sc_imask);
return 0; return 0;
} }