Merge branches 'release', 'drop_do_IRQ', 'fix_early_irq', 'misc-2.6.37', 'next-fixes', 'optimize-unwind', 'remove-compat-h' and 'stack_trace' into release
This commit is contained in:
Tony Luck
Коммит
c0f37d2ac3
|
|
@ -3925,8 +3925,10 @@ S: Supported
|
||||||
F: drivers/mfd/
|
F: drivers/mfd/
|
||||||
|
|
||||||
MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM
|
MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM
|
||||||
S: Orphan
|
M: Chris Ball <cjb@laptop.org>
|
||||||
L: linux-mmc@vger.kernel.org
|
L: linux-mmc@vger.kernel.org
|
||||||
|
T: git git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git
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||||||
|
S: Maintained
|
||||||
F: drivers/mmc/
|
F: drivers/mmc/
|
||||||
F: include/linux/mmc/
|
F: include/linux/mmc/
|
||||||
|
|
||||||
|
|
@ -5097,8 +5099,10 @@ S: Maintained
|
||||||
F: drivers/mmc/host/sdricoh_cs.c
|
F: drivers/mmc/host/sdricoh_cs.c
|
||||||
|
|
||||||
SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) DRIVER
|
SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) DRIVER
|
||||||
S: Orphan
|
M: Chris Ball <cjb@laptop.org>
|
||||||
L: linux-mmc@vger.kernel.org
|
L: linux-mmc@vger.kernel.org
|
||||||
|
T: git git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git
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||||||
|
S: Maintained
|
||||||
F: drivers/mmc/host/sdhci.*
|
F: drivers/mmc/host/sdhci.*
|
||||||
|
|
||||||
SECURE DIGITAL HOST CONTROLLER INTERFACE, OPEN FIRMWARE BINDINGS (SDHCI-OF)
|
SECURE DIGITAL HOST CONTROLLER INTERFACE, OPEN FIRMWARE BINDINGS (SDHCI-OF)
|
||||||
|
|
|
||||||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
||||||
VERSION = 2
|
VERSION = 2
|
||||||
PATCHLEVEL = 6
|
PATCHLEVEL = 6
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||||||
SUBLEVEL = 36
|
SUBLEVEL = 36
|
||||||
EXTRAVERSION = -rc5
|
EXTRAVERSION = -rc6
|
||||||
NAME = Sheep on Meth
|
NAME = Sheep on Meth
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||||||
|
|
||||||
# *DOCUMENTATION*
|
# *DOCUMENTATION*
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||||||
|
|
|
||||||
|
|
@ -914,15 +914,6 @@ sys_execve:
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||||||
jmp $31, do_sys_execve
|
jmp $31, do_sys_execve
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||||||
.end sys_execve
|
.end sys_execve
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||||||
|
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||||||
.align 4
|
|
||||||
.globl osf_sigprocmask
|
|
||||||
.ent osf_sigprocmask
|
|
||||||
osf_sigprocmask:
|
|
||||||
.prologue 0
|
|
||||||
mov $sp, $18
|
|
||||||
jmp $31, sys_osf_sigprocmask
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|
||||||
.end osf_sigprocmask
|
|
||||||
|
|
||||||
.align 4
|
.align 4
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||||||
.globl alpha_ni_syscall
|
.globl alpha_ni_syscall
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||||||
.ent alpha_ni_syscall
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.ent alpha_ni_syscall
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||||||
|
|
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||||||
|
|
@ -41,46 +41,20 @@ static void do_signal(struct pt_regs *, struct switch_stack *,
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||||||
/*
|
/*
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||||||
* The OSF/1 sigprocmask calling sequence is different from the
|
* The OSF/1 sigprocmask calling sequence is different from the
|
||||||
* C sigprocmask() sequence..
|
* C sigprocmask() sequence..
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||||||
*
|
|
||||||
* how:
|
|
||||||
* 1 - SIG_BLOCK
|
|
||||||
* 2 - SIG_UNBLOCK
|
|
||||||
* 3 - SIG_SETMASK
|
|
||||||
*
|
|
||||||
* We change the range to -1 .. 1 in order to let gcc easily
|
|
||||||
* use the conditional move instructions.
|
|
||||||
*
|
|
||||||
* Note that we don't need to acquire the kernel lock for SMP
|
|
||||||
* operation, as all of this is local to this thread.
|
|
||||||
*/
|
*/
|
||||||
SYSCALL_DEFINE3(osf_sigprocmask, int, how, unsigned long, newmask,
|
SYSCALL_DEFINE2(osf_sigprocmask, int, how, unsigned long, newmask)
|
||||||
struct pt_regs *, regs)
|
|
||||||
{
|
{
|
||||||
unsigned long oldmask = -EINVAL;
|
sigset_t oldmask;
|
||||||
|
sigset_t mask;
|
||||||
|
unsigned long res;
|
||||||
|
|
||||||
if ((unsigned long)how-1 <= 2) {
|
siginitset(&mask, newmask & ~_BLOCKABLE);
|
||||||
long sign = how-2; /* -1 .. 1 */
|
res = sigprocmask(how, &mask, &oldmask);
|
||||||
unsigned long block, unblock;
|
if (!res) {
|
||||||
|
force_successful_syscall_return();
|
||||||
newmask &= _BLOCKABLE;
|
res = oldmask.sig[0];
|
||||||
spin_lock_irq(¤t->sighand->siglock);
|
|
||||||
oldmask = current->blocked.sig[0];
|
|
||||||
|
|
||||||
unblock = oldmask & ~newmask;
|
|
||||||
block = oldmask | newmask;
|
|
||||||
if (!sign)
|
|
||||||
block = unblock;
|
|
||||||
if (sign <= 0)
|
|
||||||
newmask = block;
|
|
||||||
if (_NSIG_WORDS > 1 && sign > 0)
|
|
||||||
sigemptyset(¤t->blocked);
|
|
||||||
current->blocked.sig[0] = newmask;
|
|
||||||
recalc_sigpending();
|
|
||||||
spin_unlock_irq(¤t->sighand->siglock);
|
|
||||||
|
|
||||||
regs->r0 = 0; /* special no error return */
|
|
||||||
}
|
}
|
||||||
return oldmask;
|
return res;
|
||||||
}
|
}
|
||||||
|
|
||||||
SYSCALL_DEFINE3(osf_sigaction, int, sig,
|
SYSCALL_DEFINE3(osf_sigaction, int, sig,
|
||||||
|
|
@ -94,9 +68,9 @@ SYSCALL_DEFINE3(osf_sigaction, int, sig,
|
||||||
old_sigset_t mask;
|
old_sigset_t mask;
|
||||||
if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
|
if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
|
||||||
__get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
|
__get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
|
||||||
__get_user(new_ka.sa.sa_flags, &act->sa_flags))
|
__get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
|
||||||
|
__get_user(mask, &act->sa_mask))
|
||||||
return -EFAULT;
|
return -EFAULT;
|
||||||
__get_user(mask, &act->sa_mask);
|
|
||||||
siginitset(&new_ka.sa.sa_mask, mask);
|
siginitset(&new_ka.sa.sa_mask, mask);
|
||||||
new_ka.ka_restorer = NULL;
|
new_ka.ka_restorer = NULL;
|
||||||
}
|
}
|
||||||
|
|
@ -106,9 +80,9 @@ SYSCALL_DEFINE3(osf_sigaction, int, sig,
|
||||||
if (!ret && oact) {
|
if (!ret && oact) {
|
||||||
if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
|
if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
|
||||||
__put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
|
__put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
|
||||||
__put_user(old_ka.sa.sa_flags, &oact->sa_flags))
|
__put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
|
||||||
|
__put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
|
||||||
return -EFAULT;
|
return -EFAULT;
|
||||||
__put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
|
|
|
||||||
|
|
@ -58,7 +58,7 @@ sys_call_table:
|
||||||
.quad sys_open /* 45 */
|
.quad sys_open /* 45 */
|
||||||
.quad alpha_ni_syscall
|
.quad alpha_ni_syscall
|
||||||
.quad sys_getxgid
|
.quad sys_getxgid
|
||||||
.quad osf_sigprocmask
|
.quad sys_osf_sigprocmask
|
||||||
.quad alpha_ni_syscall
|
.quad alpha_ni_syscall
|
||||||
.quad alpha_ni_syscall /* 50 */
|
.quad alpha_ni_syscall /* 50 */
|
||||||
.quad sys_acct
|
.quad sys_acct
|
||||||
|
|
|
||||||
|
|
@ -271,7 +271,6 @@ config ARCH_AT91
|
||||||
bool "Atmel AT91"
|
bool "Atmel AT91"
|
||||||
select ARCH_REQUIRE_GPIOLIB
|
select ARCH_REQUIRE_GPIOLIB
|
||||||
select HAVE_CLK
|
select HAVE_CLK
|
||||||
select ARCH_USES_GETTIMEOFFSET
|
|
||||||
help
|
help
|
||||||
This enables support for systems based on the Atmel AT91RM9200,
|
This enables support for systems based on the Atmel AT91RM9200,
|
||||||
AT91SAM9 and AT91CAP9 processors.
|
AT91SAM9 and AT91CAP9 processors.
|
||||||
|
|
@ -1051,6 +1050,32 @@ config ARM_ERRATA_460075
|
||||||
ACTLR register. Note that setting specific bits in the ACTLR register
|
ACTLR register. Note that setting specific bits in the ACTLR register
|
||||||
may not be available in non-secure mode.
|
may not be available in non-secure mode.
|
||||||
|
|
||||||
|
config ARM_ERRATA_742230
|
||||||
|
bool "ARM errata: DMB operation may be faulty"
|
||||||
|
depends on CPU_V7 && SMP
|
||||||
|
help
|
||||||
|
This option enables the workaround for the 742230 Cortex-A9
|
||||||
|
(r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
|
||||||
|
between two write operations may not ensure the correct visibility
|
||||||
|
ordering of the two writes. This workaround sets a specific bit in
|
||||||
|
the diagnostic register of the Cortex-A9 which causes the DMB
|
||||||
|
instruction to behave as a DSB, ensuring the correct behaviour of
|
||||||
|
the two writes.
|
||||||
|
|
||||||
|
config ARM_ERRATA_742231
|
||||||
|
bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
|
||||||
|
depends on CPU_V7 && SMP
|
||||||
|
help
|
||||||
|
This option enables the workaround for the 742231 Cortex-A9
|
||||||
|
(r2p0..r2p2) erratum. Under certain conditions, specific to the
|
||||||
|
Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
|
||||||
|
accessing some data located in the same cache line, may get corrupted
|
||||||
|
data due to bad handling of the address hazard when the line gets
|
||||||
|
replaced from one of the CPUs at the same time as another CPU is
|
||||||
|
accessing it. This workaround sets specific bits in the diagnostic
|
||||||
|
register of the Cortex-A9 which reduces the linefill issuing
|
||||||
|
capabilities of the processor.
|
||||||
|
|
||||||
config PL310_ERRATA_588369
|
config PL310_ERRATA_588369
|
||||||
bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
|
bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
|
||||||
depends on CACHE_L2X0 && ARCH_OMAP4
|
depends on CACHE_L2X0 && ARCH_OMAP4
|
||||||
|
|
|
||||||
|
|
@ -116,5 +116,5 @@ CFLAGS_font.o := -Dstatic=
|
||||||
$(obj)/font.c: $(FONTC)
|
$(obj)/font.c: $(FONTC)
|
||||||
$(call cmd,shipped)
|
$(call cmd,shipped)
|
||||||
|
|
||||||
$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config
|
$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile $(KCONFIG_CONFIG)
|
||||||
@sed "$(SEDFLAGS)" < $< > $@
|
@sed "$(SEDFLAGS)" < $< > $@
|
||||||
|
|
|
||||||
|
|
@ -317,6 +317,10 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
|
||||||
#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
|
#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
|
||||||
#define pgprot_dmacoherent(prot) \
|
#define pgprot_dmacoherent(prot) \
|
||||||
__pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
|
__pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
|
||||||
|
#define __HAVE_PHYS_MEM_ACCESS_PROT
|
||||||
|
struct file;
|
||||||
|
extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
||||||
|
unsigned long size, pgprot_t vma_prot);
|
||||||
#else
|
#else
|
||||||
#define pgprot_dmacoherent(prot) \
|
#define pgprot_dmacoherent(prot) \
|
||||||
__pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
|
__pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
|
||||||
|
|
|
||||||
|
|
@ -48,6 +48,8 @@ work_pending:
|
||||||
beq no_work_pending
|
beq no_work_pending
|
||||||
mov r0, sp @ 'regs'
|
mov r0, sp @ 'regs'
|
||||||
mov r2, why @ 'syscall'
|
mov r2, why @ 'syscall'
|
||||||
|
tst r1, #_TIF_SIGPENDING @ delivering a signal?
|
||||||
|
movne why, #0 @ prevent further restarts
|
||||||
bl do_notify_resume
|
bl do_notify_resume
|
||||||
b ret_slow_syscall @ Check work again
|
b ret_slow_syscall @ Check work again
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -426,7 +426,7 @@ static struct i2c_gpio_platform_data pdata_i2c0 = {
|
||||||
.sda_is_open_drain = 1,
|
.sda_is_open_drain = 1,
|
||||||
.scl_pin = AT91_PIN_PA21,
|
.scl_pin = AT91_PIN_PA21,
|
||||||
.scl_is_open_drain = 1,
|
.scl_is_open_drain = 1,
|
||||||
.udelay = 2, /* ~100 kHz */
|
.udelay = 5, /* ~100 kHz */
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device at91sam9g45_twi0_device = {
|
static struct platform_device at91sam9g45_twi0_device = {
|
||||||
|
|
@ -440,7 +440,7 @@ static struct i2c_gpio_platform_data pdata_i2c1 = {
|
||||||
.sda_is_open_drain = 1,
|
.sda_is_open_drain = 1,
|
||||||
.scl_pin = AT91_PIN_PB11,
|
.scl_pin = AT91_PIN_PB11,
|
||||||
.scl_is_open_drain = 1,
|
.scl_is_open_drain = 1,
|
||||||
.udelay = 2, /* ~100 kHz */
|
.udelay = 5, /* ~100 kHz */
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device at91sam9g45_twi1_device = {
|
static struct platform_device at91sam9g45_twi1_device = {
|
||||||
|
|
|
||||||
|
|
@ -769,8 +769,7 @@ static struct map_desc dm355_io_desc[] = {
|
||||||
.virtual = SRAM_VIRT,
|
.virtual = SRAM_VIRT,
|
||||||
.pfn = __phys_to_pfn(0x00010000),
|
.pfn = __phys_to_pfn(0x00010000),
|
||||||
.length = SZ_32K,
|
.length = SZ_32K,
|
||||||
/* MT_MEMORY_NONCACHED requires supersection alignment */
|
.type = MT_MEMORY_NONCACHED,
|
||||||
.type = MT_DEVICE,
|
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -969,8 +969,7 @@ static struct map_desc dm365_io_desc[] = {
|
||||||
.virtual = SRAM_VIRT,
|
.virtual = SRAM_VIRT,
|
||||||
.pfn = __phys_to_pfn(0x00010000),
|
.pfn = __phys_to_pfn(0x00010000),
|
||||||
.length = SZ_32K,
|
.length = SZ_32K,
|
||||||
/* MT_MEMORY_NONCACHED requires supersection alignment */
|
.type = MT_MEMORY_NONCACHED,
|
||||||
.type = MT_DEVICE,
|
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -653,8 +653,7 @@ static struct map_desc dm644x_io_desc[] = {
|
||||||
.virtual = SRAM_VIRT,
|
.virtual = SRAM_VIRT,
|
||||||
.pfn = __phys_to_pfn(0x00008000),
|
.pfn = __phys_to_pfn(0x00008000),
|
||||||
.length = SZ_16K,
|
.length = SZ_16K,
|
||||||
/* MT_MEMORY_NONCACHED requires supersection alignment */
|
.type = MT_MEMORY_NONCACHED,
|
||||||
.type = MT_DEVICE,
|
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -737,8 +737,7 @@ static struct map_desc dm646x_io_desc[] = {
|
||||||
.virtual = SRAM_VIRT,
|
.virtual = SRAM_VIRT,
|
||||||
.pfn = __phys_to_pfn(0x00010000),
|
.pfn = __phys_to_pfn(0x00010000),
|
||||||
.length = SZ_32K,
|
.length = SZ_32K,
|
||||||
/* MT_MEMORY_NONCACHED requires supersection alignment */
|
.type = MT_MEMORY_NONCACHED,
|
||||||
.type = MT_DEVICE,
|
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -13,8 +13,8 @@
|
||||||
|
|
||||||
#define IO_SPACE_LIMIT 0xffffffff
|
#define IO_SPACE_LIMIT 0xffffffff
|
||||||
|
|
||||||
#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\
|
#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
|
||||||
DOVE_PCIE0_IO_VIRT_BASE))
|
DOVE_PCIE0_IO_VIRT_BASE))
|
||||||
#define __mem_pci(a) (a)
|
#define __mem_pci(a) (a)
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -38,7 +38,7 @@
|
||||||
|
|
||||||
#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
|
#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
|
||||||
#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
|
#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
|
||||||
#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000
|
#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000
|
||||||
#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
|
#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
|
||||||
|
|
||||||
#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
|
#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
|
||||||
|
|
|
||||||
|
|
@ -117,7 +117,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
|
||||||
* IORESOURCE_IO
|
* IORESOURCE_IO
|
||||||
*/
|
*/
|
||||||
pp->res[0].name = "PCIe 0 I/O Space";
|
pp->res[0].name = "PCIe 0 I/O Space";
|
||||||
pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
|
pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
|
||||||
pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
|
pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
|
||||||
pp->res[0].flags = IORESOURCE_IO;
|
pp->res[0].flags = IORESOURCE_IO;
|
||||||
|
|
||||||
|
|
@ -139,7 +139,7 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
|
||||||
* IORESOURCE_IO
|
* IORESOURCE_IO
|
||||||
*/
|
*/
|
||||||
pp->res[0].name = "PCIe 1 I/O Space";
|
pp->res[0].name = "PCIe 1 I/O Space";
|
||||||
pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
|
pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
|
||||||
pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
|
pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
|
||||||
pp->res[0].flags = IORESOURCE_IO;
|
pp->res[0].flags = IORESOURCE_IO;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -9,6 +9,8 @@
|
||||||
#ifndef __ASM_MACH_SYSTEM_H
|
#ifndef __ASM_MACH_SYSTEM_H
|
||||||
#define __ASM_MACH_SYSTEM_H
|
#define __ASM_MACH_SYSTEM_H
|
||||||
|
|
||||||
|
#include <mach/cputype.h>
|
||||||
|
|
||||||
static inline void arch_idle(void)
|
static inline void arch_idle(void)
|
||||||
{
|
{
|
||||||
cpu_do_idle();
|
cpu_do_idle();
|
||||||
|
|
@ -16,6 +18,9 @@ static inline void arch_idle(void)
|
||||||
|
|
||||||
static inline void arch_reset(char mode, const char *cmd)
|
static inline void arch_reset(char mode, const char *cmd)
|
||||||
{
|
{
|
||||||
cpu_reset(0);
|
if (cpu_is_pxa168())
|
||||||
|
cpu_reset(0xffff0000);
|
||||||
|
else
|
||||||
|
cpu_reset(0);
|
||||||
}
|
}
|
||||||
#endif /* __ASM_MACH_SYSTEM_H */
|
#endif /* __ASM_MACH_SYSTEM_H */
|
||||||
|
|
|
||||||
|
|
@ -312,8 +312,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
|
||||||
freqs.cpu = policy->cpu;
|
freqs.cpu = policy->cpu;
|
||||||
|
|
||||||
if (freq_debug)
|
if (freq_debug)
|
||||||
pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
|
pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
|
||||||
"(SDRAM %d Mhz)\n",
|
|
||||||
freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
|
freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
|
||||||
(new_freq_mem / 2000) : (new_freq_mem / 1000));
|
(new_freq_mem / 2000) : (new_freq_mem / 1000));
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -264,23 +264,35 @@
|
||||||
* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
|
* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
|
||||||
* == 0x3 for pxa300/pxa310/pxa320
|
* == 0x3 for pxa300/pxa310/pxa320
|
||||||
*/
|
*/
|
||||||
|
#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
|
||||||
#define __cpu_is_pxa2xx(id) \
|
#define __cpu_is_pxa2xx(id) \
|
||||||
({ \
|
({ \
|
||||||
unsigned int _id = (id) >> 13 & 0x7; \
|
unsigned int _id = (id) >> 13 & 0x7; \
|
||||||
_id <= 0x2; \
|
_id <= 0x2; \
|
||||||
})
|
})
|
||||||
|
#else
|
||||||
|
#define __cpu_is_pxa2xx(id) (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_PXA3xx
|
||||||
#define __cpu_is_pxa3xx(id) \
|
#define __cpu_is_pxa3xx(id) \
|
||||||
({ \
|
({ \
|
||||||
unsigned int _id = (id) >> 13 & 0x7; \
|
unsigned int _id = (id) >> 13 & 0x7; \
|
||||||
_id == 0x3; \
|
_id == 0x3; \
|
||||||
})
|
})
|
||||||
|
#else
|
||||||
|
#define __cpu_is_pxa3xx(id) (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
|
||||||
#define __cpu_is_pxa93x(id) \
|
#define __cpu_is_pxa93x(id) \
|
||||||
({ \
|
({ \
|
||||||
unsigned int _id = (id) >> 4 & 0xfff; \
|
unsigned int _id = (id) >> 4 & 0xfff; \
|
||||||
_id == 0x683 || _id == 0x693; \
|
_id == 0x683 || _id == 0x693; \
|
||||||
})
|
})
|
||||||
|
#else
|
||||||
|
#define __cpu_is_pxa93x(id) (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
#define cpu_is_pxa2xx() \
|
#define cpu_is_pxa2xx() \
|
||||||
({ \
|
({ \
|
||||||
|
|
|
||||||
|
|
@ -469,9 +469,13 @@ static struct i2c_board_info __initdata palm27x_pi2c_board_info[] = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct i2c_pxa_platform_data palm27x_i2c_power_info = {
|
||||||
|
.use_pio = 1,
|
||||||
|
};
|
||||||
|
|
||||||
void __init palm27x_pmic_init(void)
|
void __init palm27x_pmic_init(void)
|
||||||
{
|
{
|
||||||
i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info));
|
i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info));
|
||||||
pxa27x_set_i2c_power_info(NULL);
|
pxa27x_set_i2c_power_info(&palm27x_i2c_power_info);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -240,6 +240,7 @@ static void __init vpac270_onenand_init(void) {}
|
||||||
#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
|
#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
|
||||||
static struct pxamci_platform_data vpac270_mci_platform_data = {
|
static struct pxamci_platform_data vpac270_mci_platform_data = {
|
||||||
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
|
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
|
||||||
|
.gpio_power = -1,
|
||||||
.gpio_card_detect = GPIO53_VPAC270_SD_DETECT_N,
|
.gpio_card_detect = GPIO53_VPAC270_SD_DETECT_N,
|
||||||
.gpio_card_ro = GPIO52_VPAC270_SD_READONLY,
|
.gpio_card_ro = GPIO52_VPAC270_SD_READONLY,
|
||||||
.detect_delay_ms = 200,
|
.detect_delay_ms = 200,
|
||||||
|
|
|
||||||
|
|
@ -273,6 +273,9 @@ extern void gpio_pullup(unsigned gpio, int value);
|
||||||
extern int gpio_get_value(unsigned gpio);
|
extern int gpio_get_value(unsigned gpio);
|
||||||
extern void gpio_set_value(unsigned gpio, int value);
|
extern void gpio_set_value(unsigned gpio, int value);
|
||||||
|
|
||||||
|
#define gpio_get_value_cansleep gpio_get_value
|
||||||
|
#define gpio_set_value_cansleep gpio_set_value
|
||||||
|
|
||||||
/* wrappers to sleep-enable the previous two functions */
|
/* wrappers to sleep-enable the previous two functions */
|
||||||
static inline unsigned gpio_to_irq(unsigned gpio)
|
static inline unsigned gpio_to_irq(unsigned gpio)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -227,7 +227,13 @@ static void ct_ca9x4_init(void)
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
#ifdef CONFIG_CACHE_L2X0
|
#ifdef CONFIG_CACHE_L2X0
|
||||||
l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff);
|
void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
|
||||||
|
|
||||||
|
/* set RAM latencies to 1 cycle for this core tile. */
|
||||||
|
writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
|
||||||
|
writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
|
||||||
|
|
||||||
|
l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||||
|
|
|
||||||
|
|
@ -885,8 +885,23 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
|
||||||
|
|
||||||
if (ai_usermode & UM_SIGNAL)
|
if (ai_usermode & UM_SIGNAL)
|
||||||
force_sig(SIGBUS, current);
|
force_sig(SIGBUS, current);
|
||||||
else
|
else {
|
||||||
set_cr(cr_no_alignment);
|
/*
|
||||||
|
* We're about to disable the alignment trap and return to
|
||||||
|
* user space. But if an interrupt occurs before actually
|
||||||
|
* reaching user space, then the IRQ vector entry code will
|
||||||
|
* notice that we were still in kernel space and therefore
|
||||||
|
* the alignment trap won't be re-enabled in that case as it
|
||||||
|
* is presumed to be always on from kernel space.
|
||||||
|
* Let's prevent that race by disabling interrupts here (they
|
||||||
|
* are disabled on the way back to user space anyway in
|
||||||
|
* entry-common.S) and disable the alignment trap only if
|
||||||
|
* there is no work pending for this thread.
|
||||||
|
*/
|
||||||
|
raw_local_irq_disable();
|
||||||
|
if (!(current_thread_info()->flags & _TIF_WORK_MASK))
|
||||||
|
set_cr(cr_no_alignment);
|
||||||
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -15,6 +15,7 @@
|
||||||
#include <linux/nodemask.h>
|
#include <linux/nodemask.h>
|
||||||
#include <linux/memblock.h>
|
#include <linux/memblock.h>
|
||||||
#include <linux/sort.h>
|
#include <linux/sort.h>
|
||||||
|
#include <linux/fs.h>
|
||||||
|
|
||||||
#include <asm/cputype.h>
|
#include <asm/cputype.h>
|
||||||
#include <asm/sections.h>
|
#include <asm/sections.h>
|
||||||
|
|
@ -246,6 +247,9 @@ static struct mem_type mem_types[] = {
|
||||||
.domain = DOMAIN_USER,
|
.domain = DOMAIN_USER,
|
||||||
},
|
},
|
||||||
[MT_MEMORY] = {
|
[MT_MEMORY] = {
|
||||||
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
||||||
|
L_PTE_USER | L_PTE_EXEC,
|
||||||
|
.prot_l1 = PMD_TYPE_TABLE,
|
||||||
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
||||||
.domain = DOMAIN_KERNEL,
|
.domain = DOMAIN_KERNEL,
|
||||||
},
|
},
|
||||||
|
|
@ -254,6 +258,9 @@ static struct mem_type mem_types[] = {
|
||||||
.domain = DOMAIN_KERNEL,
|
.domain = DOMAIN_KERNEL,
|
||||||
},
|
},
|
||||||
[MT_MEMORY_NONCACHED] = {
|
[MT_MEMORY_NONCACHED] = {
|
||||||
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
||||||
|
L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
|
||||||
|
.prot_l1 = PMD_TYPE_TABLE,
|
||||||
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
||||||
.domain = DOMAIN_KERNEL,
|
.domain = DOMAIN_KERNEL,
|
||||||
},
|
},
|
||||||
|
|
@ -411,9 +418,12 @@ static void __init build_mem_type_table(void)
|
||||||
* Enable CPU-specific coherency if supported.
|
* Enable CPU-specific coherency if supported.
|
||||||
* (Only available on XSC3 at the moment.)
|
* (Only available on XSC3 at the moment.)
|
||||||
*/
|
*/
|
||||||
if (arch_is_coherent() && cpu_is_xsc3())
|
if (arch_is_coherent() && cpu_is_xsc3()) {
|
||||||
mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
|
mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
|
||||||
|
mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
|
||||||
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
|
||||||
|
mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
|
||||||
|
}
|
||||||
/*
|
/*
|
||||||
* ARMv6 and above have extended page tables.
|
* ARMv6 and above have extended page tables.
|
||||||
*/
|
*/
|
||||||
|
|
@ -438,7 +448,9 @@ static void __init build_mem_type_table(void)
|
||||||
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
|
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
|
||||||
mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
|
mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
|
||||||
mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
|
mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
|
||||||
|
mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
|
||||||
mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
|
||||||
|
mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -475,6 +487,8 @@ static void __init build_mem_type_table(void)
|
||||||
mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
|
mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
|
||||||
mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
|
mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
|
||||||
mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
|
mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
|
||||||
|
mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
|
||||||
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
|
||||||
mem_types[MT_ROM].prot_sect |= cp->pmd;
|
mem_types[MT_ROM].prot_sect |= cp->pmd;
|
||||||
|
|
||||||
switch (cp->pmd) {
|
switch (cp->pmd) {
|
||||||
|
|
@ -498,6 +512,19 @@ static void __init build_mem_type_table(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
|
||||||
|
pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
||||||
|
unsigned long size, pgprot_t vma_prot)
|
||||||
|
{
|
||||||
|
if (!pfn_valid(pfn))
|
||||||
|
return pgprot_noncached(vma_prot);
|
||||||
|
else if (file->f_flags & O_SYNC)
|
||||||
|
return pgprot_writecombine(vma_prot);
|
||||||
|
return vma_prot;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(phys_mem_access_prot);
|
||||||
|
#endif
|
||||||
|
|
||||||
#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
|
#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
|
||||||
|
|
||||||
static void __init *early_alloc(unsigned long sz)
|
static void __init *early_alloc(unsigned long sz)
|
||||||
|
|
|
||||||
|
|
@ -186,13 +186,14 @@ cpu_v7_name:
|
||||||
* It is assumed that:
|
* It is assumed that:
|
||||||
* - cache type register is implemented
|
* - cache type register is implemented
|
||||||
*/
|
*/
|
||||||
__v7_setup:
|
__v7_ca9mp_setup:
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
mrc p15, 0, r0, c1, c0, 1
|
mrc p15, 0, r0, c1, c0, 1
|
||||||
tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
|
tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
|
||||||
orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
|
orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
|
||||||
mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
|
mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
|
||||||
#endif
|
#endif
|
||||||
|
__v7_setup:
|
||||||
adr r12, __v7_setup_stack @ the local stack
|
adr r12, __v7_setup_stack @ the local stack
|
||||||
stmia r12, {r0-r5, r7, r9, r11, lr}
|
stmia r12, {r0-r5, r7, r9, r11, lr}
|
||||||
bl v7_flush_dcache_all
|
bl v7_flush_dcache_all
|
||||||
|
|
@ -201,11 +202,16 @@ __v7_setup:
|
||||||
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
|
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
|
||||||
and r10, r0, #0xff000000 @ ARM?
|
and r10, r0, #0xff000000 @ ARM?
|
||||||
teq r10, #0x41000000
|
teq r10, #0x41000000
|
||||||
bne 2f
|
bne 3f
|
||||||
and r5, r0, #0x00f00000 @ variant
|
and r5, r0, #0x00f00000 @ variant
|
||||||
and r6, r0, #0x0000000f @ revision
|
and r6, r0, #0x0000000f @ revision
|
||||||
orr r0, r6, r5, lsr #20-4 @ combine variant and revision
|
orr r6, r6, r5, lsr #20-4 @ combine variant and revision
|
||||||
|
ubfx r0, r0, #4, #12 @ primary part number
|
||||||
|
|
||||||
|
/* Cortex-A8 Errata */
|
||||||
|
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
|
||||||
|
teq r0, r10
|
||||||
|
bne 2f
|
||||||
#ifdef CONFIG_ARM_ERRATA_430973
|
#ifdef CONFIG_ARM_ERRATA_430973
|
||||||
teq r5, #0x00100000 @ only present in r1p*
|
teq r5, #0x00100000 @ only present in r1p*
|
||||||
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
|
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
|
||||||
|
|
@ -213,21 +219,42 @@ __v7_setup:
|
||||||
mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
|
mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_ARM_ERRATA_458693
|
#ifdef CONFIG_ARM_ERRATA_458693
|
||||||
teq r0, #0x20 @ only present in r2p0
|
teq r6, #0x20 @ only present in r2p0
|
||||||
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
|
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
|
||||||
orreq r10, r10, #(1 << 5) @ set L1NEON to 1
|
orreq r10, r10, #(1 << 5) @ set L1NEON to 1
|
||||||
orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
|
orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
|
||||||
mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
|
mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_ARM_ERRATA_460075
|
#ifdef CONFIG_ARM_ERRATA_460075
|
||||||
teq r0, #0x20 @ only present in r2p0
|
teq r6, #0x20 @ only present in r2p0
|
||||||
mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
|
mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
|
||||||
tsteq r10, #1 << 22
|
tsteq r10, #1 << 22
|
||||||
orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
|
orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
|
||||||
mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
|
mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
|
||||||
#endif
|
#endif
|
||||||
|
b 3f
|
||||||
|
|
||||||
2: mov r10, #0
|
/* Cortex-A9 Errata */
|
||||||
|
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
|
||||||
|
teq r0, r10
|
||||||
|
bne 3f
|
||||||
|
#ifdef CONFIG_ARM_ERRATA_742230
|
||||||
|
cmp r6, #0x22 @ only present up to r2p2
|
||||||
|
mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
||||||
|
orrle r10, r10, #1 << 4 @ set bit #4
|
||||||
|
mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_ARM_ERRATA_742231
|
||||||
|
teq r6, #0x20 @ present in r2p0
|
||||||
|
teqne r6, #0x21 @ present in r2p1
|
||||||
|
teqne r6, #0x22 @ present in r2p2
|
||||||
|
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
||||||
|
orreq r10, r10, #1 << 12 @ set bit #12
|
||||||
|
orreq r10, r10, #1 << 22 @ set bit #22
|
||||||
|
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
||||||
|
#endif
|
||||||
|
|
||||||
|
3: mov r10, #0
|
||||||
#ifdef HARVARD_CACHE
|
#ifdef HARVARD_CACHE
|
||||||
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
|
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -323,6 +350,29 @@ cpu_elf_name:
|
||||||
|
|
||||||
.section ".proc.info.init", #alloc, #execinstr
|
.section ".proc.info.init", #alloc, #execinstr
|
||||||
|
|
||||||
|
.type __v7_ca9mp_proc_info, #object
|
||||||
|
__v7_ca9mp_proc_info:
|
||||||
|
.long 0x410fc090 @ Required ID value
|
||||||
|
.long 0xff0ffff0 @ Mask for ID
|
||||||
|
.long PMD_TYPE_SECT | \
|
||||||
|
PMD_SECT_AP_WRITE | \
|
||||||
|
PMD_SECT_AP_READ | \
|
||||||
|
PMD_FLAGS
|
||||||
|
.long PMD_TYPE_SECT | \
|
||||||
|
PMD_SECT_XN | \
|
||||||
|
PMD_SECT_AP_WRITE | \
|
||||||
|
PMD_SECT_AP_READ
|
||||||
|
b __v7_ca9mp_setup
|
||||||
|
.long cpu_arch_name
|
||||||
|
.long cpu_elf_name
|
||||||
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
||||||
|
.long cpu_v7_name
|
||||||
|
.long v7_processor_functions
|
||||||
|
.long v7wbi_tlb_fns
|
||||||
|
.long v6_user_fns
|
||||||
|
.long v7_cache_fns
|
||||||
|
.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Match any ARMv7 processor core.
|
* Match any ARMv7 processor core.
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* linux/arch/arm/mach-nomadik/timer.c
|
* linux/arch/arm/plat-nomadik/timer.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2008 STMicroelectronics
|
* Copyright (C) 2008 STMicroelectronics
|
||||||
* Copyright (C) 2010 Alessandro Rubini
|
* Copyright (C) 2010 Alessandro Rubini
|
||||||
|
|
@ -75,7 +75,7 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
|
||||||
cr = readl(mtu_base + MTU_CR(1));
|
cr = readl(mtu_base + MTU_CR(1));
|
||||||
writel(0, mtu_base + MTU_LR(1));
|
writel(0, mtu_base + MTU_LR(1));
|
||||||
writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
|
writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
|
||||||
writel(0x2, mtu_base + MTU_IMSC);
|
writel(1 << 1, mtu_base + MTU_IMSC);
|
||||||
break;
|
break;
|
||||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||||
case CLOCK_EVT_MODE_UNUSED:
|
case CLOCK_EVT_MODE_UNUSED:
|
||||||
|
|
@ -131,25 +131,23 @@ void __init nmdk_timer_init(void)
|
||||||
{
|
{
|
||||||
unsigned long rate;
|
unsigned long rate;
|
||||||
struct clk *clk0;
|
struct clk *clk0;
|
||||||
struct clk *clk1;
|
u32 cr = MTU_CRn_32BITS;
|
||||||
u32 cr;
|
|
||||||
|
|
||||||
clk0 = clk_get_sys("mtu0", NULL);
|
clk0 = clk_get_sys("mtu0", NULL);
|
||||||
BUG_ON(IS_ERR(clk0));
|
BUG_ON(IS_ERR(clk0));
|
||||||
|
|
||||||
clk1 = clk_get_sys("mtu1", NULL);
|
|
||||||
BUG_ON(IS_ERR(clk1));
|
|
||||||
|
|
||||||
clk_enable(clk0);
|
clk_enable(clk0);
|
||||||
clk_enable(clk1);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
|
* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
|
||||||
* use a divide-by-16 counter if it's more than 16MHz
|
* for ux500.
|
||||||
|
* Use a divide-by-16 counter if the tick rate is more than 32MHz.
|
||||||
|
* At 32 MHz, the timer (with 32 bit counter) can be programmed
|
||||||
|
* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
|
||||||
|
* with 16 gives too low timer resolution.
|
||||||
*/
|
*/
|
||||||
cr = MTU_CRn_32BITS;;
|
|
||||||
rate = clk_get_rate(clk0);
|
rate = clk_get_rate(clk0);
|
||||||
if (rate > 16 << 20) {
|
if (rate > 32000000) {
|
||||||
rate /= 16;
|
rate /= 16;
|
||||||
cr |= MTU_CRn_PRESCALE_16;
|
cr |= MTU_CRn_PRESCALE_16;
|
||||||
} else {
|
} else {
|
||||||
|
|
@ -170,15 +168,8 @@ void __init nmdk_timer_init(void)
|
||||||
pr_err("timer: failed to initialize clock source %s\n",
|
pr_err("timer: failed to initialize clock source %s\n",
|
||||||
nmdk_clksrc.name);
|
nmdk_clksrc.name);
|
||||||
|
|
||||||
/* Timer 1 is used for events, fix according to rate */
|
/* Timer 1 is used for events */
|
||||||
cr = MTU_CRn_32BITS;
|
|
||||||
rate = clk_get_rate(clk1);
|
|
||||||
if (rate > 16 << 20) {
|
|
||||||
rate /= 16;
|
|
||||||
cr |= MTU_CRn_PRESCALE_16;
|
|
||||||
} else {
|
|
||||||
cr |= MTU_CRn_PRESCALE_1;
|
|
||||||
}
|
|
||||||
clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
|
clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
|
||||||
|
|
||||||
writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
|
writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
|
||||||
|
|
|
||||||
|
|
@ -220,20 +220,7 @@ void __init omap_map_sram(void)
|
||||||
if (omap_sram_size == 0)
|
if (omap_sram_size == 0)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
if (cpu_is_omap24xx()) {
|
|
||||||
omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
|
|
||||||
|
|
||||||
base = OMAP2_SRAM_PA;
|
|
||||||
base = ROUND_DOWN(base, PAGE_SIZE);
|
|
||||||
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (cpu_is_omap34xx()) {
|
if (cpu_is_omap34xx()) {
|
||||||
omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
|
|
||||||
base = OMAP3_SRAM_PA;
|
|
||||||
base = ROUND_DOWN(base, PAGE_SIZE);
|
|
||||||
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* SRAM must be marked as non-cached on OMAP3 since the
|
* SRAM must be marked as non-cached on OMAP3 since the
|
||||||
* CORE DPLL M2 divider change code (in SRAM) runs with the
|
* CORE DPLL M2 divider change code (in SRAM) runs with the
|
||||||
|
|
@ -244,13 +231,11 @@ void __init omap_map_sram(void)
|
||||||
omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
|
omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (cpu_is_omap44xx()) {
|
omap_sram_io_desc[0].virtual = omap_sram_base;
|
||||||
omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
|
base = omap_sram_start;
|
||||||
base = OMAP4_SRAM_PA;
|
base = ROUND_DOWN(base, PAGE_SIZE);
|
||||||
base = ROUND_DOWN(base, PAGE_SIZE);
|
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
|
||||||
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
|
omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
|
||||||
}
|
|
||||||
omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
|
|
||||||
iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
|
iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
|
||||||
|
|
||||||
printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
|
printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
|
||||||
|
|
|
||||||
|
|
@ -53,6 +53,9 @@ config MMU
|
||||||
bool
|
bool
|
||||||
default y
|
default y
|
||||||
|
|
||||||
|
config ARCH_DMA_ADDR_T_64BIT
|
||||||
|
def_bool y
|
||||||
|
|
||||||
config NEED_DMA_MAP_STATE
|
config NEED_DMA_MAP_STATE
|
||||||
def_bool y
|
def_bool y
|
||||||
|
|
||||||
|
|
@ -62,6 +65,9 @@ config NEED_SG_DMA_LENGTH
|
||||||
config SWIOTLB
|
config SWIOTLB
|
||||||
bool
|
bool
|
||||||
|
|
||||||
|
config STACKTRACE_SUPPORT
|
||||||
|
def_bool y
|
||||||
|
|
||||||
config GENERIC_LOCKBREAK
|
config GENERIC_LOCKBREAK
|
||||||
def_bool n
|
def_bool n
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,208 +0,0 @@
|
||||||
#ifndef _ASM_IA64_COMPAT_H
|
|
||||||
#define _ASM_IA64_COMPAT_H
|
|
||||||
/*
|
|
||||||
* Architecture specific compatibility types
|
|
||||||
*/
|
|
||||||
#include <linux/types.h>
|
|
||||||
|
|
||||||
#define COMPAT_USER_HZ 100
|
|
||||||
#define COMPAT_UTS_MACHINE "i686\0\0\0"
|
|
||||||
|
|
||||||
typedef u32 compat_size_t;
|
|
||||||
typedef s32 compat_ssize_t;
|
|
||||||
typedef s32 compat_time_t;
|
|
||||||
typedef s32 compat_clock_t;
|
|
||||||
typedef s32 compat_key_t;
|
|
||||||
typedef s32 compat_pid_t;
|
|
||||||
typedef u16 __compat_uid_t;
|
|
||||||
typedef u16 __compat_gid_t;
|
|
||||||
typedef u32 __compat_uid32_t;
|
|
||||||
typedef u32 __compat_gid32_t;
|
|
||||||
typedef u16 compat_mode_t;
|
|
||||||
typedef u32 compat_ino_t;
|
|
||||||
typedef u16 compat_dev_t;
|
|
||||||
typedef s32 compat_off_t;
|
|
||||||
typedef s64 compat_loff_t;
|
|
||||||
typedef u16 compat_nlink_t;
|
|
||||||
typedef u16 compat_ipc_pid_t;
|
|
||||||
typedef s32 compat_daddr_t;
|
|
||||||
typedef u32 compat_caddr_t;
|
|
||||||
typedef __kernel_fsid_t compat_fsid_t;
|
|
||||||
typedef s32 compat_timer_t;
|
|
||||||
|
|
||||||
typedef s32 compat_int_t;
|
|
||||||
typedef s32 compat_long_t;
|
|
||||||
typedef s64 __attribute__((aligned(4))) compat_s64;
|
|
||||||
typedef u32 compat_uint_t;
|
|
||||||
typedef u32 compat_ulong_t;
|
|
||||||
typedef u64 __attribute__((aligned(4))) compat_u64;
|
|
||||||
|
|
||||||
struct compat_timespec {
|
|
||||||
compat_time_t tv_sec;
|
|
||||||
s32 tv_nsec;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct compat_timeval {
|
|
||||||
compat_time_t tv_sec;
|
|
||||||
s32 tv_usec;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct compat_stat {
|
|
||||||
compat_dev_t st_dev;
|
|
||||||
u16 __pad1;
|
|
||||||
compat_ino_t st_ino;
|
|
||||||
compat_mode_t st_mode;
|
|
||||||
compat_nlink_t st_nlink;
|
|
||||||
__compat_uid_t st_uid;
|
|
||||||
__compat_gid_t st_gid;
|
|
||||||
compat_dev_t st_rdev;
|
|
||||||
u16 __pad2;
|
|
||||||
u32 st_size;
|
|
||||||
u32 st_blksize;
|
|
||||||
u32 st_blocks;
|
|
||||||
u32 st_atime;
|
|
||||||
u32 st_atime_nsec;
|
|
||||||
u32 st_mtime;
|
|
||||||
u32 st_mtime_nsec;
|
|
||||||
u32 st_ctime;
|
|
||||||
u32 st_ctime_nsec;
|
|
||||||
u32 __unused4;
|
|
||||||
u32 __unused5;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct compat_flock {
|
|
||||||
short l_type;
|
|
||||||
short l_whence;
|
|
||||||
compat_off_t l_start;
|
|
||||||
compat_off_t l_len;
|
|
||||||
compat_pid_t l_pid;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define F_GETLK64 12
|
|
||||||
#define F_SETLK64 13
|
|
||||||
#define F_SETLKW64 14
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IA32 uses 4 byte alignment for 64 bit quantities,
|
|
||||||
* so we need to pack this structure.
|
|
||||||
*/
|
|
||||||
struct compat_flock64 {
|
|
||||||
short l_type;
|
|
||||||
short l_whence;
|
|
||||||
compat_loff_t l_start;
|
|
||||||
compat_loff_t l_len;
|
|
||||||
compat_pid_t l_pid;
|
|
||||||
} __attribute__((packed));
|
|
||||||
|
|
||||||
struct compat_statfs {
|
|
||||||
int f_type;
|
|
||||||
int f_bsize;
|
|
||||||
int f_blocks;
|
|
||||||
int f_bfree;
|
|
||||||
int f_bavail;
|
|
||||||
int f_files;
|
|
||||||
int f_ffree;
|
|
||||||
compat_fsid_t f_fsid;
|
|
||||||
int f_namelen; /* SunOS ignores this field. */
|
|
||||||
int f_frsize;
|
|
||||||
int f_spare[5];
|
|
||||||
};
|
|
||||||
|
|
||||||
#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff
|
|
||||||
#define COMPAT_RLIM_INFINITY 0xffffffff
|
|
||||||
|
|
||||||
typedef u32 compat_old_sigset_t; /* at least 32 bits */
|
|
||||||
|
|
||||||
#define _COMPAT_NSIG 64
|
|
||||||
#define _COMPAT_NSIG_BPW 32
|
|
||||||
|
|
||||||
typedef u32 compat_sigset_word;
|
|
||||||
|
|
||||||
#define COMPAT_OFF_T_MAX 0x7fffffff
|
|
||||||
#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
|
|
||||||
|
|
||||||
struct compat_ipc64_perm {
|
|
||||||
compat_key_t key;
|
|
||||||
__compat_uid32_t uid;
|
|
||||||
__compat_gid32_t gid;
|
|
||||||
__compat_uid32_t cuid;
|
|
||||||
__compat_gid32_t cgid;
|
|
||||||
unsigned short mode;
|
|
||||||
unsigned short __pad1;
|
|
||||||
unsigned short seq;
|
|
||||||
unsigned short __pad2;
|
|
||||||
compat_ulong_t unused1;
|
|
||||||
compat_ulong_t unused2;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct compat_semid64_ds {
|
|
||||||
struct compat_ipc64_perm sem_perm;
|
|
||||||
compat_time_t sem_otime;
|
|
||||||
compat_ulong_t __unused1;
|
|
||||||
compat_time_t sem_ctime;
|
|
||||||
compat_ulong_t __unused2;
|
|
||||||
compat_ulong_t sem_nsems;
|
|
||||||
compat_ulong_t __unused3;
|
|
||||||
compat_ulong_t __unused4;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct compat_msqid64_ds {
|
|
||||||
struct compat_ipc64_perm msg_perm;
|
|
||||||
compat_time_t msg_stime;
|
|
||||||
compat_ulong_t __unused1;
|
|
||||||
compat_time_t msg_rtime;
|
|
||||||
compat_ulong_t __unused2;
|
|
||||||
compat_time_t msg_ctime;
|
|
||||||
compat_ulong_t __unused3;
|
|
||||||
compat_ulong_t msg_cbytes;
|
|
||||||
compat_ulong_t msg_qnum;
|
|
||||||
compat_ulong_t msg_qbytes;
|
|
||||||
compat_pid_t msg_lspid;
|
|
||||||
compat_pid_t msg_lrpid;
|
|
||||||
compat_ulong_t __unused4;
|
|
||||||
compat_ulong_t __unused5;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct compat_shmid64_ds {
|
|
||||||
struct compat_ipc64_perm shm_perm;
|
|
||||||
compat_size_t shm_segsz;
|
|
||||||
compat_time_t shm_atime;
|
|
||||||
compat_ulong_t __unused1;
|
|
||||||
compat_time_t shm_dtime;
|
|
||||||
compat_ulong_t __unused2;
|
|
||||||
compat_time_t shm_ctime;
|
|
||||||
compat_ulong_t __unused3;
|
|
||||||
compat_pid_t shm_cpid;
|
|
||||||
compat_pid_t shm_lpid;
|
|
||||||
compat_ulong_t shm_nattch;
|
|
||||||
compat_ulong_t __unused4;
|
|
||||||
compat_ulong_t __unused5;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* A pointer passed in from user mode. This should not be used for syscall parameters,
|
|
||||||
* just declare them as pointers because the syscall entry code will have appropriately
|
|
||||||
* converted them already.
|
|
||||||
*/
|
|
||||||
typedef u32 compat_uptr_t;
|
|
||||||
|
|
||||||
static inline void __user *
|
|
||||||
compat_ptr (compat_uptr_t uptr)
|
|
||||||
{
|
|
||||||
return (void __user *) (unsigned long) uptr;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline compat_uptr_t
|
|
||||||
ptr_to_compat(void __user *uptr)
|
|
||||||
{
|
|
||||||
return (u32)(unsigned long)uptr;
|
|
||||||
}
|
|
||||||
|
|
||||||
static __inline__ void __user *
|
|
||||||
arch_compat_alloc_user_space (long len)
|
|
||||||
{
|
|
||||||
struct pt_regs *regs = task_pt_regs(current);
|
|
||||||
return (void __user *) (((regs->r12 & 0xffffffff) & -16) - len);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* _ASM_IA64_COMPAT_H */
|
|
||||||
|
|
@ -6,12 +6,6 @@
|
||||||
* David Mosberger-Tang <davidm@hpl.hp.com>
|
* David Mosberger-Tang <davidm@hpl.hp.com>
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#include <linux/threads.h>
|
|
||||||
#include <linux/irq.h>
|
|
||||||
|
|
||||||
#include <asm/processor.h>
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* No irq_cpustat_t for IA-64. The data is held in the per-CPU data structure.
|
* No irq_cpustat_t for IA-64. The data is held in the per-CPU data structure.
|
||||||
*/
|
*/
|
||||||
|
|
@ -20,6 +14,11 @@
|
||||||
|
|
||||||
#define local_softirq_pending() (local_cpu_data->softirq_pending)
|
#define local_softirq_pending() (local_cpu_data->softirq_pending)
|
||||||
|
|
||||||
|
#include <linux/threads.h>
|
||||||
|
#include <linux/irq.h>
|
||||||
|
|
||||||
|
#include <asm/processor.h>
|
||||||
|
|
||||||
extern void __iomem *ipi_base_addr;
|
extern void __iomem *ipi_base_addr;
|
||||||
|
|
||||||
void ack_bad_irq(unsigned int irq);
|
void ack_bad_irq(unsigned int irq);
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,6 @@
|
||||||
|
#ifndef _ASM_IA64_IOMMU_TABLE_H
|
||||||
|
#define _ASM_IA64_IOMMU_TABLE_H
|
||||||
|
|
||||||
|
#define IOMMU_INIT_POST(_detect)
|
||||||
|
|
||||||
|
#endif /* _ASM_IA64_IOMMU_TABLE_H */
|
||||||
|
|
@ -34,6 +34,7 @@ obj-$(CONFIG_AUDIT) += audit.o
|
||||||
obj-$(CONFIG_PCI_MSI) += msi_ia64.o
|
obj-$(CONFIG_PCI_MSI) += msi_ia64.o
|
||||||
mca_recovery-y += mca_drv.o mca_drv_asm.o
|
mca_recovery-y += mca_drv.o mca_drv_asm.o
|
||||||
obj-$(CONFIG_IA64_MC_ERR_INJECT)+= err_inject.o
|
obj-$(CONFIG_IA64_MC_ERR_INJECT)+= err_inject.o
|
||||||
|
obj-$(CONFIG_STACKTRACE) += stacktrace.o
|
||||||
|
|
||||||
obj-$(CONFIG_PARAVIRT) += paravirt.o paravirtentry.o \
|
obj-$(CONFIG_PARAVIRT) += paravirt.o paravirtentry.o \
|
||||||
paravirt_patch.o
|
paravirt_patch.o
|
||||||
|
|
|
||||||
|
|
@ -59,13 +59,13 @@ int __init init_cyclone_clock(void)
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
base = readq(reg);
|
base = readq(reg);
|
||||||
|
iounmap(reg);
|
||||||
if(!base){
|
if(!base){
|
||||||
printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
|
printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
|
||||||
" value.\n");
|
" value.\n");
|
||||||
use_cyclone = 0;
|
use_cyclone = 0;
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
iounmap(reg);
|
|
||||||
|
|
||||||
/* setup PMCC */
|
/* setup PMCC */
|
||||||
offset = (base + CYCLONE_PMCC_OFFSET);
|
offset = (base + CYCLONE_PMCC_OFFSET);
|
||||||
|
|
|
||||||
|
|
@ -108,10 +108,6 @@
|
||||||
#define DBG(fmt...)
|
#define DBG(fmt...)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define NR_PREALLOCATE_RTE_ENTRIES \
|
|
||||||
(PAGE_SIZE / sizeof(struct iosapic_rte_info))
|
|
||||||
#define RTE_PREALLOCATED (1)
|
|
||||||
|
|
||||||
static DEFINE_SPINLOCK(iosapic_lock);
|
static DEFINE_SPINLOCK(iosapic_lock);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
@ -136,7 +132,6 @@ struct iosapic_rte_info {
|
||||||
struct list_head rte_list; /* RTEs sharing the same vector */
|
struct list_head rte_list; /* RTEs sharing the same vector */
|
||||||
char rte_index; /* IOSAPIC RTE index */
|
char rte_index; /* IOSAPIC RTE index */
|
||||||
int refcnt; /* reference counter */
|
int refcnt; /* reference counter */
|
||||||
unsigned int flags; /* flags */
|
|
||||||
struct iosapic *iosapic;
|
struct iosapic *iosapic;
|
||||||
} ____cacheline_aligned;
|
} ____cacheline_aligned;
|
||||||
|
|
||||||
|
|
@ -155,9 +150,6 @@ static struct iosapic_intr_info {
|
||||||
|
|
||||||
static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
|
static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
|
||||||
|
|
||||||
static int iosapic_kmalloc_ok;
|
|
||||||
static LIST_HEAD(free_rte_list);
|
|
||||||
|
|
||||||
static inline void
|
static inline void
|
||||||
iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
|
iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
|
||||||
{
|
{
|
||||||
|
|
@ -552,37 +544,6 @@ iosapic_reassign_vector (int irq)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct iosapic_rte_info * __init_refok iosapic_alloc_rte (void)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
struct iosapic_rte_info *rte;
|
|
||||||
int preallocated = 0;
|
|
||||||
|
|
||||||
if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
|
|
||||||
rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
|
|
||||||
NR_PREALLOCATE_RTE_ENTRIES);
|
|
||||||
for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
|
|
||||||
list_add(&rte->rte_list, &free_rte_list);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!list_empty(&free_rte_list)) {
|
|
||||||
rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
|
|
||||||
rte_list);
|
|
||||||
list_del(&rte->rte_list);
|
|
||||||
preallocated++;
|
|
||||||
} else {
|
|
||||||
rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
|
|
||||||
if (!rte)
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
memset(rte, 0, sizeof(struct iosapic_rte_info));
|
|
||||||
if (preallocated)
|
|
||||||
rte->flags |= RTE_PREALLOCATED;
|
|
||||||
|
|
||||||
return rte;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int irq_is_shared (int irq)
|
static inline int irq_is_shared (int irq)
|
||||||
{
|
{
|
||||||
return (iosapic_intr_info[irq].count > 1);
|
return (iosapic_intr_info[irq].count > 1);
|
||||||
|
|
@ -615,7 +576,7 @@ register_intr (unsigned int gsi, int irq, unsigned char delivery,
|
||||||
|
|
||||||
rte = find_rte(irq, gsi);
|
rte = find_rte(irq, gsi);
|
||||||
if (!rte) {
|
if (!rte) {
|
||||||
rte = iosapic_alloc_rte();
|
rte = kzalloc(sizeof (*rte), GFP_ATOMIC);
|
||||||
if (!rte) {
|
if (!rte) {
|
||||||
printk(KERN_WARNING "%s: cannot allocate memory\n",
|
printk(KERN_WARNING "%s: cannot allocate memory\n",
|
||||||
__func__);
|
__func__);
|
||||||
|
|
@ -1165,10 +1126,3 @@ map_iosapic_to_node(unsigned int gsi_base, int node)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static int __init iosapic_enable_kmalloc (void)
|
|
||||||
{
|
|
||||||
iosapic_kmalloc_ok = 1;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
core_initcall (iosapic_enable_kmalloc);
|
|
||||||
|
|
|
||||||
|
|
@ -30,6 +30,7 @@
|
||||||
#include <linux/bitops.h>
|
#include <linux/bitops.h>
|
||||||
#include <linux/irq.h>
|
#include <linux/irq.h>
|
||||||
#include <linux/ratelimit.h>
|
#include <linux/ratelimit.h>
|
||||||
|
#include <linux/acpi.h>
|
||||||
|
|
||||||
#include <asm/delay.h>
|
#include <asm/delay.h>
|
||||||
#include <asm/intrinsics.h>
|
#include <asm/intrinsics.h>
|
||||||
|
|
@ -651,6 +652,9 @@ ia64_native_register_ipi(void)
|
||||||
void __init
|
void __init
|
||||||
init_IRQ (void)
|
init_IRQ (void)
|
||||||
{
|
{
|
||||||
|
#ifdef CONFIG_ACPI
|
||||||
|
acpi_boot_init();
|
||||||
|
#endif
|
||||||
ia64_register_ipi();
|
ia64_register_ipi();
|
||||||
register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
|
register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
|
|
|
||||||
|
|
@ -2055,25 +2055,6 @@ ia64_mca_init(void)
|
||||||
|
|
||||||
IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__);
|
IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__);
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure the CMCI/P vector and handler. Interrupts for CMC are
|
|
||||||
* per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
|
|
||||||
*/
|
|
||||||
register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
|
|
||||||
register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
|
|
||||||
ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
|
|
||||||
|
|
||||||
/* Setup the MCA rendezvous interrupt vector */
|
|
||||||
register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
|
|
||||||
|
|
||||||
/* Setup the MCA wakeup interrupt vector */
|
|
||||||
register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
|
|
||||||
|
|
||||||
#ifdef CONFIG_ACPI
|
|
||||||
/* Setup the CPEI/P handler */
|
|
||||||
register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Initialize the areas set aside by the OS to buffer the
|
/* Initialize the areas set aside by the OS to buffer the
|
||||||
* platform/processor error states for MCA/INIT/CMC
|
* platform/processor error states for MCA/INIT/CMC
|
||||||
* handling.
|
* handling.
|
||||||
|
|
@ -2103,6 +2084,25 @@ ia64_mca_late_init(void)
|
||||||
if (!mca_init)
|
if (!mca_init)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure the CMCI/P vector and handler. Interrupts for CMC are
|
||||||
|
* per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
|
||||||
|
*/
|
||||||
|
register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
|
||||||
|
register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
|
||||||
|
ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
|
||||||
|
|
||||||
|
/* Setup the MCA rendezvous interrupt vector */
|
||||||
|
register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
|
||||||
|
|
||||||
|
/* Setup the MCA wakeup interrupt vector */
|
||||||
|
register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
|
||||||
|
|
||||||
|
#ifdef CONFIG_ACPI
|
||||||
|
/* Setup the CPEI/P handler */
|
||||||
|
register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
|
||||||
|
#endif
|
||||||
|
|
||||||
register_hotcpu_notifier(&mca_cpu_notifier);
|
register_hotcpu_notifier(&mca_cpu_notifier);
|
||||||
|
|
||||||
/* Setup the CMCI/P vector and handler */
|
/* Setup the CMCI/P vector and handler */
|
||||||
|
|
|
||||||
|
|
@ -434,7 +434,7 @@ register_info(char *page)
|
||||||
unsigned long phys_stacked;
|
unsigned long phys_stacked;
|
||||||
pal_hints_u_t hints;
|
pal_hints_u_t hints;
|
||||||
unsigned long iregs, dregs;
|
unsigned long iregs, dregs;
|
||||||
char *info_type[]={
|
static const char * const info_type[] = {
|
||||||
"Implemented AR(s)",
|
"Implemented AR(s)",
|
||||||
"AR(s) with read side-effects",
|
"AR(s) with read side-effects",
|
||||||
"Implemented CR(s)",
|
"Implemented CR(s)",
|
||||||
|
|
|
||||||
|
|
@ -1573,7 +1573,7 @@ pfm_read(struct file *filp, char __user *buf, size_t size, loff_t *ppos)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
ctx = (pfm_context_t *)filp->private_data;
|
ctx = filp->private_data;
|
||||||
if (ctx == NULL) {
|
if (ctx == NULL) {
|
||||||
printk(KERN_ERR "perfmon: pfm_read: NULL ctx [%d]\n", task_pid_nr(current));
|
printk(KERN_ERR "perfmon: pfm_read: NULL ctx [%d]\n", task_pid_nr(current));
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
@ -1673,7 +1673,7 @@ pfm_poll(struct file *filp, poll_table * wait)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
ctx = (pfm_context_t *)filp->private_data;
|
ctx = filp->private_data;
|
||||||
if (ctx == NULL) {
|
if (ctx == NULL) {
|
||||||
printk(KERN_ERR "perfmon: pfm_poll: NULL ctx [%d]\n", task_pid_nr(current));
|
printk(KERN_ERR "perfmon: pfm_poll: NULL ctx [%d]\n", task_pid_nr(current));
|
||||||
return 0;
|
return 0;
|
||||||
|
|
@ -1733,7 +1733,7 @@ pfm_fasync(int fd, struct file *filp, int on)
|
||||||
return -EBADF;
|
return -EBADF;
|
||||||
}
|
}
|
||||||
|
|
||||||
ctx = (pfm_context_t *)filp->private_data;
|
ctx = filp->private_data;
|
||||||
if (ctx == NULL) {
|
if (ctx == NULL) {
|
||||||
printk(KERN_ERR "perfmon: pfm_fasync NULL ctx [%d]\n", task_pid_nr(current));
|
printk(KERN_ERR "perfmon: pfm_fasync NULL ctx [%d]\n", task_pid_nr(current));
|
||||||
return -EBADF;
|
return -EBADF;
|
||||||
|
|
@ -1841,7 +1841,7 @@ pfm_flush(struct file *filp, fl_owner_t id)
|
||||||
return -EBADF;
|
return -EBADF;
|
||||||
}
|
}
|
||||||
|
|
||||||
ctx = (pfm_context_t *)filp->private_data;
|
ctx = filp->private_data;
|
||||||
if (ctx == NULL) {
|
if (ctx == NULL) {
|
||||||
printk(KERN_ERR "perfmon: pfm_flush: NULL ctx [%d]\n", task_pid_nr(current));
|
printk(KERN_ERR "perfmon: pfm_flush: NULL ctx [%d]\n", task_pid_nr(current));
|
||||||
return -EBADF;
|
return -EBADF;
|
||||||
|
|
@ -1984,7 +1984,7 @@ pfm_close(struct inode *inode, struct file *filp)
|
||||||
return -EBADF;
|
return -EBADF;
|
||||||
}
|
}
|
||||||
|
|
||||||
ctx = (pfm_context_t *)filp->private_data;
|
ctx = filp->private_data;
|
||||||
if (ctx == NULL) {
|
if (ctx == NULL) {
|
||||||
printk(KERN_ERR "perfmon: pfm_close: NULL ctx [%d]\n", task_pid_nr(current));
|
printk(KERN_ERR "perfmon: pfm_close: NULL ctx [%d]\n", task_pid_nr(current));
|
||||||
return -EBADF;
|
return -EBADF;
|
||||||
|
|
@ -4907,7 +4907,7 @@ restart_args:
|
||||||
goto error_args;
|
goto error_args;
|
||||||
}
|
}
|
||||||
|
|
||||||
ctx = (pfm_context_t *)file->private_data;
|
ctx = file->private_data;
|
||||||
if (unlikely(ctx == NULL)) {
|
if (unlikely(ctx == NULL)) {
|
||||||
DPRINT(("no context for fd %d\n", fd));
|
DPRINT(("no context for fd %d\n", fd));
|
||||||
goto error_args;
|
goto error_args;
|
||||||
|
|
|
||||||
|
|
@ -642,7 +642,7 @@ salinfo_init(void)
|
||||||
for (i = 0; i < ARRAY_SIZE(salinfo_log_name); i++) {
|
for (i = 0; i < ARRAY_SIZE(salinfo_log_name); i++) {
|
||||||
data = salinfo_data + i;
|
data = salinfo_data + i;
|
||||||
data->type = i;
|
data->type = i;
|
||||||
init_MUTEX(&data->mutex);
|
sema_init(&data->mutex, 1);
|
||||||
dir = proc_mkdir(salinfo_log_name[i], salinfo_dir);
|
dir = proc_mkdir(salinfo_log_name[i], salinfo_dir);
|
||||||
if (!dir)
|
if (!dir)
|
||||||
continue;
|
continue;
|
||||||
|
|
|
||||||
|
|
@ -594,10 +594,6 @@ setup_arch (char **cmdline_p)
|
||||||
cpu_init(); /* initialize the bootstrap CPU */
|
cpu_init(); /* initialize the bootstrap CPU */
|
||||||
mmu_context_init(); /* initialize context_id bitmap */
|
mmu_context_init(); /* initialize context_id bitmap */
|
||||||
|
|
||||||
#ifdef CONFIG_ACPI
|
|
||||||
acpi_boot_init();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
paravirt_banner();
|
paravirt_banner();
|
||||||
paravirt_arch_setup_console(cmdline_p);
|
paravirt_arch_setup_console(cmdline_p);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,39 @@
|
||||||
|
/*
|
||||||
|
* arch/ia64/kernel/stacktrace.c
|
||||||
|
*
|
||||||
|
* Stack trace management functions
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#include <linux/sched.h>
|
||||||
|
#include <linux/stacktrace.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
|
||||||
|
static void
|
||||||
|
ia64_do_save_stack(struct unw_frame_info *info, void *arg)
|
||||||
|
{
|
||||||
|
struct stack_trace *trace = arg;
|
||||||
|
unsigned long ip;
|
||||||
|
int skip = trace->skip;
|
||||||
|
|
||||||
|
trace->nr_entries = 0;
|
||||||
|
do {
|
||||||
|
unw_get_ip(info, &ip);
|
||||||
|
if (ip == 0)
|
||||||
|
break;
|
||||||
|
if (skip == 0) {
|
||||||
|
trace->entries[trace->nr_entries++] = ip;
|
||||||
|
if (trace->nr_entries == trace->max_entries)
|
||||||
|
break;
|
||||||
|
} else
|
||||||
|
skip--;
|
||||||
|
} while (unw_unwind(info) >= 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Save stack-backtrace addresses into a stack_trace buffer.
|
||||||
|
*/
|
||||||
|
void save_stack_trace(struct stack_trace *trace)
|
||||||
|
{
|
||||||
|
unw_init_running(ia64_do_save_stack, trace);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(save_stack_trace);
|
||||||
|
|
@ -1204,10 +1204,10 @@ desc_spill_sprel_p (unsigned char qp, unw_word t, unsigned char abreg, unw_word
|
||||||
static inline unw_hash_index_t
|
static inline unw_hash_index_t
|
||||||
hash (unsigned long ip)
|
hash (unsigned long ip)
|
||||||
{
|
{
|
||||||
# define hashmagic 0x9e3779b97f4a7c16UL /* based on (sqrt(5)/2-1)*2^64 */
|
/* magic number = ((sqrt(5)-1)/2)*2^64 */
|
||||||
|
static const unsigned long hashmagic = 0x9e3779b97f4a7c16UL;
|
||||||
|
|
||||||
return (ip >> 4)*hashmagic >> (64 - UNW_LOG_HASH_SIZE);
|
return (ip >> 4) * hashmagic >> (64 - UNW_LOG_HASH_SIZE);
|
||||||
#undef hashmagic
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline long
|
static inline long
|
||||||
|
|
@ -1531,7 +1531,7 @@ build_script (struct unw_frame_info *info)
|
||||||
struct unw_labeled_state *ls, *next;
|
struct unw_labeled_state *ls, *next;
|
||||||
unsigned long ip = info->ip;
|
unsigned long ip = info->ip;
|
||||||
struct unw_state_record sr;
|
struct unw_state_record sr;
|
||||||
struct unw_table *table;
|
struct unw_table *table, *prev;
|
||||||
struct unw_reg_info *r;
|
struct unw_reg_info *r;
|
||||||
struct unw_insn insn;
|
struct unw_insn insn;
|
||||||
u8 *dp, *desc_end;
|
u8 *dp, *desc_end;
|
||||||
|
|
@ -1560,11 +1560,26 @@ build_script (struct unw_frame_info *info)
|
||||||
|
|
||||||
STAT(parse_start = ia64_get_itc());
|
STAT(parse_start = ia64_get_itc());
|
||||||
|
|
||||||
|
prev = NULL;
|
||||||
for (table = unw.tables; table; table = table->next) {
|
for (table = unw.tables; table; table = table->next) {
|
||||||
if (ip >= table->start && ip < table->end) {
|
if (ip >= table->start && ip < table->end) {
|
||||||
|
/*
|
||||||
|
* Leave the kernel unwind table at the very front,
|
||||||
|
* lest moving it breaks some assumption elsewhere.
|
||||||
|
* Otherwise, move the matching table to the second
|
||||||
|
* position in the list so that traversals can benefit
|
||||||
|
* from commonality in backtrace paths.
|
||||||
|
*/
|
||||||
|
if (prev && prev != unw.tables) {
|
||||||
|
/* unw is safe - we're already spinlocked */
|
||||||
|
prev->next = table->next;
|
||||||
|
table->next = unw.tables->next;
|
||||||
|
unw.tables->next = table;
|
||||||
|
}
|
||||||
e = lookup(table, ip - table->segment_base);
|
e = lookup(table, ip - table->segment_base);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
prev = table;
|
||||||
}
|
}
|
||||||
if (!e) {
|
if (!e) {
|
||||||
/* no info, return default unwinder (leaf proc, no mem stack, no saved regs) */
|
/* no info, return default unwinder (leaf proc, no mem stack, no saved regs) */
|
||||||
|
|
|
||||||
|
|
@ -1136,7 +1136,6 @@ __initconst = {
|
||||||
static void __init
|
static void __init
|
||||||
xen_patch_branch(unsigned long tag, unsigned long type)
|
xen_patch_branch(unsigned long tag, unsigned long type)
|
||||||
{
|
{
|
||||||
const unsigned long nelem =
|
__paravirt_patch_apply_branch(tag, type, xen_branch_target,
|
||||||
sizeof(xen_branch_target) / sizeof(xen_branch_target[0]);
|
ARRAY_SIZE(xen_branch_target));
|
||||||
__paravirt_patch_apply_branch(tag, type, xen_branch_target, nelem);
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -101,7 +101,7 @@ config GDBSTUB_DEBUG_BREAKPOINT
|
||||||
|
|
||||||
choice
|
choice
|
||||||
prompt "GDB stub port"
|
prompt "GDB stub port"
|
||||||
default GDBSTUB_TTYSM0
|
default GDBSTUB_ON_TTYSM0
|
||||||
depends on GDBSTUB
|
depends on GDBSTUB
|
||||||
help
|
help
|
||||||
Select the serial port used for GDB-stub.
|
Select the serial port used for GDB-stub.
|
||||||
|
|
|
||||||
|
|
@ -65,10 +65,10 @@ asmlinkage long sys_sigaction(int sig,
|
||||||
old_sigset_t mask;
|
old_sigset_t mask;
|
||||||
if (verify_area(VERIFY_READ, act, sizeof(*act)) ||
|
if (verify_area(VERIFY_READ, act, sizeof(*act)) ||
|
||||||
__get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
|
__get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
|
||||||
__get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
|
__get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
|
||||||
|
__get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
|
||||||
|
__get_user(mask, &act->sa_mask))
|
||||||
return -EFAULT;
|
return -EFAULT;
|
||||||
__get_user(new_ka.sa.sa_flags, &act->sa_flags);
|
|
||||||
__get_user(mask, &act->sa_mask);
|
|
||||||
siginitset(&new_ka.sa.sa_mask, mask);
|
siginitset(&new_ka.sa.sa_mask, mask);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -77,10 +77,10 @@ asmlinkage long sys_sigaction(int sig,
|
||||||
if (!ret && oact) {
|
if (!ret && oact) {
|
||||||
if (verify_area(VERIFY_WRITE, oact, sizeof(*oact)) ||
|
if (verify_area(VERIFY_WRITE, oact, sizeof(*oact)) ||
|
||||||
__put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
|
__put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
|
||||||
__put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
|
__put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
|
||||||
|
__put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
|
||||||
|
__put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
|
||||||
return -EFAULT;
|
return -EFAULT;
|
||||||
__put_user(old_ka.sa.sa_flags, &oact->sa_flags);
|
|
||||||
__put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
|
|
@ -102,6 +102,9 @@ static int restore_sigcontext(struct pt_regs *regs,
|
||||||
{
|
{
|
||||||
unsigned int err = 0;
|
unsigned int err = 0;
|
||||||
|
|
||||||
|
/* Always make any pending restarted system calls return -EINTR */
|
||||||
|
current_thread_info()->restart_block.fn = do_no_restart_syscall;
|
||||||
|
|
||||||
if (is_using_fpu(current))
|
if (is_using_fpu(current))
|
||||||
fpu_kill_state(current);
|
fpu_kill_state(current);
|
||||||
|
|
||||||
|
|
@ -330,8 +333,6 @@ static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
|
||||||
regs->d0 = sig;
|
regs->d0 = sig;
|
||||||
regs->d1 = (unsigned long) &frame->sc;
|
regs->d1 = (unsigned long) &frame->sc;
|
||||||
|
|
||||||
set_fs(USER_DS);
|
|
||||||
|
|
||||||
/* the tracer may want to single-step inside the handler */
|
/* the tracer may want to single-step inside the handler */
|
||||||
if (test_thread_flag(TIF_SINGLESTEP))
|
if (test_thread_flag(TIF_SINGLESTEP))
|
||||||
ptrace_notify(SIGTRAP);
|
ptrace_notify(SIGTRAP);
|
||||||
|
|
@ -345,7 +346,7 @@ static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
give_sigsegv:
|
give_sigsegv:
|
||||||
force_sig(SIGSEGV, current);
|
force_sigsegv(sig, current);
|
||||||
return -EFAULT;
|
return -EFAULT;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -413,8 +414,6 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
|
||||||
regs->d0 = sig;
|
regs->d0 = sig;
|
||||||
regs->d1 = (long) &frame->info;
|
regs->d1 = (long) &frame->info;
|
||||||
|
|
||||||
set_fs(USER_DS);
|
|
||||||
|
|
||||||
/* the tracer may want to single-step inside the handler */
|
/* the tracer may want to single-step inside the handler */
|
||||||
if (test_thread_flag(TIF_SINGLESTEP))
|
if (test_thread_flag(TIF_SINGLESTEP))
|
||||||
ptrace_notify(SIGTRAP);
|
ptrace_notify(SIGTRAP);
|
||||||
|
|
@ -428,10 +427,16 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
give_sigsegv:
|
give_sigsegv:
|
||||||
force_sig(SIGSEGV, current);
|
force_sigsegv(sig, current);
|
||||||
return -EFAULT;
|
return -EFAULT;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline void stepback(struct pt_regs *regs)
|
||||||
|
{
|
||||||
|
regs->pc -= 2;
|
||||||
|
regs->orig_d0 = -1;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* handle the actual delivery of a signal to userspace
|
* handle the actual delivery of a signal to userspace
|
||||||
*/
|
*/
|
||||||
|
|
@ -459,7 +464,7 @@ static int handle_signal(int sig,
|
||||||
/* fallthrough */
|
/* fallthrough */
|
||||||
case -ERESTARTNOINTR:
|
case -ERESTARTNOINTR:
|
||||||
regs->d0 = regs->orig_d0;
|
regs->d0 = regs->orig_d0;
|
||||||
regs->pc -= 2;
|
stepback(regs);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -527,12 +532,12 @@ static void do_signal(struct pt_regs *regs)
|
||||||
case -ERESTARTSYS:
|
case -ERESTARTSYS:
|
||||||
case -ERESTARTNOINTR:
|
case -ERESTARTNOINTR:
|
||||||
regs->d0 = regs->orig_d0;
|
regs->d0 = regs->orig_d0;
|
||||||
regs->pc -= 2;
|
stepback(regs);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case -ERESTART_RESTARTBLOCK:
|
case -ERESTART_RESTARTBLOCK:
|
||||||
regs->d0 = __NR_restart_syscall;
|
regs->d0 = __NR_restart_syscall;
|
||||||
regs->pc -= 2;
|
stepback(regs);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -2,13 +2,11 @@
|
||||||
# Makefile for the MN10300-specific memory management code
|
# Makefile for the MN10300-specific memory management code
|
||||||
#
|
#
|
||||||
|
|
||||||
|
cacheflush-y := cache.o cache-mn10300.o
|
||||||
|
cacheflush-$(CONFIG_MN10300_CACHE_WBACK) += cache-flush-mn10300.o
|
||||||
|
|
||||||
|
cacheflush-$(CONFIG_MN10300_CACHE_DISABLED) := cache-disabled.o
|
||||||
|
|
||||||
obj-y := \
|
obj-y := \
|
||||||
init.o fault.o pgtable.o extable.o tlb-mn10300.o mmu-context.o \
|
init.o fault.o pgtable.o extable.o tlb-mn10300.o mmu-context.o \
|
||||||
misalignment.o dma-alloc.o
|
misalignment.o dma-alloc.o $(cacheflush-y)
|
||||||
|
|
||||||
ifneq ($(CONFIG_MN10300_CACHE_DISABLED),y)
|
|
||||||
obj-y += cache.o cache-mn10300.o
|
|
||||||
ifeq ($(CONFIG_MN10300_CACHE_WBACK),y)
|
|
||||||
obj-y += cache-flush-mn10300.o
|
|
||||||
endif
|
|
||||||
endif
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
/* Handle the cache being disabled
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
|
||||||
|
* Written by David Howells (dhowells@redhat.com)
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public Licence
|
||||||
|
* as published by the Free Software Foundation; either version
|
||||||
|
* 2 of the Licence, or (at your option) any later version.
|
||||||
|
*/
|
||||||
|
#include <linux/mm.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* allow userspace to flush the instruction cache
|
||||||
|
*/
|
||||||
|
asmlinkage long sys_cacheflush(unsigned long start, unsigned long end)
|
||||||
|
{
|
||||||
|
if (end < start)
|
||||||
|
return -EINVAL;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
@ -58,7 +58,19 @@ static void parse_earlyprintk(void)
|
||||||
if (arg[pos] == ',')
|
if (arg[pos] == ',')
|
||||||
pos++;
|
pos++;
|
||||||
|
|
||||||
if (!strncmp(arg, "ttyS", 4)) {
|
/*
|
||||||
|
* make sure we have
|
||||||
|
* "serial,0x3f8,115200"
|
||||||
|
* "serial,ttyS0,115200"
|
||||||
|
* "ttyS0,115200"
|
||||||
|
*/
|
||||||
|
if (pos == 7 && !strncmp(arg + pos, "0x", 2)) {
|
||||||
|
port = simple_strtoull(arg + pos, &e, 16);
|
||||||
|
if (port == 0 || arg + pos == e)
|
||||||
|
port = DEFAULT_SERIAL_PORT;
|
||||||
|
else
|
||||||
|
pos = e - arg;
|
||||||
|
} else if (!strncmp(arg + pos, "ttyS", 4)) {
|
||||||
static const int bases[] = { 0x3f8, 0x2f8 };
|
static const int bases[] = { 0x3f8, 0x2f8 };
|
||||||
int idx = 0;
|
int idx = 0;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -38,4 +38,10 @@ static inline void amd_iommu_stats_init(void) { }
|
||||||
|
|
||||||
#endif /* !CONFIG_AMD_IOMMU_STATS */
|
#endif /* !CONFIG_AMD_IOMMU_STATS */
|
||||||
|
|
||||||
|
static inline bool is_rd890_iommu(struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
|
||||||
|
(pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
|
||||||
|
}
|
||||||
|
|
||||||
#endif /* _ASM_X86_AMD_IOMMU_PROTO_H */
|
#endif /* _ASM_X86_AMD_IOMMU_PROTO_H */
|
||||||
|
|
|
||||||
|
|
@ -368,6 +368,9 @@ struct amd_iommu {
|
||||||
/* capabilities of that IOMMU read from ACPI */
|
/* capabilities of that IOMMU read from ACPI */
|
||||||
u32 cap;
|
u32 cap;
|
||||||
|
|
||||||
|
/* flags read from acpi table */
|
||||||
|
u8 acpi_flags;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Capability pointer. There could be more than one IOMMU per PCI
|
* Capability pointer. There could be more than one IOMMU per PCI
|
||||||
* device function if there are more than one AMD IOMMU capability
|
* device function if there are more than one AMD IOMMU capability
|
||||||
|
|
@ -411,6 +414,15 @@ struct amd_iommu {
|
||||||
|
|
||||||
/* default dma_ops domain for that IOMMU */
|
/* default dma_ops domain for that IOMMU */
|
||||||
struct dma_ops_domain *default_dom;
|
struct dma_ops_domain *default_dom;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This array is required to work around a potential BIOS bug.
|
||||||
|
* The BIOS may miss to restore parts of the PCI configuration
|
||||||
|
* space when the system resumes from S3. The result is that the
|
||||||
|
* IOMMU does not execute commands anymore which leads to system
|
||||||
|
* failure.
|
||||||
|
*/
|
||||||
|
u32 cache_cfg[4];
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
|
|
@ -309,7 +309,7 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
|
||||||
static __always_inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
|
static __always_inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
|
||||||
{
|
{
|
||||||
return ((1UL << (nr % BITS_PER_LONG)) &
|
return ((1UL << (nr % BITS_PER_LONG)) &
|
||||||
(((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
|
(addr[nr / BITS_PER_LONG])) != 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
|
static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
|
||||||
|
|
|
||||||
|
|
@ -11,6 +11,8 @@ ifdef CONFIG_FUNCTION_TRACER
|
||||||
CFLAGS_REMOVE_tsc.o = -pg
|
CFLAGS_REMOVE_tsc.o = -pg
|
||||||
CFLAGS_REMOVE_rtc.o = -pg
|
CFLAGS_REMOVE_rtc.o = -pg
|
||||||
CFLAGS_REMOVE_paravirt-spinlocks.o = -pg
|
CFLAGS_REMOVE_paravirt-spinlocks.o = -pg
|
||||||
|
CFLAGS_REMOVE_pvclock.o = -pg
|
||||||
|
CFLAGS_REMOVE_kvmclock.o = -pg
|
||||||
CFLAGS_REMOVE_ftrace.o = -pg
|
CFLAGS_REMOVE_ftrace.o = -pg
|
||||||
CFLAGS_REMOVE_early_printk.o = -pg
|
CFLAGS_REMOVE_early_printk.o = -pg
|
||||||
endif
|
endif
|
||||||
|
|
|
||||||
|
|
@ -1953,6 +1953,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
|
||||||
size_t size,
|
size_t size,
|
||||||
int dir)
|
int dir)
|
||||||
{
|
{
|
||||||
|
dma_addr_t flush_addr;
|
||||||
dma_addr_t i, start;
|
dma_addr_t i, start;
|
||||||
unsigned int pages;
|
unsigned int pages;
|
||||||
|
|
||||||
|
|
@ -1960,6 +1961,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
|
||||||
(dma_addr + size > dma_dom->aperture_size))
|
(dma_addr + size > dma_dom->aperture_size))
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
flush_addr = dma_addr;
|
||||||
pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
|
pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
|
||||||
dma_addr &= PAGE_MASK;
|
dma_addr &= PAGE_MASK;
|
||||||
start = dma_addr;
|
start = dma_addr;
|
||||||
|
|
@ -1974,7 +1976,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
|
||||||
dma_ops_free_addresses(dma_dom, dma_addr, pages);
|
dma_ops_free_addresses(dma_dom, dma_addr, pages);
|
||||||
|
|
||||||
if (amd_iommu_unmap_flush || dma_dom->need_flush) {
|
if (amd_iommu_unmap_flush || dma_dom->need_flush) {
|
||||||
iommu_flush_pages(&dma_dom->domain, dma_addr, size);
|
iommu_flush_pages(&dma_dom->domain, flush_addr, size);
|
||||||
dma_dom->need_flush = false;
|
dma_dom->need_flush = false;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -632,6 +632,13 @@ static void __init init_iommu_from_pci(struct amd_iommu *iommu)
|
||||||
iommu->last_device = calc_devid(MMIO_GET_BUS(range),
|
iommu->last_device = calc_devid(MMIO_GET_BUS(range),
|
||||||
MMIO_GET_LD(range));
|
MMIO_GET_LD(range));
|
||||||
iommu->evt_msi_num = MMIO_MSI_NUM(misc);
|
iommu->evt_msi_num = MMIO_MSI_NUM(misc);
|
||||||
|
|
||||||
|
if (is_rd890_iommu(iommu->dev)) {
|
||||||
|
pci_read_config_dword(iommu->dev, 0xf0, &iommu->cache_cfg[0]);
|
||||||
|
pci_read_config_dword(iommu->dev, 0xf4, &iommu->cache_cfg[1]);
|
||||||
|
pci_read_config_dword(iommu->dev, 0xf8, &iommu->cache_cfg[2]);
|
||||||
|
pci_read_config_dword(iommu->dev, 0xfc, &iommu->cache_cfg[3]);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
@ -649,29 +656,9 @@ static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
|
||||||
struct ivhd_entry *e;
|
struct ivhd_entry *e;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* First set the recommended feature enable bits from ACPI
|
* First save the recommended feature enable bits from ACPI
|
||||||
* into the IOMMU control registers
|
|
||||||
*/
|
*/
|
||||||
h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
|
iommu->acpi_flags = h->flags;
|
||||||
iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
|
|
||||||
iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
|
|
||||||
|
|
||||||
h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
|
|
||||||
iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
|
|
||||||
iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
|
|
||||||
|
|
||||||
h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
|
|
||||||
iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
|
|
||||||
iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
|
|
||||||
|
|
||||||
h->flags & IVHD_FLAG_ISOC_EN_MASK ?
|
|
||||||
iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
|
|
||||||
iommu_feature_disable(iommu, CONTROL_ISOC_EN);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* make IOMMU memory accesses cache coherent
|
|
||||||
*/
|
|
||||||
iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Done. Now parse the device entries
|
* Done. Now parse the device entries
|
||||||
|
|
@ -1116,6 +1103,40 @@ static void init_device_table(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void iommu_init_flags(struct amd_iommu *iommu)
|
||||||
|
{
|
||||||
|
iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
|
||||||
|
iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
|
||||||
|
iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
|
||||||
|
|
||||||
|
iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
|
||||||
|
iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
|
||||||
|
iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
|
||||||
|
|
||||||
|
iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
|
||||||
|
iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
|
||||||
|
iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
|
||||||
|
|
||||||
|
iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
|
||||||
|
iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
|
||||||
|
iommu_feature_disable(iommu, CONTROL_ISOC_EN);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* make IOMMU memory accesses cache coherent
|
||||||
|
*/
|
||||||
|
iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void iommu_apply_quirks(struct amd_iommu *iommu)
|
||||||
|
{
|
||||||
|
if (is_rd890_iommu(iommu->dev)) {
|
||||||
|
pci_write_config_dword(iommu->dev, 0xf0, iommu->cache_cfg[0]);
|
||||||
|
pci_write_config_dword(iommu->dev, 0xf4, iommu->cache_cfg[1]);
|
||||||
|
pci_write_config_dword(iommu->dev, 0xf8, iommu->cache_cfg[2]);
|
||||||
|
pci_write_config_dword(iommu->dev, 0xfc, iommu->cache_cfg[3]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This function finally enables all IOMMUs found in the system after
|
* This function finally enables all IOMMUs found in the system after
|
||||||
* they have been initialized
|
* they have been initialized
|
||||||
|
|
@ -1126,6 +1147,8 @@ static void enable_iommus(void)
|
||||||
|
|
||||||
for_each_iommu(iommu) {
|
for_each_iommu(iommu) {
|
||||||
iommu_disable(iommu);
|
iommu_disable(iommu);
|
||||||
|
iommu_apply_quirks(iommu);
|
||||||
|
iommu_init_flags(iommu);
|
||||||
iommu_set_device_table(iommu);
|
iommu_set_device_table(iommu);
|
||||||
iommu_enable_command_buffer(iommu);
|
iommu_enable_command_buffer(iommu);
|
||||||
iommu_enable_event_buffer(iommu);
|
iommu_enable_event_buffer(iommu);
|
||||||
|
|
|
||||||
|
|
@ -102,6 +102,7 @@ struct cpu_hw_events {
|
||||||
*/
|
*/
|
||||||
struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
|
struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
|
||||||
unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
|
unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
|
||||||
|
unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
|
||||||
int enabled;
|
int enabled;
|
||||||
|
|
||||||
int n_events;
|
int n_events;
|
||||||
|
|
@ -1010,6 +1011,7 @@ static int x86_pmu_start(struct perf_event *event)
|
||||||
x86_perf_event_set_period(event);
|
x86_perf_event_set_period(event);
|
||||||
cpuc->events[idx] = event;
|
cpuc->events[idx] = event;
|
||||||
__set_bit(idx, cpuc->active_mask);
|
__set_bit(idx, cpuc->active_mask);
|
||||||
|
__set_bit(idx, cpuc->running);
|
||||||
x86_pmu.enable(event);
|
x86_pmu.enable(event);
|
||||||
perf_event_update_userpage(event);
|
perf_event_update_userpage(event);
|
||||||
|
|
||||||
|
|
@ -1141,8 +1143,16 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
|
||||||
cpuc = &__get_cpu_var(cpu_hw_events);
|
cpuc = &__get_cpu_var(cpu_hw_events);
|
||||||
|
|
||||||
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
||||||
if (!test_bit(idx, cpuc->active_mask))
|
if (!test_bit(idx, cpuc->active_mask)) {
|
||||||
|
/*
|
||||||
|
* Though we deactivated the counter some cpus
|
||||||
|
* might still deliver spurious interrupts still
|
||||||
|
* in flight. Catch them:
|
||||||
|
*/
|
||||||
|
if (__test_and_clear_bit(idx, cpuc->running))
|
||||||
|
handled++;
|
||||||
continue;
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
event = cpuc->events[idx];
|
event = cpuc->events[idx];
|
||||||
hwc = &event->hw;
|
hwc = &event->hw;
|
||||||
|
|
|
||||||
|
|
@ -90,6 +90,10 @@ static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
|
||||||
static int ahci_pci_device_resume(struct pci_dev *pdev);
|
static int ahci_pci_device_resume(struct pci_dev *pdev);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
static struct scsi_host_template ahci_sht = {
|
||||||
|
AHCI_SHT("ahci"),
|
||||||
|
};
|
||||||
|
|
||||||
static struct ata_port_operations ahci_vt8251_ops = {
|
static struct ata_port_operations ahci_vt8251_ops = {
|
||||||
.inherits = &ahci_ops,
|
.inherits = &ahci_ops,
|
||||||
.hardreset = ahci_vt8251_hardreset,
|
.hardreset = ahci_vt8251_hardreset,
|
||||||
|
|
|
||||||
|
|
@ -298,7 +298,17 @@ struct ahci_host_priv {
|
||||||
|
|
||||||
extern int ahci_ignore_sss;
|
extern int ahci_ignore_sss;
|
||||||
|
|
||||||
extern struct scsi_host_template ahci_sht;
|
extern struct device_attribute *ahci_shost_attrs[];
|
||||||
|
extern struct device_attribute *ahci_sdev_attrs[];
|
||||||
|
|
||||||
|
#define AHCI_SHT(drv_name) \
|
||||||
|
ATA_NCQ_SHT(drv_name), \
|
||||||
|
.can_queue = AHCI_MAX_CMDS - 1, \
|
||||||
|
.sg_tablesize = AHCI_MAX_SG, \
|
||||||
|
.dma_boundary = AHCI_DMA_BOUNDARY, \
|
||||||
|
.shost_attrs = ahci_shost_attrs, \
|
||||||
|
.sdev_attrs = ahci_sdev_attrs
|
||||||
|
|
||||||
extern struct ata_port_operations ahci_ops;
|
extern struct ata_port_operations ahci_ops;
|
||||||
|
|
||||||
void ahci_save_initial_config(struct device *dev,
|
void ahci_save_initial_config(struct device *dev,
|
||||||
|
|
|
||||||
|
|
@ -23,6 +23,10 @@
|
||||||
#include <linux/ahci_platform.h>
|
#include <linux/ahci_platform.h>
|
||||||
#include "ahci.h"
|
#include "ahci.h"
|
||||||
|
|
||||||
|
static struct scsi_host_template ahci_platform_sht = {
|
||||||
|
AHCI_SHT("ahci_platform"),
|
||||||
|
};
|
||||||
|
|
||||||
static int __init ahci_probe(struct platform_device *pdev)
|
static int __init ahci_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct device *dev = &pdev->dev;
|
struct device *dev = &pdev->dev;
|
||||||
|
|
@ -145,7 +149,7 @@ static int __init ahci_probe(struct platform_device *pdev)
|
||||||
ahci_print_info(host, "platform");
|
ahci_print_info(host, "platform");
|
||||||
|
|
||||||
rc = ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
|
rc = ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
|
||||||
&ahci_sht);
|
&ahci_platform_sht);
|
||||||
if (rc)
|
if (rc)
|
||||||
goto err0;
|
goto err0;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -121,7 +121,7 @@ static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
|
||||||
static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
|
static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
|
||||||
ahci_read_em_buffer, ahci_store_em_buffer);
|
ahci_read_em_buffer, ahci_store_em_buffer);
|
||||||
|
|
||||||
static struct device_attribute *ahci_shost_attrs[] = {
|
struct device_attribute *ahci_shost_attrs[] = {
|
||||||
&dev_attr_link_power_management_policy,
|
&dev_attr_link_power_management_policy,
|
||||||
&dev_attr_em_message_type,
|
&dev_attr_em_message_type,
|
||||||
&dev_attr_em_message,
|
&dev_attr_em_message,
|
||||||
|
|
@ -132,22 +132,14 @@ static struct device_attribute *ahci_shost_attrs[] = {
|
||||||
&dev_attr_em_buffer,
|
&dev_attr_em_buffer,
|
||||||
NULL
|
NULL
|
||||||
};
|
};
|
||||||
|
EXPORT_SYMBOL_GPL(ahci_shost_attrs);
|
||||||
|
|
||||||
static struct device_attribute *ahci_sdev_attrs[] = {
|
struct device_attribute *ahci_sdev_attrs[] = {
|
||||||
&dev_attr_sw_activity,
|
&dev_attr_sw_activity,
|
||||||
&dev_attr_unload_heads,
|
&dev_attr_unload_heads,
|
||||||
NULL
|
NULL
|
||||||
};
|
};
|
||||||
|
EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
|
||||||
struct scsi_host_template ahci_sht = {
|
|
||||||
ATA_NCQ_SHT("ahci"),
|
|
||||||
.can_queue = AHCI_MAX_CMDS - 1,
|
|
||||||
.sg_tablesize = AHCI_MAX_SG,
|
|
||||||
.dma_boundary = AHCI_DMA_BOUNDARY,
|
|
||||||
.shost_attrs = ahci_shost_attrs,
|
|
||||||
.sdev_attrs = ahci_sdev_attrs,
|
|
||||||
};
|
|
||||||
EXPORT_SYMBOL_GPL(ahci_sht);
|
|
||||||
|
|
||||||
struct ata_port_operations ahci_ops = {
|
struct ata_port_operations ahci_ops = {
|
||||||
.inherits = &sata_pmp_port_ops,
|
.inherits = &sata_pmp_port_ops,
|
||||||
|
|
|
||||||
|
|
@ -2369,7 +2369,7 @@ static void pkt_release_dev(struct pktcdvd_device *pd, int flush)
|
||||||
pkt_shrink_pktlist(pd);
|
pkt_shrink_pktlist(pd);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct pktcdvd_device *pkt_find_dev_from_minor(int dev_minor)
|
static struct pktcdvd_device *pkt_find_dev_from_minor(unsigned int dev_minor)
|
||||||
{
|
{
|
||||||
if (dev_minor >= MAX_WRITERS)
|
if (dev_minor >= MAX_WRITERS)
|
||||||
return NULL;
|
return NULL;
|
||||||
|
|
|
||||||
|
|
@ -162,7 +162,7 @@ static int mv_is_err_intr(u32 intr_cause)
|
||||||
|
|
||||||
static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
|
static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
|
||||||
{
|
{
|
||||||
u32 val = (1 << (1 + (chan->idx * 16)));
|
u32 val = ~(1 << (chan->idx * 16));
|
||||||
dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
|
dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
|
||||||
__raw_writel(val, XOR_INTR_CAUSE(chan));
|
__raw_writel(val, XOR_INTR_CAUSE(chan));
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -339,6 +339,9 @@ static void edac_mc_workq_teardown(struct mem_ctl_info *mci)
|
||||||
{
|
{
|
||||||
int status;
|
int status;
|
||||||
|
|
||||||
|
if (mci->op_state != OP_RUNNING_POLL)
|
||||||
|
return;
|
||||||
|
|
||||||
status = cancel_delayed_work(&mci->work);
|
status = cancel_delayed_work(&mci->work);
|
||||||
if (status == 0) {
|
if (status == 0) {
|
||||||
debugf0("%s() not canceled, flush the queue\n",
|
debugf0("%s() not canceled, flush the queue\n",
|
||||||
|
|
|
||||||
|
|
@ -2400,7 +2400,7 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj)
|
||||||
I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
|
I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
|
||||||
break;
|
break;
|
||||||
case 3:
|
case 3:
|
||||||
if (obj_priv->fence_reg > 8)
|
if (obj_priv->fence_reg >= 8)
|
||||||
fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
|
fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
|
||||||
else
|
else
|
||||||
case 2:
|
case 2:
|
||||||
|
|
|
||||||
|
|
@ -2170,8 +2170,7 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
err:
|
err:
|
||||||
intel_sdvo_destroy_enhance_property(connector);
|
intel_sdvo_destroy(connector);
|
||||||
kfree(intel_sdvo_connector);
|
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -2243,8 +2242,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
err:
|
err:
|
||||||
intel_sdvo_destroy_enhance_property(connector);
|
intel_sdvo_destroy(connector);
|
||||||
kfree(intel_sdvo_connector);
|
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -2522,11 +2520,10 @@ static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
|
||||||
uint16_t response;
|
uint16_t response;
|
||||||
} enhancements;
|
} enhancements;
|
||||||
|
|
||||||
if (!intel_sdvo_get_value(intel_sdvo,
|
enhancements.response = 0;
|
||||||
SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
|
intel_sdvo_get_value(intel_sdvo,
|
||||||
&enhancements, sizeof(enhancements)))
|
SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
|
||||||
return false;
|
&enhancements, sizeof(enhancements));
|
||||||
|
|
||||||
if (enhancements.response == 0) {
|
if (enhancements.response == 0) {
|
||||||
DRM_DEBUG_KMS("No enhancement is supported\n");
|
DRM_DEBUG_KMS("No enhancement is supported\n");
|
||||||
return true;
|
return true;
|
||||||
|
|
|
||||||
|
|
@ -36,6 +36,7 @@
|
||||||
#include <linux/pci.h>
|
#include <linux/pci.h>
|
||||||
#include <asm/msr.h>
|
#include <asm/msr.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
|
#include <asm/smp.h>
|
||||||
|
|
||||||
#define DRVNAME "coretemp"
|
#define DRVNAME "coretemp"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -463,7 +463,8 @@ static int send_connect(struct iwch_ep *ep)
|
||||||
V_MSS_IDX(mtu_idx) |
|
V_MSS_IDX(mtu_idx) |
|
||||||
V_L2T_IDX(ep->l2t->idx) | V_TX_CHANNEL(ep->l2t->smt_idx);
|
V_L2T_IDX(ep->l2t->idx) | V_TX_CHANNEL(ep->l2t->smt_idx);
|
||||||
opt0l = V_TOS((ep->tos >> 2) & M_TOS) | V_RCV_BUFSIZ(rcv_win>>10);
|
opt0l = V_TOS((ep->tos >> 2) & M_TOS) | V_RCV_BUFSIZ(rcv_win>>10);
|
||||||
opt2 = V_FLAVORS_VALID(1) | V_CONG_CONTROL_FLAVOR(cong_flavor);
|
opt2 = F_RX_COALESCE_VALID | V_RX_COALESCE(0) | V_FLAVORS_VALID(1) |
|
||||||
|
V_CONG_CONTROL_FLAVOR(cong_flavor);
|
||||||
skb->priority = CPL_PRIORITY_SETUP;
|
skb->priority = CPL_PRIORITY_SETUP;
|
||||||
set_arp_failure_handler(skb, act_open_req_arp_failure);
|
set_arp_failure_handler(skb, act_open_req_arp_failure);
|
||||||
|
|
||||||
|
|
@ -1280,7 +1281,8 @@ static void accept_cr(struct iwch_ep *ep, __be32 peer_ip, struct sk_buff *skb)
|
||||||
V_MSS_IDX(mtu_idx) |
|
V_MSS_IDX(mtu_idx) |
|
||||||
V_L2T_IDX(ep->l2t->idx) | V_TX_CHANNEL(ep->l2t->smt_idx);
|
V_L2T_IDX(ep->l2t->idx) | V_TX_CHANNEL(ep->l2t->smt_idx);
|
||||||
opt0l = V_TOS((ep->tos >> 2) & M_TOS) | V_RCV_BUFSIZ(rcv_win>>10);
|
opt0l = V_TOS((ep->tos >> 2) & M_TOS) | V_RCV_BUFSIZ(rcv_win>>10);
|
||||||
opt2 = V_FLAVORS_VALID(1) | V_CONG_CONTROL_FLAVOR(cong_flavor);
|
opt2 = F_RX_COALESCE_VALID | V_RX_COALESCE(0) | V_FLAVORS_VALID(1) |
|
||||||
|
V_CONG_CONTROL_FLAVOR(cong_flavor);
|
||||||
|
|
||||||
rpl = cplhdr(skb);
|
rpl = cplhdr(skb);
|
||||||
rpl->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
|
rpl->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
|
||||||
|
|
|
||||||
|
|
@ -81,7 +81,7 @@ static int ns2_led_get_mode(struct ns2_led_data *led_dat,
|
||||||
int cmd_level;
|
int cmd_level;
|
||||||
int slow_level;
|
int slow_level;
|
||||||
|
|
||||||
read_lock(&led_dat->rw_lock);
|
read_lock_irq(&led_dat->rw_lock);
|
||||||
|
|
||||||
cmd_level = gpio_get_value(led_dat->cmd);
|
cmd_level = gpio_get_value(led_dat->cmd);
|
||||||
slow_level = gpio_get_value(led_dat->slow);
|
slow_level = gpio_get_value(led_dat->slow);
|
||||||
|
|
@ -95,7 +95,7 @@ static int ns2_led_get_mode(struct ns2_led_data *led_dat,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
read_unlock(&led_dat->rw_lock);
|
read_unlock_irq(&led_dat->rw_lock);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
@ -104,8 +104,9 @@ static void ns2_led_set_mode(struct ns2_led_data *led_dat,
|
||||||
enum ns2_led_modes mode)
|
enum ns2_led_modes mode)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
write_lock(&led_dat->rw_lock);
|
write_lock_irqsave(&led_dat->rw_lock, flags);
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(ns2_led_modval); i++) {
|
for (i = 0; i < ARRAY_SIZE(ns2_led_modval); i++) {
|
||||||
if (mode == ns2_led_modval[i].mode) {
|
if (mode == ns2_led_modval[i].mode) {
|
||||||
|
|
@ -116,7 +117,7 @@ static void ns2_led_set_mode(struct ns2_led_data *led_dat,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
write_unlock(&led_dat->rw_lock);
|
write_unlock_irqrestore(&led_dat->rw_lock, flags);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void ns2_led_set(struct led_classdev *led_cdev,
|
static void ns2_led_set(struct led_classdev *led_cdev,
|
||||||
|
|
|
||||||
|
|
@ -241,8 +241,10 @@ static struct sdhci_ops sdhci_s3c_ops = {
|
||||||
static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
|
static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
|
||||||
{
|
{
|
||||||
struct sdhci_host *host = platform_get_drvdata(dev);
|
struct sdhci_host *host = platform_get_drvdata(dev);
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
if (host) {
|
if (host) {
|
||||||
spin_lock(&host->lock);
|
spin_lock_irqsave(&host->lock, flags);
|
||||||
if (state) {
|
if (state) {
|
||||||
dev_dbg(&dev->dev, "card inserted.\n");
|
dev_dbg(&dev->dev, "card inserted.\n");
|
||||||
host->flags &= ~SDHCI_DEVICE_DEAD;
|
host->flags &= ~SDHCI_DEVICE_DEAD;
|
||||||
|
|
@ -253,7 +255,7 @@ static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
|
||||||
host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
||||||
}
|
}
|
||||||
tasklet_schedule(&host->card_tasklet);
|
tasklet_schedule(&host->card_tasklet);
|
||||||
spin_unlock(&host->lock);
|
spin_unlock_irqrestore(&host->lock, flags);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -481,8 +483,10 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
|
||||||
sdhci_remove_host(host, 1);
|
sdhci_remove_host(host, 1);
|
||||||
|
|
||||||
for (ptr = 0; ptr < 3; ptr++) {
|
for (ptr = 0; ptr < 3; ptr++) {
|
||||||
clk_disable(sc->clk_bus[ptr]);
|
if (sc->clk_bus[ptr]) {
|
||||||
clk_put(sc->clk_bus[ptr]);
|
clk_disable(sc->clk_bus[ptr]);
|
||||||
|
clk_put(sc->clk_bus[ptr]);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
clk_disable(sc->clk_io);
|
clk_disable(sc->clk_io);
|
||||||
clk_put(sc->clk_io);
|
clk_put(sc->clk_io);
|
||||||
|
|
|
||||||
|
|
@ -2942,6 +2942,9 @@ static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
||||||
{
|
{
|
||||||
struct vortex_private *vp = netdev_priv(dev);
|
struct vortex_private *vp = netdev_priv(dev);
|
||||||
|
|
||||||
|
if (!VORTEX_PCI(vp))
|
||||||
|
return;
|
||||||
|
|
||||||
wol->supported = WAKE_MAGIC;
|
wol->supported = WAKE_MAGIC;
|
||||||
|
|
||||||
wol->wolopts = 0;
|
wol->wolopts = 0;
|
||||||
|
|
@ -2952,6 +2955,10 @@ static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
||||||
static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
||||||
{
|
{
|
||||||
struct vortex_private *vp = netdev_priv(dev);
|
struct vortex_private *vp = netdev_priv(dev);
|
||||||
|
|
||||||
|
if (!VORTEX_PCI(vp))
|
||||||
|
return -EOPNOTSUPP;
|
||||||
|
|
||||||
if (wol->wolopts & ~WAKE_MAGIC)
|
if (wol->wolopts & ~WAKE_MAGIC)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
|
|
@ -3201,6 +3208,9 @@ static void acpi_set_WOL(struct net_device *dev)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
|
||||||
|
return;
|
||||||
|
|
||||||
/* Change the power state to D3; RxEnable doesn't take effect. */
|
/* Change the power state to D3; RxEnable doesn't take effect. */
|
||||||
pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
|
pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1251,6 +1251,12 @@ static void atl1_free_ring_resources(struct atl1_adapter *adapter)
|
||||||
|
|
||||||
rrd_ring->desc = NULL;
|
rrd_ring->desc = NULL;
|
||||||
rrd_ring->dma = 0;
|
rrd_ring->dma = 0;
|
||||||
|
|
||||||
|
adapter->cmb.dma = 0;
|
||||||
|
adapter->cmb.cmb = NULL;
|
||||||
|
|
||||||
|
adapter->smb.dma = 0;
|
||||||
|
adapter->smb.smb = NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
|
static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
|
||||||
|
|
@ -2847,10 +2853,11 @@ static int atl1_resume(struct pci_dev *pdev)
|
||||||
pci_enable_wake(pdev, PCI_D3cold, 0);
|
pci_enable_wake(pdev, PCI_D3cold, 0);
|
||||||
|
|
||||||
atl1_reset_hw(&adapter->hw);
|
atl1_reset_hw(&adapter->hw);
|
||||||
adapter->cmb.cmb->int_stats = 0;
|
|
||||||
|
|
||||||
if (netif_running(netdev))
|
if (netif_running(netdev)) {
|
||||||
|
adapter->cmb.cmb->int_stats = 0;
|
||||||
atl1_up(adapter);
|
atl1_up(adapter);
|
||||||
|
}
|
||||||
netif_device_attach(netdev);
|
netif_device_attach(netdev);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
|
||||||
|
|
@ -57,6 +57,7 @@ enum e1e_registers {
|
||||||
E1000_SCTL = 0x00024, /* SerDes Control - RW */
|
E1000_SCTL = 0x00024, /* SerDes Control - RW */
|
||||||
E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
|
E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
|
||||||
E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
|
E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
|
||||||
|
E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
|
||||||
E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
|
E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
|
||||||
E1000_FCT = 0x00030, /* Flow Control Type - RW */
|
E1000_FCT = 0x00030, /* Flow Control Type - RW */
|
||||||
E1000_VET = 0x00038, /* VLAN Ether Type - RW */
|
E1000_VET = 0x00038, /* VLAN Ether Type - RW */
|
||||||
|
|
|
||||||
|
|
@ -105,6 +105,10 @@
|
||||||
#define E1000_FEXTNVM_SW_CONFIG 1
|
#define E1000_FEXTNVM_SW_CONFIG 1
|
||||||
#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
|
#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
|
||||||
|
|
||||||
|
#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
|
||||||
|
#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
|
||||||
|
#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
|
||||||
|
|
||||||
#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
|
#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
|
||||||
|
|
||||||
#define E1000_ICH_RAR_ENTRIES 7
|
#define E1000_ICH_RAR_ENTRIES 7
|
||||||
|
|
@ -125,6 +129,7 @@
|
||||||
|
|
||||||
/* SMBus Address Phy Register */
|
/* SMBus Address Phy Register */
|
||||||
#define HV_SMB_ADDR PHY_REG(768, 26)
|
#define HV_SMB_ADDR PHY_REG(768, 26)
|
||||||
|
#define HV_SMB_ADDR_MASK 0x007F
|
||||||
#define HV_SMB_ADDR_PEC_EN 0x0200
|
#define HV_SMB_ADDR_PEC_EN 0x0200
|
||||||
#define HV_SMB_ADDR_VALID 0x0080
|
#define HV_SMB_ADDR_VALID 0x0080
|
||||||
|
|
||||||
|
|
@ -237,6 +242,8 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
|
||||||
static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
|
static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
|
||||||
static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
|
static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
|
||||||
static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
|
static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
|
||||||
|
static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
|
||||||
|
static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
|
||||||
|
|
||||||
static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
|
static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
|
||||||
{
|
{
|
||||||
|
|
@ -272,7 +279,7 @@ static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
|
||||||
static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
|
static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
|
||||||
{
|
{
|
||||||
struct e1000_phy_info *phy = &hw->phy;
|
struct e1000_phy_info *phy = &hw->phy;
|
||||||
u32 ctrl;
|
u32 ctrl, fwsm;
|
||||||
s32 ret_val = 0;
|
s32 ret_val = 0;
|
||||||
|
|
||||||
phy->addr = 1;
|
phy->addr = 1;
|
||||||
|
|
@ -294,7 +301,8 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
|
||||||
* disabled, then toggle the LANPHYPC Value bit to force
|
* disabled, then toggle the LANPHYPC Value bit to force
|
||||||
* the interconnect to PCIe mode.
|
* the interconnect to PCIe mode.
|
||||||
*/
|
*/
|
||||||
if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
|
fwsm = er32(FWSM);
|
||||||
|
if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
|
||||||
ctrl = er32(CTRL);
|
ctrl = er32(CTRL);
|
||||||
ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
|
ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
|
||||||
ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
|
ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
|
||||||
|
|
@ -303,6 +311,13 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
|
||||||
ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
|
ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
|
||||||
ew32(CTRL, ctrl);
|
ew32(CTRL, ctrl);
|
||||||
msleep(50);
|
msleep(50);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Gate automatic PHY configuration by hardware on
|
||||||
|
* non-managed 82579
|
||||||
|
*/
|
||||||
|
if (hw->mac.type == e1000_pch2lan)
|
||||||
|
e1000_gate_hw_phy_config_ich8lan(hw, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
@ -315,6 +330,13 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
|
||||||
if (ret_val)
|
if (ret_val)
|
||||||
goto out;
|
goto out;
|
||||||
|
|
||||||
|
/* Ungate automatic PHY configuration on non-managed 82579 */
|
||||||
|
if ((hw->mac.type == e1000_pch2lan) &&
|
||||||
|
!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
|
||||||
|
msleep(10);
|
||||||
|
e1000_gate_hw_phy_config_ich8lan(hw, false);
|
||||||
|
}
|
||||||
|
|
||||||
phy->id = e1000_phy_unknown;
|
phy->id = e1000_phy_unknown;
|
||||||
ret_val = e1000e_get_phy_id(hw);
|
ret_val = e1000e_get_phy_id(hw);
|
||||||
if (ret_val)
|
if (ret_val)
|
||||||
|
|
@ -561,13 +583,10 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
|
||||||
if (mac->type == e1000_ich8lan)
|
if (mac->type == e1000_ich8lan)
|
||||||
e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
|
e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
|
||||||
|
|
||||||
/* Disable PHY configuration by hardware, config by software */
|
/* Gate automatic PHY configuration by hardware on managed 82579 */
|
||||||
if (mac->type == e1000_pch2lan) {
|
if ((mac->type == e1000_pch2lan) &&
|
||||||
u32 extcnf_ctrl = er32(EXTCNF_CTRL);
|
(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
|
||||||
|
e1000_gate_hw_phy_config_ich8lan(hw, true);
|
||||||
extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
|
|
||||||
ew32(EXTCNF_CTRL, extcnf_ctrl);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
@ -652,6 +671,12 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (hw->mac.type == e1000_pch2lan) {
|
||||||
|
ret_val = e1000_k1_workaround_lv(hw);
|
||||||
|
if (ret_val)
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Check if there was DownShift, must be checked
|
* Check if there was DownShift, must be checked
|
||||||
* immediately after link-up
|
* immediately after link-up
|
||||||
|
|
@ -894,6 +919,34 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
|
||||||
return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
|
return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
|
||||||
|
* @hw: pointer to the HW structure
|
||||||
|
*
|
||||||
|
* Assumes semaphore already acquired.
|
||||||
|
*
|
||||||
|
**/
|
||||||
|
static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
|
||||||
|
{
|
||||||
|
u16 phy_data;
|
||||||
|
u32 strap = er32(STRAP);
|
||||||
|
s32 ret_val = 0;
|
||||||
|
|
||||||
|
strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
|
||||||
|
|
||||||
|
ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
|
||||||
|
if (ret_val)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
phy_data &= ~HV_SMB_ADDR_MASK;
|
||||||
|
phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
|
||||||
|
phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
|
||||||
|
ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
|
||||||
|
|
||||||
|
out:
|
||||||
|
return ret_val;
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
|
* e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
|
||||||
* @hw: pointer to the HW structure
|
* @hw: pointer to the HW structure
|
||||||
|
|
@ -903,7 +956,6 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
|
||||||
**/
|
**/
|
||||||
static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
|
static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
|
||||||
{
|
{
|
||||||
struct e1000_adapter *adapter = hw->adapter;
|
|
||||||
struct e1000_phy_info *phy = &hw->phy;
|
struct e1000_phy_info *phy = &hw->phy;
|
||||||
u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
|
u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
|
||||||
s32 ret_val = 0;
|
s32 ret_val = 0;
|
||||||
|
|
@ -921,7 +973,8 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
|
||||||
if (phy->type != e1000_phy_igp_3)
|
if (phy->type != e1000_phy_igp_3)
|
||||||
return ret_val;
|
return ret_val;
|
||||||
|
|
||||||
if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
|
if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
|
||||||
|
(hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
|
||||||
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
|
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
@ -961,21 +1014,16 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
|
||||||
cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
|
cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
|
||||||
cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
|
cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
|
||||||
|
|
||||||
if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
|
if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
|
||||||
((hw->mac.type == e1000_pchlan) ||
|
(hw->mac.type == e1000_pchlan)) ||
|
||||||
(hw->mac.type == e1000_pch2lan))) {
|
(hw->mac.type == e1000_pch2lan)) {
|
||||||
/*
|
/*
|
||||||
* HW configures the SMBus address and LEDs when the
|
* HW configures the SMBus address and LEDs when the
|
||||||
* OEM and LCD Write Enable bits are set in the NVM.
|
* OEM and LCD Write Enable bits are set in the NVM.
|
||||||
* When both NVM bits are cleared, SW will configure
|
* When both NVM bits are cleared, SW will configure
|
||||||
* them instead.
|
* them instead.
|
||||||
*/
|
*/
|
||||||
data = er32(STRAP);
|
ret_val = e1000_write_smbus_addr(hw);
|
||||||
data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
|
|
||||||
reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
|
|
||||||
reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
|
|
||||||
ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
|
|
||||||
reg_data);
|
|
||||||
if (ret_val)
|
if (ret_val)
|
||||||
goto out;
|
goto out;
|
||||||
|
|
||||||
|
|
@ -1440,10 +1488,6 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
|
||||||
goto out;
|
goto out;
|
||||||
|
|
||||||
/* Enable jumbo frame workaround in the PHY */
|
/* Enable jumbo frame workaround in the PHY */
|
||||||
e1e_rphy(hw, PHY_REG(769, 20), &data);
|
|
||||||
ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
|
|
||||||
if (ret_val)
|
|
||||||
goto out;
|
|
||||||
e1e_rphy(hw, PHY_REG(769, 23), &data);
|
e1e_rphy(hw, PHY_REG(769, 23), &data);
|
||||||
data &= ~(0x7F << 5);
|
data &= ~(0x7F << 5);
|
||||||
data |= (0x37 << 5);
|
data |= (0x37 << 5);
|
||||||
|
|
@ -1452,7 +1496,6 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
|
||||||
goto out;
|
goto out;
|
||||||
e1e_rphy(hw, PHY_REG(769, 16), &data);
|
e1e_rphy(hw, PHY_REG(769, 16), &data);
|
||||||
data &= ~(1 << 13);
|
data &= ~(1 << 13);
|
||||||
data |= (1 << 12);
|
|
||||||
ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
|
ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
|
||||||
if (ret_val)
|
if (ret_val)
|
||||||
goto out;
|
goto out;
|
||||||
|
|
@ -1477,7 +1520,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
|
||||||
|
|
||||||
mac_reg = er32(RCTL);
|
mac_reg = er32(RCTL);
|
||||||
mac_reg &= ~E1000_RCTL_SECRC;
|
mac_reg &= ~E1000_RCTL_SECRC;
|
||||||
ew32(FFLT_DBG, mac_reg);
|
ew32(RCTL, mac_reg);
|
||||||
|
|
||||||
ret_val = e1000e_read_kmrn_reg(hw,
|
ret_val = e1000e_read_kmrn_reg(hw,
|
||||||
E1000_KMRNCTRLSTA_CTRL_OFFSET,
|
E1000_KMRNCTRLSTA_CTRL_OFFSET,
|
||||||
|
|
@ -1503,17 +1546,12 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
|
||||||
goto out;
|
goto out;
|
||||||
|
|
||||||
/* Write PHY register values back to h/w defaults */
|
/* Write PHY register values back to h/w defaults */
|
||||||
e1e_rphy(hw, PHY_REG(769, 20), &data);
|
|
||||||
ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
|
|
||||||
if (ret_val)
|
|
||||||
goto out;
|
|
||||||
e1e_rphy(hw, PHY_REG(769, 23), &data);
|
e1e_rphy(hw, PHY_REG(769, 23), &data);
|
||||||
data &= ~(0x7F << 5);
|
data &= ~(0x7F << 5);
|
||||||
ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
|
ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
|
||||||
if (ret_val)
|
if (ret_val)
|
||||||
goto out;
|
goto out;
|
||||||
e1e_rphy(hw, PHY_REG(769, 16), &data);
|
e1e_rphy(hw, PHY_REG(769, 16), &data);
|
||||||
data &= ~(1 << 12);
|
|
||||||
data |= (1 << 13);
|
data |= (1 << 13);
|
||||||
ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
|
ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
|
||||||
if (ret_val)
|
if (ret_val)
|
||||||
|
|
@ -1558,6 +1596,69 @@ out:
|
||||||
return ret_val;
|
return ret_val;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* e1000_k1_gig_workaround_lv - K1 Si workaround
|
||||||
|
* @hw: pointer to the HW structure
|
||||||
|
*
|
||||||
|
* Workaround to set the K1 beacon duration for 82579 parts
|
||||||
|
**/
|
||||||
|
static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
|
||||||
|
{
|
||||||
|
s32 ret_val = 0;
|
||||||
|
u16 status_reg = 0;
|
||||||
|
u32 mac_reg;
|
||||||
|
|
||||||
|
if (hw->mac.type != e1000_pch2lan)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
/* Set K1 beacon duration based on 1Gbps speed or otherwise */
|
||||||
|
ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
|
||||||
|
if (ret_val)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
|
||||||
|
== (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
|
||||||
|
mac_reg = er32(FEXTNVM4);
|
||||||
|
mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
|
||||||
|
|
||||||
|
if (status_reg & HV_M_STATUS_SPEED_1000)
|
||||||
|
mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
|
||||||
|
else
|
||||||
|
mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
|
||||||
|
|
||||||
|
ew32(FEXTNVM4, mac_reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
out:
|
||||||
|
return ret_val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
|
||||||
|
* @hw: pointer to the HW structure
|
||||||
|
* @gate: boolean set to true to gate, false to ungate
|
||||||
|
*
|
||||||
|
* Gate/ungate the automatic PHY configuration via hardware; perform
|
||||||
|
* the configuration via software instead.
|
||||||
|
**/
|
||||||
|
static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
|
||||||
|
{
|
||||||
|
u32 extcnf_ctrl;
|
||||||
|
|
||||||
|
if (hw->mac.type != e1000_pch2lan)
|
||||||
|
return;
|
||||||
|
|
||||||
|
extcnf_ctrl = er32(EXTCNF_CTRL);
|
||||||
|
|
||||||
|
if (gate)
|
||||||
|
extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
|
||||||
|
else
|
||||||
|
extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
|
||||||
|
|
||||||
|
ew32(EXTCNF_CTRL, extcnf_ctrl);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* e1000_lan_init_done_ich8lan - Check for PHY config completion
|
* e1000_lan_init_done_ich8lan - Check for PHY config completion
|
||||||
* @hw: pointer to the HW structure
|
* @hw: pointer to the HW structure
|
||||||
|
|
@ -1602,6 +1703,9 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
|
||||||
if (e1000_check_reset_block(hw))
|
if (e1000_check_reset_block(hw))
|
||||||
goto out;
|
goto out;
|
||||||
|
|
||||||
|
/* Allow time for h/w to get to quiescent state after reset */
|
||||||
|
msleep(10);
|
||||||
|
|
||||||
/* Perform any necessary post-reset workarounds */
|
/* Perform any necessary post-reset workarounds */
|
||||||
switch (hw->mac.type) {
|
switch (hw->mac.type) {
|
||||||
case e1000_pchlan:
|
case e1000_pchlan:
|
||||||
|
|
@ -1630,6 +1734,13 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
|
||||||
/* Configure the LCD with the OEM bits in NVM */
|
/* Configure the LCD with the OEM bits in NVM */
|
||||||
ret_val = e1000_oem_bits_config_ich8lan(hw, true);
|
ret_val = e1000_oem_bits_config_ich8lan(hw, true);
|
||||||
|
|
||||||
|
/* Ungate automatic PHY configuration on non-managed 82579 */
|
||||||
|
if ((hw->mac.type == e1000_pch2lan) &&
|
||||||
|
!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
|
||||||
|
msleep(10);
|
||||||
|
e1000_gate_hw_phy_config_ich8lan(hw, false);
|
||||||
|
}
|
||||||
|
|
||||||
out:
|
out:
|
||||||
return ret_val;
|
return ret_val;
|
||||||
}
|
}
|
||||||
|
|
@ -1646,6 +1757,11 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
|
||||||
{
|
{
|
||||||
s32 ret_val = 0;
|
s32 ret_val = 0;
|
||||||
|
|
||||||
|
/* Gate automatic PHY configuration by hardware on non-managed 82579 */
|
||||||
|
if ((hw->mac.type == e1000_pch2lan) &&
|
||||||
|
!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
|
||||||
|
e1000_gate_hw_phy_config_ich8lan(hw, true);
|
||||||
|
|
||||||
ret_val = e1000e_phy_hw_reset_generic(hw);
|
ret_val = e1000e_phy_hw_reset_generic(hw);
|
||||||
if (ret_val)
|
if (ret_val)
|
||||||
goto out;
|
goto out;
|
||||||
|
|
@ -2910,6 +3026,14 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
|
||||||
* external PHY is reset.
|
* external PHY is reset.
|
||||||
*/
|
*/
|
||||||
ctrl |= E1000_CTRL_PHY_RST;
|
ctrl |= E1000_CTRL_PHY_RST;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Gate automatic PHY configuration by hardware on
|
||||||
|
* non-managed 82579
|
||||||
|
*/
|
||||||
|
if ((hw->mac.type == e1000_pch2lan) &&
|
||||||
|
!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
|
||||||
|
e1000_gate_hw_phy_config_ich8lan(hw, true);
|
||||||
}
|
}
|
||||||
ret_val = e1000_acquire_swflag_ich8lan(hw);
|
ret_val = e1000_acquire_swflag_ich8lan(hw);
|
||||||
e_dbg("Issuing a global reset to ich8lan\n");
|
e_dbg("Issuing a global reset to ich8lan\n");
|
||||||
|
|
@ -3460,13 +3584,20 @@ void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
|
||||||
void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
|
void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
|
||||||
{
|
{
|
||||||
u32 phy_ctrl;
|
u32 phy_ctrl;
|
||||||
|
s32 ret_val;
|
||||||
|
|
||||||
phy_ctrl = er32(PHY_CTRL);
|
phy_ctrl = er32(PHY_CTRL);
|
||||||
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
|
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
|
||||||
ew32(PHY_CTRL, phy_ctrl);
|
ew32(PHY_CTRL, phy_ctrl);
|
||||||
|
|
||||||
if (hw->mac.type >= e1000_pchlan)
|
if (hw->mac.type >= e1000_pchlan) {
|
||||||
e1000_phy_hw_reset_ich8lan(hw);
|
e1000_oem_bits_config_ich8lan(hw, true);
|
||||||
|
ret_val = hw->phy.ops.acquire(hw);
|
||||||
|
if (ret_val)
|
||||||
|
return;
|
||||||
|
e1000_write_smbus_addr(hw);
|
||||||
|
hw->phy.ops.release(hw);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
||||||
|
|
@ -2704,6 +2704,16 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
|
||||||
u32 psrctl = 0;
|
u32 psrctl = 0;
|
||||||
u32 pages = 0;
|
u32 pages = 0;
|
||||||
|
|
||||||
|
/* Workaround Si errata on 82579 - configure jumbo frame flow */
|
||||||
|
if (hw->mac.type == e1000_pch2lan) {
|
||||||
|
s32 ret_val;
|
||||||
|
|
||||||
|
if (adapter->netdev->mtu > ETH_DATA_LEN)
|
||||||
|
ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
|
||||||
|
else
|
||||||
|
ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
|
||||||
|
}
|
||||||
|
|
||||||
/* Program MC offset vector base */
|
/* Program MC offset vector base */
|
||||||
rctl = er32(RCTL);
|
rctl = er32(RCTL);
|
||||||
rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
|
rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
|
||||||
|
|
@ -2744,16 +2754,6 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
|
||||||
e1e_wphy(hw, 22, phy_data);
|
e1e_wphy(hw, 22, phy_data);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Workaround Si errata on 82579 - configure jumbo frame flow */
|
|
||||||
if (hw->mac.type == e1000_pch2lan) {
|
|
||||||
s32 ret_val;
|
|
||||||
|
|
||||||
if (rctl & E1000_RCTL_LPE)
|
|
||||||
ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
|
|
||||||
else
|
|
||||||
ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Setup buffer sizes */
|
/* Setup buffer sizes */
|
||||||
rctl &= ~E1000_RCTL_SZ_4096;
|
rctl &= ~E1000_RCTL_SZ_4096;
|
||||||
rctl |= E1000_RCTL_BSEX;
|
rctl |= E1000_RCTL_BSEX;
|
||||||
|
|
@ -4833,6 +4833,15 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Jumbo frame workaround on 82579 requires CRC be stripped */
|
||||||
|
if ((adapter->hw.mac.type == e1000_pch2lan) &&
|
||||||
|
!(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
|
||||||
|
(new_mtu > ETH_DATA_LEN)) {
|
||||||
|
e_err("Jumbo Frames not supported on 82579 when CRC "
|
||||||
|
"stripping is disabled.\n");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
/* 82573 Errata 17 */
|
/* 82573 Errata 17 */
|
||||||
if (((adapter->hw.mac.type == e1000_82573) ||
|
if (((adapter->hw.mac.type == e1000_82573) ||
|
||||||
(adapter->hw.mac.type == e1000_82574)) &&
|
(adapter->hw.mac.type == e1000_82574)) &&
|
||||||
|
|
|
||||||
|
|
@ -2928,7 +2928,7 @@ static int __devinit emac_probe(struct platform_device *ofdev,
|
||||||
if (dev->emac_irq != NO_IRQ)
|
if (dev->emac_irq != NO_IRQ)
|
||||||
irq_dispose_mapping(dev->emac_irq);
|
irq_dispose_mapping(dev->emac_irq);
|
||||||
err_free:
|
err_free:
|
||||||
kfree(ndev);
|
free_netdev(ndev);
|
||||||
err_gone:
|
err_gone:
|
||||||
/* if we were on the bootlist, remove us as we won't show up and
|
/* if we were on the bootlist, remove us as we won't show up and
|
||||||
* wake up all waiters to notify them in case they were waiting
|
* wake up all waiters to notify them in case they were waiting
|
||||||
|
|
@ -2971,7 +2971,7 @@ static int __devexit emac_remove(struct platform_device *ofdev)
|
||||||
if (dev->emac_irq != NO_IRQ)
|
if (dev->emac_irq != NO_IRQ)
|
||||||
irq_dispose_mapping(dev->emac_irq);
|
irq_dispose_mapping(dev->emac_irq);
|
||||||
|
|
||||||
kfree(dev->ndev);
|
free_netdev(dev->ndev);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1540,7 +1540,6 @@ netxen_process_rcv(struct netxen_adapter *adapter,
|
||||||
if (pkt_offset)
|
if (pkt_offset)
|
||||||
skb_pull(skb, pkt_offset);
|
skb_pull(skb, pkt_offset);
|
||||||
|
|
||||||
skb->truesize = skb->len + sizeof(struct sk_buff);
|
|
||||||
skb->protocol = eth_type_trans(skb, netdev);
|
skb->protocol = eth_type_trans(skb, netdev);
|
||||||
|
|
||||||
napi_gro_receive(&sds_ring->napi, skb);
|
napi_gro_receive(&sds_ring->napi, skb);
|
||||||
|
|
@ -1602,8 +1601,6 @@ netxen_process_lro(struct netxen_adapter *adapter,
|
||||||
|
|
||||||
skb_put(skb, lro_length + data_offset);
|
skb_put(skb, lro_length + data_offset);
|
||||||
|
|
||||||
skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
|
|
||||||
|
|
||||||
skb_pull(skb, l2_hdr_offset);
|
skb_pull(skb, l2_hdr_offset);
|
||||||
skb->protocol = eth_type_trans(skb, netdev);
|
skb->protocol = eth_type_trans(skb, netdev);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1316,7 +1316,7 @@ qlcnic_alloc_rx_skb(struct qlcnic_adapter *adapter,
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
}
|
}
|
||||||
|
|
||||||
skb_reserve(skb, 2);
|
skb_reserve(skb, NET_IP_ALIGN);
|
||||||
|
|
||||||
dma = pci_map_single(pdev, skb->data,
|
dma = pci_map_single(pdev, skb->data,
|
||||||
rds_ring->dma_size, PCI_DMA_FROMDEVICE);
|
rds_ring->dma_size, PCI_DMA_FROMDEVICE);
|
||||||
|
|
@ -1404,7 +1404,6 @@ qlcnic_process_rcv(struct qlcnic_adapter *adapter,
|
||||||
if (pkt_offset)
|
if (pkt_offset)
|
||||||
skb_pull(skb, pkt_offset);
|
skb_pull(skb, pkt_offset);
|
||||||
|
|
||||||
skb->truesize = skb->len + sizeof(struct sk_buff);
|
|
||||||
skb->protocol = eth_type_trans(skb, netdev);
|
skb->protocol = eth_type_trans(skb, netdev);
|
||||||
|
|
||||||
napi_gro_receive(&sds_ring->napi, skb);
|
napi_gro_receive(&sds_ring->napi, skb);
|
||||||
|
|
@ -1466,8 +1465,6 @@ qlcnic_process_lro(struct qlcnic_adapter *adapter,
|
||||||
|
|
||||||
skb_put(skb, lro_length + data_offset);
|
skb_put(skb, lro_length + data_offset);
|
||||||
|
|
||||||
skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
|
|
||||||
|
|
||||||
skb_pull(skb, l2_hdr_offset);
|
skb_pull(skb, l2_hdr_offset);
|
||||||
skb->protocol = eth_type_trans(skb, netdev);
|
skb->protocol = eth_type_trans(skb, netdev);
|
||||||
|
|
||||||
|
|
@ -1700,8 +1697,6 @@ qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter,
|
||||||
if (pkt_offset)
|
if (pkt_offset)
|
||||||
skb_pull(skb, pkt_offset);
|
skb_pull(skb, pkt_offset);
|
||||||
|
|
||||||
skb->truesize = skb->len + sizeof(struct sk_buff);
|
|
||||||
|
|
||||||
if (!qlcnic_check_loopback_buff(skb->data))
|
if (!qlcnic_check_loopback_buff(skb->data))
|
||||||
adapter->diag_cnt++;
|
adapter->diag_cnt++;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -384,7 +384,7 @@ static void rionet_remove(struct rio_dev *rdev)
|
||||||
free_pages((unsigned long)rionet_active, rdev->net->hport->sys_size ?
|
free_pages((unsigned long)rionet_active, rdev->net->hport->sys_size ?
|
||||||
__ilog2(sizeof(void *)) + 4 : 0);
|
__ilog2(sizeof(void *)) + 4 : 0);
|
||||||
unregister_netdev(ndev);
|
unregister_netdev(ndev);
|
||||||
kfree(ndev);
|
free_netdev(ndev);
|
||||||
|
|
||||||
list_for_each_entry_safe(peer, tmp, &rionet_peers, node) {
|
list_for_each_entry_safe(peer, tmp, &rionet_peers, node) {
|
||||||
list_del(&peer->node);
|
list_del(&peer->node);
|
||||||
|
|
|
||||||
|
|
@ -804,7 +804,7 @@ static int __devinit sgiseeq_probe(struct platform_device *pdev)
|
||||||
err_out_free_page:
|
err_out_free_page:
|
||||||
free_page((unsigned long) sp->srings);
|
free_page((unsigned long) sp->srings);
|
||||||
err_out_free_dev:
|
err_out_free_dev:
|
||||||
kfree(dev);
|
free_netdev(dev);
|
||||||
|
|
||||||
err_out:
|
err_out:
|
||||||
return err;
|
return err;
|
||||||
|
|
|
||||||
|
|
@ -58,6 +58,7 @@
|
||||||
|
|
||||||
MODULE_LICENSE("GPL");
|
MODULE_LICENSE("GPL");
|
||||||
MODULE_VERSION(SMSC_DRV_VERSION);
|
MODULE_VERSION(SMSC_DRV_VERSION);
|
||||||
|
MODULE_ALIAS("platform:smsc911x");
|
||||||
|
|
||||||
#if USE_DEBUG > 0
|
#if USE_DEBUG > 0
|
||||||
static int debug = 16;
|
static int debug = 16;
|
||||||
|
|
|
||||||
|
|
@ -243,6 +243,7 @@ enum {
|
||||||
NWayState = (1 << 14) | (1 << 13) | (1 << 12),
|
NWayState = (1 << 14) | (1 << 13) | (1 << 12),
|
||||||
NWayRestart = (1 << 12),
|
NWayRestart = (1 << 12),
|
||||||
NonselPortActive = (1 << 9),
|
NonselPortActive = (1 << 9),
|
||||||
|
SelPortActive = (1 << 8),
|
||||||
LinkFailStatus = (1 << 2),
|
LinkFailStatus = (1 << 2),
|
||||||
NetCxnErr = (1 << 1),
|
NetCxnErr = (1 << 1),
|
||||||
};
|
};
|
||||||
|
|
@ -363,7 +364,9 @@ static u16 t21040_csr15[] = { 0, 0, 0x0006, 0x0000, 0x0000, };
|
||||||
|
|
||||||
/* 21041 transceiver register settings: TP AUTO, BNC, AUI, TP, TP FD*/
|
/* 21041 transceiver register settings: TP AUTO, BNC, AUI, TP, TP FD*/
|
||||||
static u16 t21041_csr13[] = { 0xEF01, 0xEF09, 0xEF09, 0xEF01, 0xEF09, };
|
static u16 t21041_csr13[] = { 0xEF01, 0xEF09, 0xEF09, 0xEF01, 0xEF09, };
|
||||||
static u16 t21041_csr14[] = { 0xFFFF, 0xF7FD, 0xF7FD, 0x6F3F, 0x6F3D, };
|
static u16 t21041_csr14[] = { 0xFFFF, 0xF7FD, 0xF7FD, 0x7F3F, 0x7F3D, };
|
||||||
|
/* If on-chip autonegotiation is broken, use half-duplex (FF3F) instead */
|
||||||
|
static u16 t21041_csr14_brk[] = { 0xFF3F, 0xF7FD, 0xF7FD, 0x7F3F, 0x7F3D, };
|
||||||
static u16 t21041_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
|
static u16 t21041_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -1064,6 +1067,9 @@ static void de21041_media_timer (unsigned long data)
|
||||||
unsigned int carrier;
|
unsigned int carrier;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
|
|
||||||
|
/* clear port active bits */
|
||||||
|
dw32(SIAStatus, NonselPortActive | SelPortActive);
|
||||||
|
|
||||||
carrier = (status & NetCxnErr) ? 0 : 1;
|
carrier = (status & NetCxnErr) ? 0 : 1;
|
||||||
|
|
||||||
if (carrier) {
|
if (carrier) {
|
||||||
|
|
@ -1158,14 +1164,29 @@ no_link_yet:
|
||||||
static void de_media_interrupt (struct de_private *de, u32 status)
|
static void de_media_interrupt (struct de_private *de, u32 status)
|
||||||
{
|
{
|
||||||
if (status & LinkPass) {
|
if (status & LinkPass) {
|
||||||
|
/* Ignore if current media is AUI or BNC and we can't use TP */
|
||||||
|
if ((de->media_type == DE_MEDIA_AUI ||
|
||||||
|
de->media_type == DE_MEDIA_BNC) &&
|
||||||
|
(de->media_lock ||
|
||||||
|
!de_ok_to_advertise(de, DE_MEDIA_TP_AUTO)))
|
||||||
|
return;
|
||||||
|
/* If current media is not TP, change it to TP */
|
||||||
|
if ((de->media_type == DE_MEDIA_AUI ||
|
||||||
|
de->media_type == DE_MEDIA_BNC)) {
|
||||||
|
de->media_type = DE_MEDIA_TP_AUTO;
|
||||||
|
de_stop_rxtx(de);
|
||||||
|
de_set_media(de);
|
||||||
|
de_start_rxtx(de);
|
||||||
|
}
|
||||||
de_link_up(de);
|
de_link_up(de);
|
||||||
mod_timer(&de->media_timer, jiffies + DE_TIMER_LINK);
|
mod_timer(&de->media_timer, jiffies + DE_TIMER_LINK);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
BUG_ON(!(status & LinkFail));
|
BUG_ON(!(status & LinkFail));
|
||||||
|
/* Mark the link as down only if current media is TP */
|
||||||
if (netif_carrier_ok(de->dev)) {
|
if (netif_carrier_ok(de->dev) && de->media_type != DE_MEDIA_AUI &&
|
||||||
|
de->media_type != DE_MEDIA_BNC) {
|
||||||
de_link_down(de);
|
de_link_down(de);
|
||||||
mod_timer(&de->media_timer, jiffies + DE_TIMER_NO_LINK);
|
mod_timer(&de->media_timer, jiffies + DE_TIMER_NO_LINK);
|
||||||
}
|
}
|
||||||
|
|
@ -1229,6 +1250,7 @@ static void de_adapter_sleep (struct de_private *de)
|
||||||
if (de->de21040)
|
if (de->de21040)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
dw32(CSR13, 0); /* Reset phy */
|
||||||
pci_read_config_dword(de->pdev, PCIPM, &pmctl);
|
pci_read_config_dword(de->pdev, PCIPM, &pmctl);
|
||||||
pmctl |= PM_Sleep;
|
pmctl |= PM_Sleep;
|
||||||
pci_write_config_dword(de->pdev, PCIPM, pmctl);
|
pci_write_config_dword(de->pdev, PCIPM, pmctl);
|
||||||
|
|
@ -1574,12 +1596,15 @@ static int __de_set_settings(struct de_private *de, struct ethtool_cmd *ecmd)
|
||||||
return 0; /* nothing to change */
|
return 0; /* nothing to change */
|
||||||
|
|
||||||
de_link_down(de);
|
de_link_down(de);
|
||||||
|
mod_timer(&de->media_timer, jiffies + DE_TIMER_NO_LINK);
|
||||||
de_stop_rxtx(de);
|
de_stop_rxtx(de);
|
||||||
|
|
||||||
de->media_type = new_media;
|
de->media_type = new_media;
|
||||||
de->media_lock = media_lock;
|
de->media_lock = media_lock;
|
||||||
de->media_advertise = ecmd->advertising;
|
de->media_advertise = ecmd->advertising;
|
||||||
de_set_media(de);
|
de_set_media(de);
|
||||||
|
if (netif_running(de->dev))
|
||||||
|
de_start_rxtx(de);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
@ -1911,8 +1936,14 @@ fill_defaults:
|
||||||
for (i = 0; i < DE_MAX_MEDIA; i++) {
|
for (i = 0; i < DE_MAX_MEDIA; i++) {
|
||||||
if (de->media[i].csr13 == 0xffff)
|
if (de->media[i].csr13 == 0xffff)
|
||||||
de->media[i].csr13 = t21041_csr13[i];
|
de->media[i].csr13 = t21041_csr13[i];
|
||||||
if (de->media[i].csr14 == 0xffff)
|
if (de->media[i].csr14 == 0xffff) {
|
||||||
de->media[i].csr14 = t21041_csr14[i];
|
/* autonegotiation is broken at least on some chip
|
||||||
|
revisions - rev. 0x21 works, 0x11 does not */
|
||||||
|
if (de->pdev->revision < 0x20)
|
||||||
|
de->media[i].csr14 = t21041_csr14_brk[i];
|
||||||
|
else
|
||||||
|
de->media[i].csr14 = t21041_csr14[i];
|
||||||
|
}
|
||||||
if (de->media[i].csr15 == 0xffff)
|
if (de->media[i].csr15 == 0xffff)
|
||||||
de->media[i].csr15 = t21041_csr15[i];
|
de->media[i].csr15 = t21041_csr15[i];
|
||||||
}
|
}
|
||||||
|
|
@ -2158,6 +2189,8 @@ static int de_resume (struct pci_dev *pdev)
|
||||||
dev_err(&dev->dev, "pci_enable_device failed in resume\n");
|
dev_err(&dev->dev, "pci_enable_device failed in resume\n");
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
pci_set_master(pdev);
|
||||||
|
de_init_rings(de);
|
||||||
de_init_hw(de);
|
de_init_hw(de);
|
||||||
out_attach:
|
out_attach:
|
||||||
netif_device_attach(dev);
|
netif_device_attach(dev);
|
||||||
|
|
|
||||||
|
|
@ -2613,6 +2613,11 @@ int iwl_force_reset(struct iwl_priv *priv, int mode, bool external)
|
||||||
if (test_bit(STATUS_EXIT_PENDING, &priv->status))
|
if (test_bit(STATUS_EXIT_PENDING, &priv->status))
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (test_bit(STATUS_SCANNING, &priv->status)) {
|
||||||
|
IWL_DEBUG_INFO(priv, "scan in progress.\n");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
if (mode >= IWL_MAX_FORCE_RESET) {
|
if (mode >= IWL_MAX_FORCE_RESET) {
|
||||||
IWL_DEBUG_INFO(priv, "invalid reset request.\n");
|
IWL_DEBUG_INFO(priv, "invalid reset request.\n");
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
|
||||||
|
|
@ -3757,6 +3757,33 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
|
||||||
|
|
||||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
|
||||||
|
|
||||||
|
#define GGC 0x52
|
||||||
|
#define GGC_MEMORY_SIZE_MASK (0xf << 8)
|
||||||
|
#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
|
||||||
|
#define GGC_MEMORY_SIZE_1M (0x1 << 8)
|
||||||
|
#define GGC_MEMORY_SIZE_2M (0x3 << 8)
|
||||||
|
#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
|
||||||
|
#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
|
||||||
|
#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
|
||||||
|
#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
|
||||||
|
|
||||||
|
static void __devinit quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
|
||||||
|
{
|
||||||
|
unsigned short ggc;
|
||||||
|
|
||||||
|
if (pci_read_config_word(dev, GGC, &ggc))
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
|
||||||
|
printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
|
||||||
|
dmar_map_gfx = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
|
||||||
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
|
||||||
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
|
||||||
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
|
||||||
|
|
||||||
/* On Tylersburg chipsets, some BIOSes have been known to enable the
|
/* On Tylersburg chipsets, some BIOSes have been known to enable the
|
||||||
ISOCH DMAR unit for the Azalia sound device, but not give it any
|
ISOCH DMAR unit for the Azalia sound device, but not give it any
|
||||||
TLB entries, which causes it to deadlock. Check for that. We do
|
TLB entries, which causes it to deadlock. Check for that. We do
|
||||||
|
|
|
||||||
|
|
@ -608,7 +608,7 @@ int pci_iov_resource_bar(struct pci_dev *dev, int resno,
|
||||||
* the VF BAR size multiplied by the number of VFs. The alignment
|
* the VF BAR size multiplied by the number of VFs. The alignment
|
||||||
* is just the VF BAR size.
|
* is just the VF BAR size.
|
||||||
*/
|
*/
|
||||||
int pci_sriov_resource_alignment(struct pci_dev *dev, int resno)
|
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno)
|
||||||
{
|
{
|
||||||
struct resource tmp;
|
struct resource tmp;
|
||||||
enum pci_bar_type type;
|
enum pci_bar_type type;
|
||||||
|
|
|
||||||
|
|
@ -264,7 +264,8 @@ extern int pci_iov_init(struct pci_dev *dev);
|
||||||
extern void pci_iov_release(struct pci_dev *dev);
|
extern void pci_iov_release(struct pci_dev *dev);
|
||||||
extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
|
extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
|
||||||
enum pci_bar_type *type);
|
enum pci_bar_type *type);
|
||||||
extern int pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
|
extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
|
||||||
|
int resno);
|
||||||
extern void pci_restore_iov_state(struct pci_dev *dev);
|
extern void pci_restore_iov_state(struct pci_dev *dev);
|
||||||
extern int pci_iov_bus_range(struct pci_bus *bus);
|
extern int pci_iov_bus_range(struct pci_bus *bus);
|
||||||
|
|
||||||
|
|
@ -320,7 +321,7 @@ static inline int pci_ats_enabled(struct pci_dev *dev)
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_PCI_IOV */
|
#endif /* CONFIG_PCI_IOV */
|
||||||
|
|
||||||
static inline int pci_resource_alignment(struct pci_dev *dev,
|
static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
|
||||||
struct resource *res)
|
struct resource *res)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_PCI_IOV
|
#ifdef CONFIG_PCI_IOV
|
||||||
|
|
|
||||||
|
|
@ -595,7 +595,13 @@ int pcmcia_request_io(struct pcmcia_device *p_dev)
|
||||||
if (c->io[1].end) {
|
if (c->io[1].end) {
|
||||||
ret = alloc_io_space(s, &c->io[1], p_dev->io_lines);
|
ret = alloc_io_space(s, &c->io[1], p_dev->io_lines);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
|
struct resource tmp = c->io[0];
|
||||||
|
/* release the previously allocated resource */
|
||||||
release_io_space(s, &c->io[0]);
|
release_io_space(s, &c->io[0]);
|
||||||
|
/* but preserve the settings, for they worked... */
|
||||||
|
c->io[0].end = resource_size(&tmp);
|
||||||
|
c->io[0].start = tmp.start;
|
||||||
|
c->io[0].flags = tmp.flags;
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
} else
|
} else
|
||||||
|
|
|
||||||
|
|
@ -646,7 +646,7 @@ static int __devinit pd6729_pci_probe(struct pci_dev *dev,
|
||||||
if (!pci_resource_start(dev, 0)) {
|
if (!pci_resource_start(dev, 0)) {
|
||||||
dev_warn(&dev->dev, "refusing to load the driver as the "
|
dev_warn(&dev->dev, "refusing to load the driver as the "
|
||||||
"io_base is NULL.\n");
|
"io_base is NULL.\n");
|
||||||
goto err_out_free_mem;
|
goto err_out_disable;
|
||||||
}
|
}
|
||||||
|
|
||||||
dev_info(&dev->dev, "Cirrus PD6729 PCI to PCMCIA Bridge at 0x%llx "
|
dev_info(&dev->dev, "Cirrus PD6729 PCI to PCMCIA Bridge at 0x%llx "
|
||||||
|
|
|
||||||
|
|
@ -1154,7 +1154,7 @@ static struct net_device *ctcm_init_netdevice(struct ctcm_priv *priv)
|
||||||
dev_fsm, dev_fsm_len, GFP_KERNEL);
|
dev_fsm, dev_fsm_len, GFP_KERNEL);
|
||||||
if (priv->fsm == NULL) {
|
if (priv->fsm == NULL) {
|
||||||
CTCMY_DBF_DEV(SETUP, dev, "init_fsm error");
|
CTCMY_DBF_DEV(SETUP, dev, "init_fsm error");
|
||||||
kfree(dev);
|
free_netdev(dev);
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
fsm_newstate(priv->fsm, DEV_STATE_STOPPED);
|
fsm_newstate(priv->fsm, DEV_STATE_STOPPED);
|
||||||
|
|
@ -1165,7 +1165,7 @@ static struct net_device *ctcm_init_netdevice(struct ctcm_priv *priv)
|
||||||
grp = ctcmpc_init_mpc_group(priv);
|
grp = ctcmpc_init_mpc_group(priv);
|
||||||
if (grp == NULL) {
|
if (grp == NULL) {
|
||||||
MPC_DBF_DEV(SETUP, dev, "init_mpc_group error");
|
MPC_DBF_DEV(SETUP, dev, "init_mpc_group error");
|
||||||
kfree(dev);
|
free_netdev(dev);
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
tasklet_init(&grp->mpc_tasklet2,
|
tasklet_init(&grp->mpc_tasklet2,
|
||||||
|
|
|
||||||
|
|
@ -2017,6 +2017,7 @@ ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
|
||||||
struct ioc3_port *port;
|
struct ioc3_port *port;
|
||||||
struct ioc3_port *ports[PORTS_PER_CARD];
|
struct ioc3_port *ports[PORTS_PER_CARD];
|
||||||
int phys_port;
|
int phys_port;
|
||||||
|
int cnt;
|
||||||
|
|
||||||
DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, is, idd));
|
DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, is, idd));
|
||||||
|
|
||||||
|
|
@ -2146,6 +2147,9 @@ ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
|
||||||
|
|
||||||
/* error exits that give back resources */
|
/* error exits that give back resources */
|
||||||
out4:
|
out4:
|
||||||
|
for (cnt = 0; cnt < phys_port; cnt++)
|
||||||
|
kfree(ports[cnt]);
|
||||||
|
|
||||||
kfree(card_ptr);
|
kfree(card_ptr);
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -243,7 +243,7 @@ static int get_rx_bufs(struct vhost_virtqueue *vq,
|
||||||
int r, nlogs = 0;
|
int r, nlogs = 0;
|
||||||
|
|
||||||
while (datalen > 0) {
|
while (datalen > 0) {
|
||||||
if (unlikely(headcount >= VHOST_NET_MAX_SG)) {
|
if (unlikely(seg >= VHOST_NET_MAX_SG)) {
|
||||||
r = -ENOBUFS;
|
r = -ENOBUFS;
|
||||||
goto err;
|
goto err;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -858,11 +858,12 @@ int vhost_log_write(struct vhost_virtqueue *vq, struct vhost_log *log,
|
||||||
if (r < 0)
|
if (r < 0)
|
||||||
return r;
|
return r;
|
||||||
len -= l;
|
len -= l;
|
||||||
if (!len)
|
if (!len) {
|
||||||
|
if (vq->log_ctx)
|
||||||
|
eventfd_signal(vq->log_ctx, 1);
|
||||||
return 0;
|
return 0;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
if (vq->log_ctx)
|
|
||||||
eventfd_signal(vq->log_ctx, 1);
|
|
||||||
/* Length written exceeds what we have stored. This is a bug. */
|
/* Length written exceeds what we have stored. This is a bug. */
|
||||||
BUG();
|
BUG();
|
||||||
return 0;
|
return 0;
|
||||||
|
|
|
||||||
|
|
@ -298,8 +298,8 @@ static void set_dma_control0(struct pxa168fb_info *fbi)
|
||||||
* Set bit to enable graphics DMA.
|
* Set bit to enable graphics DMA.
|
||||||
*/
|
*/
|
||||||
x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
|
x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
|
||||||
x |= fbi->active ? 0x00000100 : 0;
|
x &= ~CFG_GRA_ENA_MASK;
|
||||||
fbi->active = 0;
|
x |= fbi->active ? CFG_GRA_ENA(1) : CFG_GRA_ENA(0);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* If we are in a pseudo-color mode, we need to enable
|
* If we are in a pseudo-color mode, we need to enable
|
||||||
|
|
|
||||||
|
|
@ -27,8 +27,6 @@
|
||||||
|
|
||||||
#define MAX_LINKS 32
|
#define MAX_LINKS 32
|
||||||
|
|
||||||
struct net;
|
|
||||||
|
|
||||||
struct sockaddr_nl {
|
struct sockaddr_nl {
|
||||||
sa_family_t nl_family; /* AF_NETLINK */
|
sa_family_t nl_family; /* AF_NETLINK */
|
||||||
unsigned short nl_pad; /* zero */
|
unsigned short nl_pad; /* zero */
|
||||||
|
|
@ -151,6 +149,8 @@ struct nlattr {
|
||||||
#include <linux/capability.h>
|
#include <linux/capability.h>
|
||||||
#include <linux/skbuff.h>
|
#include <linux/skbuff.h>
|
||||||
|
|
||||||
|
struct net;
|
||||||
|
|
||||||
static inline struct nlmsghdr *nlmsg_hdr(const struct sk_buff *skb)
|
static inline struct nlmsghdr *nlmsg_hdr(const struct sk_buff *skb)
|
||||||
{
|
{
|
||||||
return (struct nlmsghdr *)skb->data;
|
return (struct nlmsghdr *)skb->data;
|
||||||
|
|
|
||||||
|
|
@ -393,6 +393,9 @@
|
||||||
#define PCI_DEVICE_ID_VLSI_82C147 0x0105
|
#define PCI_DEVICE_ID_VLSI_82C147 0x0105
|
||||||
#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702
|
#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702
|
||||||
|
|
||||||
|
/* AMD RD890 Chipset */
|
||||||
|
#define PCI_DEVICE_ID_RD890_IOMMU 0x5a23
|
||||||
|
|
||||||
#define PCI_VENDOR_ID_ADL 0x1005
|
#define PCI_VENDOR_ID_ADL 0x1005
|
||||||
#define PCI_DEVICE_ID_ADL_2301 0x2301
|
#define PCI_DEVICE_ID_ADL_2301 0x2301
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -322,7 +322,7 @@ extern int csum_partial_copy_fromiovecend(unsigned char *kdata,
|
||||||
int offset,
|
int offset,
|
||||||
unsigned int len, __wsum *csump);
|
unsigned int len, __wsum *csump);
|
||||||
|
|
||||||
extern int verify_iovec(struct msghdr *m, struct iovec *iov, struct sockaddr *address, int mode);
|
extern long verify_iovec(struct msghdr *m, struct iovec *iov, struct sockaddr *address, int mode);
|
||||||
extern int memcpy_toiovec(struct iovec *v, unsigned char *kdata, int len);
|
extern int memcpy_toiovec(struct iovec *v, unsigned char *kdata, int len);
|
||||||
extern int memcpy_toiovecend(const struct iovec *v, unsigned char *kdata,
|
extern int memcpy_toiovecend(const struct iovec *v, unsigned char *kdata,
|
||||||
int offset, int len);
|
int offset, int len);
|
||||||
|
|
|
||||||
|
|
@ -121,6 +121,7 @@ static inline int addrconf_finite_timeout(unsigned long timeout)
|
||||||
* IPv6 Address Label subsystem (addrlabel.c)
|
* IPv6 Address Label subsystem (addrlabel.c)
|
||||||
*/
|
*/
|
||||||
extern int ipv6_addr_label_init(void);
|
extern int ipv6_addr_label_init(void);
|
||||||
|
extern void ipv6_addr_label_cleanup(void);
|
||||||
extern void ipv6_addr_label_rtnl_register(void);
|
extern void ipv6_addr_label_rtnl_register(void);
|
||||||
extern u32 ipv6_addr_label(struct net *net,
|
extern u32 ipv6_addr_label(struct net *net,
|
||||||
const struct in6_addr *addr,
|
const struct in6_addr *addr,
|
||||||
|
|
|
||||||
|
|
@ -242,6 +242,7 @@ static inline void skb_tunnel_rx(struct sk_buff *skb, struct net_device *dev)
|
||||||
dev->stats.rx_packets++;
|
dev->stats.rx_packets++;
|
||||||
dev->stats.rx_bytes += skb->len;
|
dev->stats.rx_bytes += skb->len;
|
||||||
skb->rxhash = 0;
|
skb->rxhash = 0;
|
||||||
|
skb_set_queue_mapping(skb, 0);
|
||||||
skb_dst_drop(skb);
|
skb_dst_drop(skb);
|
||||||
nf_reset(skb);
|
nf_reset(skb);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -199,6 +199,8 @@ static inline int ip_route_newports(struct rtable **rp, u8 protocol,
|
||||||
fl.fl_ip_sport = sport;
|
fl.fl_ip_sport = sport;
|
||||||
fl.fl_ip_dport = dport;
|
fl.fl_ip_dport = dport;
|
||||||
fl.proto = protocol;
|
fl.proto = protocol;
|
||||||
|
if (inet_sk(sk)->transparent)
|
||||||
|
fl.flags |= FLOWI_FLAG_ANYSRC;
|
||||||
ip_rt_put(*rp);
|
ip_rt_put(*rp);
|
||||||
*rp = NULL;
|
*rp = NULL;
|
||||||
security_sk_classify_flow(sk, &fl);
|
security_sk_classify_flow(sk, &fl);
|
||||||
|
|
|
||||||
|
|
@ -298,8 +298,8 @@ struct xfrm_state_afinfo {
|
||||||
const struct xfrm_type *type_map[IPPROTO_MAX];
|
const struct xfrm_type *type_map[IPPROTO_MAX];
|
||||||
struct xfrm_mode *mode_map[XFRM_MODE_MAX];
|
struct xfrm_mode *mode_map[XFRM_MODE_MAX];
|
||||||
int (*init_flags)(struct xfrm_state *x);
|
int (*init_flags)(struct xfrm_state *x);
|
||||||
void (*init_tempsel)(struct xfrm_state *x, struct flowi *fl,
|
void (*init_tempsel)(struct xfrm_selector *sel, struct flowi *fl);
|
||||||
struct xfrm_tmpl *tmpl,
|
void (*init_temprop)(struct xfrm_state *x, struct xfrm_tmpl *tmpl,
|
||||||
xfrm_address_t *daddr, xfrm_address_t *saddr);
|
xfrm_address_t *daddr, xfrm_address_t *saddr);
|
||||||
int (*tmpl_sort)(struct xfrm_tmpl **dst, struct xfrm_tmpl **src, int n);
|
int (*tmpl_sort)(struct xfrm_tmpl **dst, struct xfrm_tmpl **src, int n);
|
||||||
int (*state_sort)(struct xfrm_state **dst, struct xfrm_state **src, int n);
|
int (*state_sort)(struct xfrm_state **dst, struct xfrm_state **src, int n);
|
||||||
|
|
|
||||||
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