From c0f8584f0553f3e7b37270d203b3ad8fc7bd1262 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 17 Oct 2018 12:00:33 +0200 Subject: [PATCH] clk: renesas: r8a77995: Simplify PLL3 multiplier/divider 116/6 can be simplified to 58/3. Signed-off-by: Geert Uytterhoeven Acked-by: Stephen Boyd --- drivers/clk/renesas/r8a77995-cpg-mssr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index b9745665731f..eee3874865a9 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -191,14 +191,14 @@ static const unsigned int r8a77995_crit_mod_clks[] __initconst = { * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 *-------------------------------------------------------------------- * 0 48 x 1 x250/4 x100/3 x100/3 - * 1 48 x 1 x250/4 x100/3 x116/6 + * 1 48 x 1 x250/4 x100/3 x58/3 */ #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div */ { 1, 100, 3, 100, 3, }, - { 1, 100, 3, 116, 6, }, + { 1, 100, 3, 58, 3, }, }; static int __init r8a77995_cpg_mssr_init(struct device *dev)