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Merge branch 'for-4.18/alps' into for-linus 

hid-alps driver cleanups wrt. t4_read_write_register() handling
from Christophe Jaillet
This commit is contained in:
Jiri Kosina 2018-06-08 10:20:42 +02:00
Родитель d6c70a86bc a317e55957
Коммит c1144d29f4
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428
.clang-format Normal file
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@ -0,0 +1,428 @@
# SPDX-License-Identifier: GPL-2.0
#
# clang-format configuration file. Intended for clang-format >= 4.
#
# For more information, see:
#
# Documentation/process/clang-format.rst
# https://clang.llvm.org/docs/ClangFormat.html
# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
#
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BreakBeforeBinaryOperators: None
BreakBeforeBraces: Custom
#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0
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DisableFormat: false
ExperimentalAutoDetectBinPacking: false
#FixNamespaceComments: false # Unknown to clang-format-4.0
# Taken from:
# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \
# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \
# | sort | uniq
ForEachMacros:
- 'apei_estatus_for_each_section'
- 'ata_for_each_dev'
- 'ata_for_each_link'
- 'ax25_for_each'
- 'ax25_uid_for_each'
- 'bio_for_each_integrity_vec'
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- 'bio_list_for_each'
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- 'btree_for_each_safe128'
- 'btree_for_each_safe32'
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- 'cpufreq_for_each_entry'
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- 'cpufreq_for_each_valid_entry'
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- 'css_for_each_child'
- 'css_for_each_descendant_post'
- 'css_for_each_descendant_pre'
- 'device_for_each_child_node'
- 'drm_atomic_crtc_for_each_plane'
- 'drm_atomic_crtc_state_for_each_plane'
- 'drm_atomic_crtc_state_for_each_plane_state'
- 'drm_for_each_connector_iter'
- 'drm_for_each_crtc'
- 'drm_for_each_encoder'
- 'drm_for_each_encoder_mask'
- 'drm_for_each_fb'
- 'drm_for_each_legacy_plane'
- 'drm_for_each_plane'
- 'drm_for_each_plane_mask'
- 'drm_mm_for_each_hole'
- 'drm_mm_for_each_node'
- 'drm_mm_for_each_node_in_range'
- 'drm_mm_for_each_node_safe'
- 'for_each_active_drhd_unit'
- 'for_each_active_iommu'
- 'for_each_available_child_of_node'
- 'for_each_bio'
- 'for_each_board_func_rsrc'
- 'for_each_bvec'
- 'for_each_child_of_node'
- 'for_each_clear_bit'
- 'for_each_clear_bit_from'
- 'for_each_cmsghdr'
- 'for_each_compatible_node'
- 'for_each_console'
- 'for_each_cpu'
- 'for_each_cpu_and'
- 'for_each_cpu_not'
- 'for_each_cpu_wrap'
- 'for_each_dev_addr'
- 'for_each_dma_cap_mask'
- 'for_each_drhd_unit'
- 'for_each_dss_dev'
- 'for_each_efi_memory_desc'
- 'for_each_efi_memory_desc_in_map'
- 'for_each_endpoint_of_node'
- 'for_each_evictable_lru'
- 'for_each_fib6_node_rt_rcu'
- 'for_each_fib6_walker_rt'
- 'for_each_free_mem_range'
- 'for_each_free_mem_range_reverse'
- 'for_each_func_rsrc'
- 'for_each_hstate'
- 'for_each_if'
- 'for_each_iommu'
- 'for_each_ip_tunnel_rcu'
- 'for_each_irq_nr'
- 'for_each_lru'
- 'for_each_matching_node'
- 'for_each_matching_node_and_match'
- 'for_each_memblock'
- 'for_each_memblock_type'
- 'for_each_memcg_cache_index'
- 'for_each_mem_pfn_range'
- 'for_each_mem_range'
- 'for_each_mem_range_rev'
- 'for_each_migratetype_order'
- 'for_each_msi_entry'
- 'for_each_net'
- 'for_each_netdev'
- 'for_each_netdev_continue'
- 'for_each_netdev_continue_rcu'
- 'for_each_netdev_feature'
- 'for_each_netdev_in_bond_rcu'
- 'for_each_netdev_rcu'
- 'for_each_netdev_reverse'
- 'for_each_netdev_safe'
- 'for_each_net_rcu'
- 'for_each_new_connector_in_state'
- 'for_each_new_crtc_in_state'
- 'for_each_new_plane_in_state'
- 'for_each_new_private_obj_in_state'
- 'for_each_node'
- 'for_each_node_by_name'
- 'for_each_node_by_type'
- 'for_each_node_mask'
- 'for_each_node_state'
- 'for_each_node_with_cpus'
- 'for_each_node_with_property'
- 'for_each_of_allnodes'
- 'for_each_of_allnodes_from'
- 'for_each_of_pci_range'
- 'for_each_old_connector_in_state'
- 'for_each_old_crtc_in_state'
- 'for_each_oldnew_connector_in_state'
- 'for_each_oldnew_crtc_in_state'
- 'for_each_oldnew_plane_in_state'
- 'for_each_oldnew_private_obj_in_state'
- 'for_each_old_plane_in_state'
- 'for_each_old_private_obj_in_state'
- 'for_each_online_cpu'
- 'for_each_online_node'
- 'for_each_online_pgdat'
- 'for_each_pci_bridge'
- 'for_each_pci_dev'
- 'for_each_pci_msi_entry'
- 'for_each_populated_zone'
- 'for_each_possible_cpu'
- 'for_each_present_cpu'
- 'for_each_prime_number'
- 'for_each_prime_number_from'
- 'for_each_process'
- 'for_each_process_thread'
- 'for_each_property_of_node'
- 'for_each_reserved_mem_region'
- 'for_each_resv_unavail_range'
- 'for_each_rtdcom'
- 'for_each_rtdcom_safe'
- 'for_each_set_bit'
- 'for_each_set_bit_from'
- 'for_each_sg'
- 'for_each_sg_page'
- '__for_each_thread'
- 'for_each_thread'
- 'for_each_zone'
- 'for_each_zone_zonelist'
- 'for_each_zone_zonelist_nodemask'
- 'fwnode_for_each_available_child_node'
- 'fwnode_for_each_child_node'
- 'fwnode_graph_for_each_endpoint'
- 'gadget_for_each_ep'
- 'hash_for_each'
- 'hash_for_each_possible'
- 'hash_for_each_possible_rcu'
- 'hash_for_each_possible_rcu_notrace'
- 'hash_for_each_possible_safe'
- 'hash_for_each_rcu'
- 'hash_for_each_safe'
- 'hctx_for_each_ctx'
- 'hlist_bl_for_each_entry'
- 'hlist_bl_for_each_entry_rcu'
- 'hlist_bl_for_each_entry_safe'
- 'hlist_for_each'
- 'hlist_for_each_entry'
- 'hlist_for_each_entry_continue'
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- 'hlist_for_each_entry_continue_rcu_bh'
- 'hlist_for_each_entry_from'
- 'hlist_for_each_entry_from_rcu'
- 'hlist_for_each_entry_rcu'
- 'hlist_for_each_entry_rcu_bh'
- 'hlist_for_each_entry_rcu_notrace'
- 'hlist_for_each_entry_safe'
- '__hlist_for_each_rcu'
- 'hlist_for_each_safe'
- 'hlist_nulls_for_each_entry'
- 'hlist_nulls_for_each_entry_from'
- 'hlist_nulls_for_each_entry_rcu'
- 'hlist_nulls_for_each_entry_safe'
- 'ide_host_for_each_port'
- 'ide_port_for_each_dev'
- 'ide_port_for_each_present_dev'
- 'idr_for_each_entry'
- 'idr_for_each_entry_continue'
- 'idr_for_each_entry_ul'
- 'inet_bind_bucket_for_each'
- 'inet_lhash2_for_each_icsk_rcu'
- 'iov_for_each'
- 'key_for_each'
- 'key_for_each_safe'
- 'klp_for_each_func'
- 'klp_for_each_object'
- 'kvm_for_each_memslot'
- 'kvm_for_each_vcpu'
- 'list_for_each'
- 'list_for_each_entry'
- 'list_for_each_entry_continue'
- 'list_for_each_entry_continue_rcu'
- 'list_for_each_entry_continue_reverse'
- 'list_for_each_entry_from'
- 'list_for_each_entry_from_reverse'
- 'list_for_each_entry_lockless'
- 'list_for_each_entry_rcu'
- 'list_for_each_entry_reverse'
- 'list_for_each_entry_safe'
- 'list_for_each_entry_safe_continue'
- 'list_for_each_entry_safe_from'
- 'list_for_each_entry_safe_reverse'
- 'list_for_each_prev'
- 'list_for_each_prev_safe'
- 'list_for_each_safe'
- 'llist_for_each'
- 'llist_for_each_entry'
- 'llist_for_each_entry_safe'
- 'llist_for_each_safe'
- 'media_device_for_each_entity'
- 'media_device_for_each_intf'
- 'media_device_for_each_link'
- 'media_device_for_each_pad'
- 'netdev_for_each_lower_dev'
- 'netdev_for_each_lower_private'
- 'netdev_for_each_lower_private_rcu'
- 'netdev_for_each_mc_addr'
- 'netdev_for_each_uc_addr'
- 'netdev_for_each_upper_dev_rcu'
- 'netdev_hw_addr_list_for_each'
- 'nft_rule_for_each_expr'
- 'nla_for_each_attr'
- 'nla_for_each_nested'
- 'nlmsg_for_each_attr'
- 'nlmsg_for_each_msg'
- 'nr_neigh_for_each'
- 'nr_neigh_for_each_safe'
- 'nr_node_for_each'
- 'nr_node_for_each_safe'
- 'of_for_each_phandle'
- 'of_property_for_each_string'
- 'of_property_for_each_u32'
- 'pci_bus_for_each_resource'
- 'ping_portaddr_for_each_entry'
- 'plist_for_each'
- 'plist_for_each_continue'
- 'plist_for_each_entry'
- 'plist_for_each_entry_continue'
- 'plist_for_each_entry_safe'
- 'plist_for_each_safe'
- 'pnp_for_each_card'
- 'pnp_for_each_dev'
- 'protocol_for_each_card'
- 'protocol_for_each_dev'
- 'queue_for_each_hw_ctx'
- 'radix_tree_for_each_contig'
- 'radix_tree_for_each_slot'
- 'radix_tree_for_each_tagged'
- 'rbtree_postorder_for_each_entry_safe'
- 'resource_list_for_each_entry'
- 'resource_list_for_each_entry_safe'
- 'rhl_for_each_entry_rcu'
- 'rhl_for_each_rcu'
- 'rht_for_each'
- 'rht_for_each_continue'
- 'rht_for_each_entry'
- 'rht_for_each_entry_continue'
- 'rht_for_each_entry_rcu'
- 'rht_for_each_entry_rcu_continue'
- 'rht_for_each_entry_safe'
- 'rht_for_each_rcu'
- 'rht_for_each_rcu_continue'
- '__rq_for_each_bio'
- 'rq_for_each_segment'
- 'scsi_for_each_prot_sg'
- 'scsi_for_each_sg'
- 'sctp_for_each_hentry'
- 'sctp_skb_for_each'
- 'shdma_for_each_chan'
- '__shost_for_each_device'
- 'shost_for_each_device'
- 'sk_for_each'
- 'sk_for_each_bound'
- 'sk_for_each_entry_offset_rcu'
- 'sk_for_each_from'
- 'sk_for_each_rcu'
- 'sk_for_each_safe'
- 'sk_nulls_for_each'
- 'sk_nulls_for_each_from'
- 'sk_nulls_for_each_rcu'
- 'snd_pcm_group_for_each_entry'
- 'snd_soc_dapm_widget_for_each_path'
- 'snd_soc_dapm_widget_for_each_path_safe'
- 'snd_soc_dapm_widget_for_each_sink_path'
- 'snd_soc_dapm_widget_for_each_source_path'
- 'tb_property_for_each'
- 'udp_portaddr_for_each_entry'
- 'udp_portaddr_for_each_entry_rcu'
- 'usb_hub_for_each_child'
- 'v4l2_device_for_each_subdev'
- 'v4l2_m2m_for_each_dst_buf'
- 'v4l2_m2m_for_each_dst_buf_safe'
- 'v4l2_m2m_for_each_src_buf'
- 'v4l2_m2m_for_each_src_buf_safe'
- 'zorro_for_each_dev'
#IncludeBlocks: Preserve # Unknown to clang-format-5.0
IncludeCategories:
- Regex: '.*'
Priority: 1
IncludeIsMainRegex: '(Test)?$'
IndentCaseLabels: false
#IndentPPDirectives: None # Unknown to clang-format-5.0
IndentWidth: 8
IndentWrappedFunctionNames: true
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: false
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: Inner
#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0
ObjCBlockIndentWidth: 8
ObjCSpaceAfterProperty: true
ObjCSpaceBeforeProtocolList: true
# Taken from git's rules
#PenaltyBreakAssignment: 10 # Unknown to clang-format-4.0
PenaltyBreakBeforeFirstCallParameter: 30
PenaltyBreakComment: 10
PenaltyBreakFirstLessLess: 0
PenaltyBreakString: 10
PenaltyExcessCharacter: 100
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
ReflowComments: false
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#SortUsingDeclarations: false # Unknown to clang-format-4.0
SpaceAfterCStyleCast: false
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#SpaceBeforeCtorInitializerColon: true # Unknown to clang-format-5.0
#SpaceBeforeInheritanceColon: true # Unknown to clang-format-5.0
SpaceBeforeParens: ControlStatements
#SpaceBeforeRangeBasedForLoopColon: true # Unknown to clang-format-5.0
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
SpacesInContainerLiterals: false
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
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Standard: Cpp03
TabWidth: 8
UseTab: Always
...

8
.gitignore поставляемый
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@ -11,6 +11,7 @@
#
.*
*.a
*.asn1.[ch]
*.bin
*.bz2
*.c.[012]*.*
@ -22,6 +23,7 @@
*.gz
*.i
*.ko
*.lex.c
*.ll
*.lst
*.lz4
@ -37,6 +39,7 @@
*.so.dbg
*.su
*.symtypes
*.tab.[ch]
*.tar
*.xz
Module.symvers
@ -81,6 +84,7 @@ modules.builtin
!.gitignore
!.mailmap
!.cocciconfig
!.clang-format
#
# Generated include files
@ -128,7 +132,3 @@ all.config
# Kdevelop4
*.kdev4
#Automatically generated by ASN.1 compiler
net/ipv4/netfilter/nf_nat_snmp_basic-asn1.c
net/ipv4/netfilter/nf_nat_snmp_basic-asn1.h

9
.mailmap
Просмотреть файл

@ -34,9 +34,9 @@ Axel Lin <axel.lin@gmail.com>
Ben Gardner <bgardner@wabtec.com>
Ben M Cahill <ben.m.cahill@intel.com>
Björn Steinbrink <B.Steinbrink@gmx.de>
Boris Brezillon <boris.brezillon@free-electrons.com>
Boris Brezillon <boris.brezillon@free-electrons.com> <b.brezillon.dev@gmail.com>
Boris Brezillon <boris.brezillon@free-electrons.com> <b.brezillon@overkiz.com>
Boris Brezillon <boris.brezillon@bootlin.com> <boris.brezillon@free-electrons.com>
Boris Brezillon <boris.brezillon@bootlin.com> <b.brezillon.dev@gmail.com>
Boris Brezillon <boris.brezillon@bootlin.com> <b.brezillon@overkiz.com>
Brian Avery <b.avery@hp.com>
Brian King <brking@us.ibm.com>
Christoph Hellwig <hch@lst.de>
@ -102,6 +102,8 @@ Koushik <raghavendra.koushik@neterion.com>
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Leon Romanovsky <leon@kernel.org> <leon@leon.nu>
Leon Romanovsky <leon@kernel.org> <leonro@mellanox.com>
Leonid I Ananiev <leonid.i.ananiev@intel.com>
Linas Vepstas <linas@austin.ibm.com>
Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
@ -128,6 +130,7 @@ Mayuresh Janorkar <mayur@ti.com>
Michael Buesch <m@bues.ch>
Michel Dänzer <michel@tungstengraphics.com>
Miodrag Dinic <miodrag.dinic@mips.com> <miodrag.dinic@imgtec.com>
Miquel Raynal <miquel.raynal@bootlin.com> <miquel.raynal@free-electrons.com>
Mitesh shah <mshah@teja.com>
Mohit Kumar <mohit.kumar@st.com> <mohit.kumar.dhaka@gmail.com>
Morten Welinder <terra@gnome.org>

2
Documentation/ABI/testing/ima_policy
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@ -26,7 +26,7 @@ Description:
[obj_user=] [obj_role=] [obj_type=]]
option: [[appraise_type=]] [permit_directio]
base: func:= [BPRM_CHECK][MMAP_CHECK][FILE_CHECK][MODULE_CHECK]
base: func:= [BPRM_CHECK][MMAP_CHECK][CREDS_CHECK][FILE_CHECK][MODULE_CHECK]
[FIRMWARE_CHECK]
[KEXEC_KERNEL_CHECK] [KEXEC_INITRAMFS_CHECK]
mask:= [[^]MAY_READ] [[^]MAY_WRITE] [[^]MAY_APPEND]

16
Documentation/ABI/testing/sysfs-class-rtc
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@ -43,6 +43,14 @@ Contact: linux-rtc@vger.kernel.org
Description:
(RO) The name of the RTC corresponding to this sysfs directory
What: /sys/class/rtc/rtcX/range
Date: January 2018
KernelVersion: 4.16
Contact: linux-rtc@vger.kernel.org
Description:
Valid time range for the RTC, as seconds from epoch, formatted
as [min, max]
What: /sys/class/rtc/rtcX/since_epoch
Date: March 2006
KernelVersion: 2.6.17
@ -57,14 +65,6 @@ Contact: linux-rtc@vger.kernel.org
Description:
(RO) RTC-provided time in 24-hour notation (hh:mm:ss)
What: /sys/class/rtc/rtcX/*/nvmem
Date: February 2016
KernelVersion: 4.6
Contact: linux-rtc@vger.kernel.org
Description:
(RW) The non volatile storage exported as a raw file, as
described in Documentation/nvmem/nvmem.txt
What: /sys/class/rtc/rtcX/offset
Date: February 2016
KernelVersion: 4.6

885
Documentation/ABI/testing/sysfs-driver-ufs Normal file
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@ -0,0 +1,885 @@
What: /sys/bus/*/drivers/ufshcd/*/auto_hibern8
Date: March 2018
Contact: linux-scsi@vger.kernel.org
Description:
This file contains the auto-hibernate idle timer setting of a
UFS host controller. A value of '0' means auto-hibernate is not
enabled. Otherwise the value is the number of microseconds of
idle time before the UFS host controller will autonomously put
the link into hibernate state. That will save power at the
expense of increased latency. Note that the hardware supports
10-bit values with a power-of-ten multiplier which allows a
maximum value of 102300000. Refer to the UFS Host Controller
Interface specification for more details.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/device_type
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the device type. This is one of the UFS
device descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/device_class
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the device class. This is one of the UFS
device descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/device_sub_class
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the UFS storage subclass. This is one of
the UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/protocol
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the protocol supported by an UFS device.
This is one of the UFS device descriptor parameters.
The full information about the descriptor could be found
at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/number_of_luns
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows number of logical units. This is one of
the UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/number_of_wluns
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows number of well known logical units.
This is one of the UFS device descriptor parameters.
The full information about the descriptor could be found
at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/boot_enable
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows value that indicates whether the device is
enabled for boot. This is one of the UFS device descriptor
parameters. The full information about the descriptor could
be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/descriptor_access_enable
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows value that indicates whether the device
descriptor could be read after partial initialization phase
of the boot sequence. This is one of the UFS device descriptor
parameters. The full information about the descriptor could
be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/initial_power_mode
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows value that defines the power mode after
device initialization or hardware reset. This is one of
the UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/high_priority_lun
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the high priority lun. This is one of
the UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/secure_removal_type
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the secure removal type. This is one of
the UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/support_security_lun
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows whether the security lun is supported.
This is one of the UFS device descriptor parameters.
The full information about the descriptor could be found
at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/bkops_termination_latency
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the background operations termination
latency. This is one of the UFS device descriptor parameters.
The full information about the descriptor could be found
at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/initial_active_icc_level
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the initial active ICC level. This is one
of the UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/specification_version
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the specification version. This is one
of the UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/manufacturing_date
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the manufacturing date in BCD format.
This is one of the UFS device descriptor parameters.
The full information about the descriptor could be found
at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/manufacturer_id
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the manufacturee ID. This is one of the
UFS device descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/rtt_capability
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the maximum number of outstanding RTTs
supported by the device. This is one of the UFS device
descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/rtc_update
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the frequency and method of the realtime
clock update. This is one of the UFS device descriptor
parameters. The full information about the descriptor
could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/ufs_features
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows which features are supported by the device.
This is one of the UFS device descriptor parameters.
The full information about the descriptor could be
found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/ffu_timeout
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the FFU timeout. This is one of the
UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/queue_depth
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the device queue depth. This is one of the
UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/device_version
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the device version. This is one of the
UFS device descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/number_of_secure_wpa
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows number of secure write protect areas
supported by the device. This is one of the UFS device
descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/psa_max_data_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the maximum amount of data that may be
written during the pre-soldering phase of the PSA flow.
This is one of the UFS device descriptor parameters.
The full information about the descriptor could be found
at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/psa_state_timeout
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the command maximum timeout for a change
in PSA state. This is one of the UFS device descriptor
parameters. The full information about the descriptor could
be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/interconnect_descriptor/unipro_version
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the MIPI UniPro version number in BCD format.
This is one of the UFS interconnect descriptor parameters.
The full information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/interconnect_descriptor/mphy_version
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the MIPI M-PHY version number in BCD format.
This is one of the UFS interconnect descriptor parameters.
The full information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/raw_device_capacity
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the total memory quantity available to
the user to configure the device logical units. This is one
of the UFS geometry descriptor parameters. The full
information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/max_number_of_luns
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the maximum number of logical units
supported by the UFS device. This is one of the UFS
geometry descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/segment_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the segment size. This is one of the UFS
geometry descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/allocation_unit_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the allocation unit size. This is one of
the UFS geometry descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/min_addressable_block_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the minimum addressable block size. This
is one of the UFS geometry descriptor parameters. The full
information about the descriptor could be found at UFS
specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/optimal_read_block_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the optimal read block size. This is one
of the UFS geometry descriptor parameters. The full
information about the descriptor could be found at UFS
specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/optimal_write_block_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the optimal write block size. This is one
of the UFS geometry descriptor parameters. The full
information about the descriptor could be found at UFS
specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/max_in_buffer_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the maximum data-in buffer size. This
is one of the UFS geometry descriptor parameters. The full
information about the descriptor could be found at UFS
specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/max_out_buffer_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the maximum data-out buffer size. This
is one of the UFS geometry descriptor parameters. The full
information about the descriptor could be found at UFS
specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/rpmb_rw_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the maximum number of RPMB frames allowed
in Security Protocol In/Out. This is one of the UFS geometry
descriptor parameters. The full information about the
descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/dyn_capacity_resource_policy
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the dynamic capacity resource policy. This
is one of the UFS geometry descriptor parameters. The full
information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/data_ordering
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows support for out-of-order data transfer.
This is one of the UFS geometry descriptor parameters.
The full information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/max_number_of_contexts
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows maximum available number of contexts which
are supported by the device. This is one of the UFS geometry
descriptor parameters. The full information about the
descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/sys_data_tag_unit_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows system data tag unit size. This is one of
the UFS geometry descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/sys_data_tag_resource_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows maximum storage area size allocated by
the device to handle system data by the tagging mechanism.
This is one of the UFS geometry descriptor parameters.
The full information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/secure_removal_types
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows supported secure removal types. This is
one of the UFS geometry descriptor parameters. The full
information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/memory_types
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows supported memory types. This is one of
the UFS geometry descriptor parameters. The full
information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/*_memory_max_alloc_units
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the maximum number of allocation units for
different memory types (system code, non persistent,
enhanced type 1-4). This is one of the UFS geometry
descriptor parameters. The full information about the
descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/*_memory_capacity_adjustment_factor
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the memory capacity adjustment factor for
different memory types (system code, non persistent,
enhanced type 1-4). This is one of the UFS geometry
descriptor parameters. The full information about the
descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/health_descriptor/eol_info
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows preend of life information. This is one
of the UFS health descriptor parameters. The full
information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/health_descriptor/life_time_estimation_a
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows indication of the device life time
(method a). This is one of the UFS health descriptor
parameters. The full information about the descriptor
could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/health_descriptor/life_time_estimation_b
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows indication of the device life time
(method b). This is one of the UFS health descriptor
parameters. The full information about the descriptor
could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/power_descriptor/active_icc_levels_vcc*
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows maximum VCC, VCCQ and VCCQ2 value for
active ICC levels from 0 to 15. This is one of the UFS
power descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/manufacturer_name
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file contains a device manufactureer name string.
The full information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/product_name
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file contains a product name string. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/oem_id
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file contains a OEM ID string. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/serial_number
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file contains a device serial number string. The full
information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/product_revision
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file contains a product revision string. The full
information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/boot_lun_id
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows boot LUN information. This is one of
the UFS unit descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/lun_write_protect
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows LUN write protection status. This is one of
the UFS unit descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/lun_queue_depth
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows LUN queue depth. This is one of the UFS
unit descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/psa_sensitive
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows PSA sensitivity. This is one of the UFS
unit descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/lun_memory_type
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows LUN memory type. This is one of the UFS
unit descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/data_reliability
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file defines the device behavior when a power failure
occurs during a write operation. This is one of the UFS
unit descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/logical_block_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the size of addressable logical blocks
(calculated as an exponent with base 2). This is one of
the UFS unit descriptor parameters. The full information about
the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/logical_block_count
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows total number of addressable logical blocks.
This is one of the UFS unit descriptor parameters. The full
information about the descriptor could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/erase_block_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the erase block size. This is one of
the UFS unit descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/provisioning_type
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the thin provisioning type. This is one of
the UFS unit descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/physical_memory_resourse_count
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the total physical memory resources. This is
one of the UFS unit descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/context_capabilities
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the context capabilities. This is one of
the UFS unit descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/unit_descriptor/large_unit_granularity
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the granularity of the LUN. This is one of
the UFS unit descriptor parameters. The full information
about the descriptor could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/flags/device_init
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the device init status. The full information
about the flag could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/flags/permanent_wpe
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows whether permanent write protection is enabled.
The full information about the flag could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/flags/power_on_wpe
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows whether write protection is enabled on all
logical units configured as power on write protected. The
full information about the flag could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/flags/bkops_enable
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows whether the device background operations are
enabled. The full information about the flag could be
found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/flags/life_span_mode_enable
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows whether the device life span mode is enabled.
The full information about the flag could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/flags/phy_resource_removal
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows whether physical resource removal is enable.
The full information about the flag could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/flags/busy_rtc
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows whether the device is executing internal
operation related to real time clock. The full information
about the flag could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/flags/disable_fw_update
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows whether the device FW update is permanently
disabled. The full information about the flag could be found
at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/boot_lun_enabled
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the boot lun enabled UFS device attribute.
The full information about the attribute could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/current_power_mode
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the current power mode UFS device attribute.
The full information about the attribute could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/active_icc_level
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the active icc level UFS device attribute.
The full information about the attribute could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/ooo_data_enabled
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the out of order data transfer enabled UFS
device attribute. The full information about the attribute
could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/bkops_status
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the background operations status UFS device
attribute. The full information about the attribute could
be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/purge_status
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the purge operation status UFS device
attribute. The full information about the attribute could
be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/max_data_in_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the maximum data size in a DATA IN
UPIU. The full information about the attribute could
be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/max_data_out_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the maximum number of bytes that can be
requested with a READY TO TRANSFER UPIU. The full information
about the attribute could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/reference_clock_frequency
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the reference clock frequency UFS device
attribute. The full information about the attribute could
be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/configuration_descriptor_lock
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows whether the configuration descriptor is locked.
The full information about the attribute could be found at
UFS specifications 2.1. The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/max_number_of_rtt
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the maximum current number of
outstanding RTTs in device that is allowed. The full
information about the attribute could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/exception_event_control
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the exception event control UFS device
attribute. The full information about the attribute could
be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/exception_event_status
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the exception event status UFS device
attribute. The full information about the attribute could
be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/ffu_status
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file provides the ffu status UFS device attribute.
The full information about the attribute could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/psa_state
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file show the PSA feature status. The full information
about the attribute could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/attributes/psa_data_size
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the amount of data that the host plans to
load to all logical units in pre-soldering state.
The full information about the attribute could be found at
UFS specifications 2.1.
The file is read only.
What: /sys/class/scsi_device/*/device/dyn_cap_needed
Date: February 2018
Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
Description: This file shows the The amount of physical memory needed
to be removed from the physical memory resources pool of
the particular logical unit. The full information about
the attribute could be found at UFS specifications 2.1.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/rpm_lvl
Date: September 2014
Contact: Subhash Jadavani <subhashj@codeaurora.org>
Description: This entry could be used to set or show the UFS device
runtime power management level. The current driver
implementation supports 6 levels with next target states:
0 - an UFS device will stay active, an UIC link will
stay active
1 - an UFS device will stay active, an UIC link will
hibernate
2 - an UFS device will moved to sleep, an UIC link will
stay active
3 - an UFS device will moved to sleep, an UIC link will
hibernate
4 - an UFS device will be powered off, an UIC link will
hibernate
5 - an UFS device will be powered off, an UIC link will
be powered off
What: /sys/bus/platform/drivers/ufshcd/*/rpm_target_dev_state
Date: February 2018
Contact: Subhash Jadavani <subhashj@codeaurora.org>
Description: This entry shows the target power mode of an UFS device
for the chosen runtime power management level.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/rpm_target_link_state
Date: February 2018
Contact: Subhash Jadavani <subhashj@codeaurora.org>
Description: This entry shows the target state of an UFS UIC link
for the chosen runtime power management level.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/spm_lvl
Date: September 2014
Contact: Subhash Jadavani <subhashj@codeaurora.org>
Description: This entry could be used to set or show the UFS device
system power management level. The current driver
implementation supports 6 levels with next target states:
0 - an UFS device will stay active, an UIC link will
stay active
1 - an UFS device will stay active, an UIC link will
hibernate
2 - an UFS device will moved to sleep, an UIC link will
stay active
3 - an UFS device will moved to sleep, an UIC link will
hibernate
4 - an UFS device will be powered off, an UIC link will
hibernate
5 - an UFS device will be powered off, an UIC link will
be powered off
What: /sys/bus/platform/drivers/ufshcd/*/spm_target_dev_state
Date: February 2018
Contact: Subhash Jadavani <subhashj@codeaurora.org>
Description: This entry shows the target power mode of an UFS device
for the chosen system power management level.
The file is read only.
What: /sys/bus/platform/drivers/ufshcd/*/spm_target_link_state
Date: February 2018
Contact: Subhash Jadavani <subhashj@codeaurora.org>
Description: This entry shows the target state of an UFS UIC link
for the chosen system power management level.
The file is read only.

11
Documentation/ABI/testing/sysfs-fs-f2fs
Просмотреть файл

@ -192,3 +192,14 @@ Date: November 2017
Contact: "Sheng Yong" <shengyong1@huawei.com>
Description:
Controls readahead inode block in readdir.
What: /sys/fs/f2fs/<disk>/extension_list
Date: Feburary 2018
Contact: "Chao Yu" <yuchao0@huawei.com>
Description:
Used to control configure extension list:
- Query: cat /sys/fs/f2fs/<disk>/extension_list
- Add: echo '[h/c]extension' > /sys/fs/f2fs/<disk>/extension_list
- Del: echo '[h/c]!extension' > /sys/fs/f2fs/<disk>/extension_list
- [h] means add/del hot file extension
- [c] means add/del cold file extension

98
Documentation/admin-guide/kernel-parameters.txt
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@ -389,15 +389,15 @@
Use software keyboard repeat
audit= [KNL] Enable the audit sub-system
Format: { "0" | "1" } (0 = disabled, 1 = enabled)
0 - kernel audit is disabled and can not be enabled
until the next reboot
Format: { "0" | "1" | "off" | "on" }
0 | off - kernel audit is disabled and can not be
enabled until the next reboot
unset - kernel audit is initialized but disabled and
will be fully enabled by the userspace auditd.
1 - kernel audit is initialized and partially enabled,
storing at most audit_backlog_limit messages in
RAM until it is fully enabled by the userspace
auditd.
1 | on - kernel audit is initialized and partially
enabled, storing at most audit_backlog_limit
messages in RAM until it is fully enabled by the
userspace auditd.
Default: unset
audit_backlog_limit= [KNL] Set the audit queue size limit.
@ -1521,7 +1521,8 @@
ima_policy= [IMA]
The builtin policies to load during IMA setup.
Format: "tcb | appraise_tcb | secure_boot"
Format: "tcb | appraise_tcb | secure_boot |
fail_securely"
The "tcb" policy measures all programs exec'd, files
mmap'd for exec, and all files opened with the read
@ -1536,6 +1537,11 @@
of files (eg. kexec kernel image, kernel modules,
firmware, policy, etc) based on file signatures.
The "fail_securely" policy forces file signature
verification failure also on privileged mounted
filesystems with the SB_I_UNVERIFIABLE_SIGNATURE
flag.
ima_tcb [IMA] Deprecated. Use ima_policy= instead.
Load a policy which meets the needs of the Trusted
Computing Base. This means IMA will measure all
@ -1840,30 +1846,29 @@
keepinitrd [HW,ARM]
kernelcore= [KNL,X86,IA-64,PPC]
Format: nn[KMGTPE] | "mirror"
This parameter
specifies the amount of memory usable by the kernel
for non-movable allocations. The requested amount is
spread evenly throughout all nodes in the system. The
remaining memory in each node is used for Movable
pages. In the event, a node is too small to have both
kernelcore and Movable pages, kernelcore pages will
take priority and other nodes will have a larger number
of Movable pages. The Movable zone is used for the
allocation of pages that may be reclaimed or moved
by the page migration subsystem. This means that
HugeTLB pages may not be allocated from this zone.
Note that allocations like PTEs-from-HighMem still
use the HighMem zone if it exists, and the Normal
Format: nn[KMGTPE] | nn% | "mirror"
This parameter specifies the amount of memory usable by
the kernel for non-movable allocations. The requested
amount is spread evenly throughout all nodes in the
system as ZONE_NORMAL. The remaining memory is used for
movable memory in its own zone, ZONE_MOVABLE. In the
event, a node is too small to have both ZONE_NORMAL and
ZONE_MOVABLE, kernelcore memory will take priority and
other nodes will have a larger ZONE_MOVABLE.
ZONE_MOVABLE is used for the allocation of pages that
may be reclaimed or moved by the page migration
subsystem. Note that allocations like PTEs-from-HighMem
still use the HighMem zone if it exists, and the Normal
zone if it does not.
Instead of specifying the amount of memory (nn[KMGTPE]),
you can specify "mirror" option. In case "mirror"
It is possible to specify the exact amount of memory in
the form of "nn[KMGTPE]", a percentage of total system
memory in the form of "nn%", or "mirror". If "mirror"
option is specified, mirrored (reliable) memory is used
for non-movable allocations and remaining memory is used
for Movable pages. nn[KMGTPE] and "mirror" are exclusive,
so you can NOT specify nn[KMGTPE] and "mirror" at the same
time.
for Movable pages. "nn[KMGTPE]", "nn%", and "mirror"
are exclusive, so you cannot specify multiple forms.
kgdbdbgp= [KGDB,HW] kgdb over EHCI usb debug port.
Format: <Controller#>[,poll interval]
@ -1902,6 +1907,9 @@
kvm.ignore_msrs=[KVM] Ignore guest accesses to unhandled MSRs.
Default is 0 (don't ignore, but inject #GP)
kvm.enable_vmware_backdoor=[KVM] Support VMware backdoor PV interface.
Default is false (don't support).
kvm.mmu_audit= [KVM] This is a R/W parameter which allows audit
KVM MMU at runtime.
Default is 0 (off)
@ -2377,13 +2385,14 @@
mousedev.yres= [MOUSE] Vertical screen resolution, used for devices
reporting absolute coordinates, such as tablets
movablecore=nn[KMG] [KNL,X86,IA-64,PPC] This parameter
is similar to kernelcore except it specifies the
amount of memory used for migratable allocations.
If both kernelcore and movablecore is specified,
then kernelcore will be at *least* the specified
value but may be more. If movablecore on its own
is specified, the administrator must be careful
movablecore= [KNL,X86,IA-64,PPC]
Format: nn[KMGTPE] | nn%
This parameter is the complement to kernelcore=, it
specifies the amount of memory used for migratable
allocations. If both kernelcore and movablecore is
specified, then kernelcore will be at *least* the
specified value but may be more. If movablecore on its
own is specified, the administrator must be careful
that the amount of memory usable for all allocations
is not too small.
@ -3154,18 +3163,13 @@
force Enable ASPM even on devices that claim not to support it.
WARNING: Forcing ASPM on may cause system lockups.
pcie_hp= [PCIE] PCI Express Hotplug driver options:
nomsi Do not use MSI for PCI Express Native Hotplug (this
makes all PCIe ports use INTx for hotplug services).
pcie_ports= [PCIE] PCIe ports handling:
auto Ask the BIOS whether or not to use native PCIe services
associated with PCIe ports (PME, hot-plug, AER). Use
them only if that is allowed by the BIOS.
native Use native PCIe services associated with PCIe ports
unconditionally.
compat Treat PCIe ports as PCI-to-PCI bridges, disable the PCIe
ports driver.
pcie_ports= [PCIE] PCIe port services handling:
native Use native PCIe services (PME, AER, DPC, PCIe hotplug)
even if the platform doesn't give the OS permission to
use them. This may cause conflicts if the platform
also tries to use these services.
compat Disable native PCIe services (PME, AER, DPC, PCIe
hotplug).
pcie_port_pm= [PCIE] PCIe port power management handling:
off Disable power management of all PCIe ports

52
Documentation/arm/Atmel/README → Documentation/arm/Microchip/README
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@ -1,54 +1,54 @@
ARM Atmel SoCs (aka AT91)
=========================
ARM Microchip SoCs (aka AT91)
=============================
Introduction
------------
This document gives useful information about the ARM Atmel SoCs that are
This document gives useful information about the ARM Microchip SoCs that are
currently supported in Linux Mainline (you know, the one on kernel.org).
It is important to note that the Atmel | SMART ARM-based MPU product line is
historically named "AT91" or "at91" throughout the Linux kernel development
process even if this product prefix has completely disappeared from the
official Atmel product name. Anyway, files, directories, git trees,
It is important to note that the Microchip (previously Atmel) ARM-based MPU
product line is historically named "AT91" or "at91" throughout the Linux kernel
development process even if this product prefix has completely disappeared from
the official Microchip product name. Anyway, files, directories, git trees,
git branches/tags and email subject always contain this "at91" sub-string.
AT91 SoCs
---------
Documentation and detailed datasheet for each product are available on
the Atmel website: http://www.atmel.com.
the Microchip website: http://www.microchip.com.
Flavors:
* ARM 920 based SoC
- at91rm9200
+ Datasheet
http://www.atmel.com/Images/doc1768.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-1768-32-bit-ARM920T-Embedded-Microprocessor-AT91RM9200_Datasheet.pdf
* ARM 926 based SoCs
- at91sam9260
+ Datasheet
http://www.atmel.com/Images/doc6221.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6221-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9260_Datasheet.pdf
- at91sam9xe
+ Datasheet
http://www.atmel.com/Images/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9XE_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9XE_Datasheet.pdf
- at91sam9261
+ Datasheet
http://www.atmel.com/Images/doc6062.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6062-ARM926EJ-S-Microprocessor-SAM9261_Datasheet.pdf
- at91sam9263
+ Datasheet
http://www.atmel.com/Images/Atmel_6249_32-bit-ARM926EJ-S-Microcontroller_SAM9263_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6249-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9263_Datasheet.pdf
- at91sam9rl
+ Datasheet
http://www.atmel.com/Images/doc6289.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/doc6289.pdf
- at91sam9g20
+ Datasheet
http://www.atmel.com/Images/doc6384.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001516A.pdf
- at91sam9g45 family
- at91sam9g45
@ -56,7 +56,7 @@ the Atmel website: http://www.atmel.com.
- at91sam9m10
- at91sam9m11 (device superset)
+ Datasheet
http://www.atmel.com/Images/Atmel-6437-32-bit-ARM926-Embedded-Microprocessor-SAM9M11_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6437-32-bit-ARM926-Embedded-Microprocessor-SAM9M11_Datasheet.pdf
- at91sam9x5 family (aka "The 5 series")
- at91sam9g15
@ -65,11 +65,11 @@ the Atmel website: http://www.atmel.com.
- at91sam9x25
- at91sam9x35
+ Datasheet (can be considered as covering the whole family)
http://www.atmel.com/Images/Atmel_11055_32-bit-ARM926EJ-S-Microcontroller_SAM9X35_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11055-32-bit-ARM926EJ-S-Microcontroller-SAM9X35_Datasheet.pdf
- at91sam9n12
+ Datasheet
http://www.atmel.com/Images/Atmel_11063_32-bit-ARM926EJ-S-Microcontroller_SAM9N12CN11CN12_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001517A.pdf
* ARM Cortex-A5 based SoCs
- sama5d3 family
@ -79,7 +79,7 @@ the Atmel website: http://www.atmel.com.
- sama5d35
- sama5d36 (device superset)
+ Datasheet
http://www.atmel.com/Images/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf
* ARM Cortex-A5 + NEON based SoCs
- sama5d4 family
@ -88,7 +88,7 @@ the Atmel website: http://www.atmel.com.
- sama5d43
- sama5d44 (device superset)
+ Datasheet
http://www.atmel.com/Images/Atmel-11238-32-bit-Cortex-A5-Microcontroller-SAMA5D4_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/60001525A.pdf
- sama5d2 family
- sama5d21
@ -99,7 +99,7 @@ the Atmel website: http://www.atmel.com.
- sama5d27 (device superset)
- sama5d28 (device superset + environmental monitors)
+ Datasheet
http://www.atmel.com/Images/Atmel-11267-32-bit-Cortex-A5-Microcontroller-SAMA5D2_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001476B.pdf
* ARM Cortex-M7 MCUs
- sams70 family
@ -112,8 +112,6 @@ the Atmel website: http://www.atmel.com.
- sams70q19
- sams70q20
- sams70q21
+ Datasheet
http://www.atmel.com/Images/Atmel-11242-32-bit-Cortex-M7-Microcontroller-SAM-S70Q-SAM-S70N-SAM-S70J_Datasheet.pdf
- samv70 family
- samv70j19
@ -122,8 +120,6 @@ the Atmel website: http://www.atmel.com.
- samv70n20
- samv70q19
- samv70q20
+ Datasheet
http://www.atmel.com/Images/Atmel-11297-32-bit-Cortex-M7-Microcontroller-SAM-V70Q-SAM-V70N-SAM-V70J_Datasheet.pdf
- samv71 family
- samv71j19
@ -135,13 +131,15 @@ the Atmel website: http://www.atmel.com.
- samv71q19
- samv71q20
- samv71q21
+ Datasheet
http://www.atmel.com/Images/Atmel-44003-32-bit-Cortex-M7-Microcontroller-SAM-V71Q-SAM-V71N-SAM-V71J_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/60001527A.pdf
Linux kernel information
------------------------
Linux kernel mach directory: arch/arm/mach-at91
MAINTAINERS entry is: "ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES"
MAINTAINERS entry is: "ARM/Microchip (AT91) SoC support"
Device Tree for AT91 SoCs and boards

2
Documentation/arm/Samsung-S3C24XX/S3C2412.txt
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@ -46,7 +46,7 @@ NAND
----
The NAND hardware is similar to the S3C2440, and is supported by the
s3c2410 driver in the drivers/mtd/nand directory.
s3c2410 driver in the drivers/mtd/nand/raw directory.
USB Host

34
Documentation/arm/stm32/overview.rst Normal file
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@ -0,0 +1,34 @@
========================
STM32 ARM Linux Overview
========================
Introduction
------------
The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and
Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of
ARM Linux.
Configuration
-------------
For MCUs, use the provided default configuration:
make stm32_defconfig
For MPUs, use multi_v7 configuration:
make multi_v7_defconfig
Layout
------
All the files for multiple machine families are located in the platform code
contained in arch/arm/mach-stm32
There is a generic board board-dt.c in the mach folder which support
Flattened Device Tree, which means, it works with any compatible board with
Device Trees.
:Authors:
- Maxime Coquelin <mcoquelin.stm32@gmail.com>
- Ludovic Barre <ludovic.barre@st.com>
- Gerald Baeza <gerald.baeza@st.com>

33
Documentation/arm/stm32/overview.txt
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@ -1,33 +0,0 @@
STM32 ARM Linux Overview
========================
Introduction
------------
The STMicroelectronics family of Cortex-M based MCUs are supported by the
'STM32' platform of ARM Linux. Currently only the STM32F429 (Cortex-M4)
and STM32F746 (Cortex-M7) are supported.
Configuration
-------------
A generic configuration is provided for STM32 family, and can be used as the
default by
make stm32_defconfig
Layout
------
All the files for multiple machine families are located in the platform code
contained in arch/arm/mach-stm32
There is a generic board board-dt.c in the mach folder which support
Flattened Device Tree, which means, it works with any compatible board with
Device Trees.
Document Author
---------------
Maxime Coquelin <mcoquelin.stm32@gmail.com>

26
Documentation/arm/stm32/stm32f429-overview.rst Normal file
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@ -0,0 +1,26 @@
STM32F429 Overview
==================
Introduction
------------
The STM32F429 is a Cortex-M4 MCU aimed at various applications.
It features:
- ARM Cortex-M4 up to 180MHz with FPU
- 2MB internal Flash Memory
- External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
- I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
- LCD controller & Camera interface
- Cryptographic processor
Resources
---------
Datasheet and reference manual are publicly available on ST website (STM32F429_).
.. _STM32F429: http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
:Authors:
Maxime Coquelin <mcoquelin.stm32@gmail.com>

22
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@ -1,22 +0,0 @@
STM32F429 Overview
==================
Introduction
------------
The STM32F429 is a Cortex-M4 MCU aimed at various applications.
It features:
- ARM Cortex-M4 up to 180MHz with FPU
- 2MB internal Flash Memory
- External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
- I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
- LCD controller & Camera interface
- Cryptographic processor
Resources
---------
Datasheet and reference manual are publicly available on ST website:
- http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
Document Author
---------------
Maxime Coquelin <mcoquelin.stm32@gmail.com>

33
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@ -0,0 +1,33 @@
STM32F746 Overview
==================
Introduction
------------
The STM32F746 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @216MHz
- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
Resources
---------
Datasheet and reference manual are publicly available on ST website (STM32F746_).
.. _STM32F746: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
:Authors:
Alexandre Torgue <alexandre.torgue@st.com>

34
Documentation/arm/stm32/stm32f746-overview.txt
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@ -1,34 +0,0 @@
STM32F746 Overview
==================
Introduction
------------
The STM32F746 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @216MHz
- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
Resources
---------
Datasheet and reference manual are publicly available on ST website:
- http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
Document Author
---------------
Alexandre Torgue <alexandre.torgue@st.com>

35
Documentation/arm/stm32/stm32f769-overview.rst Normal file
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@ -0,0 +1,35 @@
STM32F769 Overview
==================
Introduction
------------
The STM32F769 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @216MHz
- 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support*2
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C*4, SPI*6, CAN*3 busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface*2
- LCD controller
- HDMI-CEC
- DSI
- SPDIFRX
- MDIO salave interface
Resources
---------
Datasheet and reference manual are publicly available on ST website (STM32F769_).
.. _STM32F769: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x9/stm32f769ni.html
:Authors:
Alexandre Torgue <alexandre.torgue@st.com>

34
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@ -0,0 +1,34 @@
STM32H743 Overview
==================
Introduction
------------
The STM32H743 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @400MHz
- 2MB internal flash, 1MBytes internal RAM
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
- DFSDM
Resources
---------
Datasheet and reference manual are publicly available on ST website (STM32H743_).
.. _STM32H743: http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
:Authors:
Alexandre Torgue <alexandre.torgue@st.com>

30
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@ -1,30 +0,0 @@
STM32H743 Overview
==================
Introduction
------------
The STM32H743 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @400MHz
- 2MB internal flash, 1MBytes internal RAM
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
- DFSDM
Resources
---------
Datasheet and reference manual are publicly available on ST website:
- http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
Document Author
---------------
Alexandre Torgue <alexandre.torgue@st.com>

19
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@ -0,0 +1,19 @@
STM32MP157 Overview
===================
Introduction
------------
The STM32MP157 is a Cortex-A MPU aimed at various applications.
It features:
- Dual core Cortex-A7 application core
- 2D/3D image composition with GPU
- Standard memories interface support
- Standard connectivity, widely inherited from the STM32 MCU family
- Comprehensive security support
:Authors:
- Ludovic Barre <ludovic.barre@st.com>
- Gerald Baeza <gerald.baeza@st.com>

9
Documentation/arm64/memory.txt
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@ -86,9 +86,12 @@ Translation table lookup with 64KB pages:
+-------------------------------------------------> [63] TTBR0/1
When using KVM without the Virtualization Host Extensions, the hypervisor
maps kernel pages in EL2 at a fixed offset from the kernel VA. See the
kern_hyp_va macro for more details.
When using KVM without the Virtualization Host Extensions, the
hypervisor maps kernel pages in EL2 at a fixed (and potentially
random) offset from the linear mapping. See the kern_hyp_va macro and
kvm_update_va_mask function for more details. MMIO devices such as
GICv2 gets mapped next to the HYP idmap page, as do vectors when
ARM64_HARDEN_EL2_VECTORS is selected for particular CPUs.
When using KVM with the Virtualization Host Extensions, no additional
mappings are created, since the host kernel runs directly in EL2.

31
Documentation/cdrom/cdrom-standard.tex
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@ -234,6 +234,7 @@ struct& cdrom_device_ops\ \{ \hidewidth\cr
&int& (* open)(struct\ cdrom_device_info *, int)\cr
&void& (* release)(struct\ cdrom_device_info *);\cr
&int& (* drive_status)(struct\ cdrom_device_info *, int);\cr
&unsigned\ int& (* check_events)(struct\ cdrom_device_info *, unsigned\ int, int);\cr
&int& (* media_changed)(struct\ cdrom_device_info *, int);\cr
&int& (* tray_move)(struct\ cdrom_device_info *, int);\cr
&int& (* lock_door)(struct\ cdrom_device_info *, int);\cr
@ -245,10 +246,9 @@ struct& cdrom_device_ops\ \{ \hidewidth\cr
&int& (* reset)(struct\ cdrom_device_info *);\cr
&int& (* audio_ioctl)(struct\ cdrom_device_info *, unsigned\ int,
void *{});\cr
&int& (* dev_ioctl)(struct\ cdrom_device_info *, unsigned\ int,
unsigned\ long);\cr
\noalign{\medskip}
&const\ int& capability;& capability flags \cr
&int& (* generic_packet)(struct\ cdrom_device_info *, struct\ packet_command *{});\cr
\};\cr
}
$$
@ -274,19 +274,32 @@ $$
\halign{$#$\ \hfil&$#$\ \hfil&\hbox to 10em{$#$\hss}&
$/*$ \rm# $*/$\hfil\cr
struct& cdrom_device_info\ \{ \hidewidth\cr
& struct\ cdrom_device_ops *& ops;& device operations for this major\cr
& struct\ cdrom_device_info *& next;& next device_info for this major\cr
& const\ struct\ cdrom_device_ops *& ops;& device operations for this major\cr
& struct\ list_head& list;& linked list of all device_info\cr
& struct\ gendisk *& disk;& matching block layer disk\cr
& void *& handle;& driver-dependent data\cr
\noalign{\medskip}
& kdev_t& dev;& device number (incorporates minor)\cr
& int& mask;& mask of capability: disables them \cr
& int& speed;& maximum speed for reading data \cr
& int& capacity;& number of discs in a jukebox \cr
\noalign{\medskip}
&int& options : 30;& options flags \cr
&unsigned\ int& options : 30;& options flags \cr
&unsigned& mc_flags : 2;& media-change buffer flags \cr
&unsigned\ int& vfs_events;& cached events for vfs path\cr
&unsigned\ int& ioctl_events;& cached events for ioctl path\cr
& int& use_count;& number of times device is opened\cr
& char& name[20];& name of the device type\cr
\noalign{\medskip}
&__u8& sanyo_slot : 2;& Sanyo 3-CD changer support\cr
&__u8& keeplocked : 1;& CDROM_LOCKDOOR status\cr
&__u8& reserved : 5;& not used yet\cr
& int& cdda_method;& see CDDA_* flags\cr
&__u8& last_sense;& saves last sense key\cr
&__u8& media_written;& dirty flag, DVD+RW bookkeeping\cr
&unsigned\ short& mmc3_profile;& current MMC3 profile\cr
& int& for_data;& unknown:TBD\cr
& int\ (* exit)\ (struct\ cdrom_device_info *);&& unknown:TBD\cr
& int& mrw_mode_page;& which MRW mode page is in use\cr
\}\cr
}$$
Using this $struct$, a linked list of the registered minor devices is
@ -298,9 +311,7 @@ The $mask$ flags can be used to mask out some of the capabilities listed
in $ops\to capability$, if a specific drive doesn't support a feature
of the driver. The value $speed$ specifies the maximum head-rate of the
drive, measured in units of normal audio speed (176\,kB/sec raw data or
150\,kB/sec file system data). The value $n_discs$ should reflect the
number of discs the drive can hold simultaneously, if it is designed
as a juke-box, or otherwise~1. The parameters are declared $const$
150\,kB/sec file system data). The parameters are declared $const$
because they describe properties of the drive, which don't change after
registration.
@ -1002,7 +1013,7 @@ taken over the torch in maintaining \cdromc\ and integrating much
\cdrom-related code in the 2.1-kernel. Thanks to Scott Snyder and
Gerd Knorr, who were the first to implement this interface for SCSI
and IDE-CD drivers and added many ideas for extension of the data
structures relative to kernel~2.0. Further thanks to Heiko Ei{\sz}feldt,
structures relative to kernel~2.0. Further thanks to Heiko Ei{\ss}feldt,
Thomas Quinot, Jon Tombs, Ken Pizzini, Eberhard M\"onkeberg and Andrew
Kroll, the \linux\ \cdrom\ device driver developers who were kind
enough to give suggestions and criticisms during the writing. Finally

2
Documentation/cgroup-v1/memory.txt
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@ -262,7 +262,7 @@ When oom event notifier is registered, event will be delivered.
2.6 Locking
lock_page_cgroup()/unlock_page_cgroup() should not be called under
mapping->tree_lock.
the i_pages lock.
Other lock order is following:
PG_locked.

16
Documentation/clk.txt
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@ -268,9 +268,19 @@ The common clock framework uses two global locks, the prepare lock and the
enable lock.
The enable lock is a spinlock and is held across calls to the .enable,
.disable and .is_enabled operations. Those operations are thus not allowed to
sleep, and calls to the clk_enable(), clk_disable() and clk_is_enabled() API
functions are allowed in atomic context.
.disable operations. Those operations are thus not allowed to sleep,
and calls to the clk_enable(), clk_disable() API functions are allowed in
atomic context.
For clk_is_enabled() API, it is also designed to be allowed to be used in
atomic context. However, it doesn't really make any sense to hold the enable
lock in core, unless you want to do something else with the information of
the enable state with that lock held. Otherwise, seeing if a clk is enabled is
a one-shot read of the enabled state, which could just as easily change after
the function returns because the lock is released. Thus the user of this API
needs to handle synchronizing the read of the state with whatever they're
using it for to make sure that the enable state doesn't change during that
time.
The prepare lock is a mutex and is held across calls to all other operations.
All those operations are allowed to sleep, and calls to the corresponding API

12
Documentation/cpu-freq/core.txt
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@ -97,12 +97,10 @@ flags - flags of the cpufreq driver
==================================================================
For details about OPP, see Documentation/power/opp.txt
dev_pm_opp_init_cpufreq_table - cpufreq framework typically is initialized with
cpufreq_table_validate_and_show() which is provided with the list of
frequencies that are available for operation. This function provides
a ready to use conversion routine to translate the OPP layer's internal
information about the available frequencies into a format readily
providable to cpufreq.
dev_pm_opp_init_cpufreq_table -
This function provides a ready to use conversion routine to translate
the OPP layer's internal information about the available frequencies
into a format readily providable to cpufreq.
WARNING: Do not use this function in interrupt context.
@ -112,7 +110,7 @@ dev_pm_opp_init_cpufreq_table - cpufreq framework typically is initialized with
/* Do things */
r = dev_pm_opp_init_cpufreq_table(dev, &freq_table);
if (!r)
cpufreq_table_validate_and_show(policy, freq_table);
policy->freq_table = freq_table;
/* Do other things */
}

6
Documentation/cpu-freq/cpu-drivers.txt
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@ -259,10 +259,8 @@ CPUFREQ_ENTRY_INVALID. The entries don't need to be in sorted in any
particular order, but if they are cpufreq core will do DVFS a bit
quickly for them as search for best match is faster.
By calling cpufreq_table_validate_and_show(), the cpuinfo.min_freq and
cpuinfo.max_freq values are detected, and policy->min and policy->max
are set to the same values. This is helpful for the per-CPU
initialization stage.
The cpufreq table is verified automatically by the core if the policy contains a
valid pointer in its policy->freq_table field.
cpufreq_frequency_table_verify() assures that at least one valid
frequency is within policy->min and policy->max, and all other criteria

6
Documentation/cpuidle/sysfs.txt
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@ -40,6 +40,7 @@ total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
-r--r--r-- 1 root root 4096 Feb 8 10:42 residency
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
@ -50,6 +51,7 @@ total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
-r--r--r-- 1 root root 4096 Feb 8 10:42 residency
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
@ -60,6 +62,7 @@ total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
-r--r--r-- 1 root root 4096 Feb 8 10:42 residency
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
@ -70,6 +73,7 @@ total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
-r--r--r-- 1 root root 4096 Feb 8 10:42 residency
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
--------------------------------------------------------------------------------
@ -78,6 +82,8 @@ total 0
* desc : Small description about the idle state (string)
* disable : Option to disable this idle state (bool) -> see note below
* latency : Latency to exit out of this idle state (in microseconds)
* residency : Time after which a state becomes more effecient than any
shallower state (in microseconds)
* name : Name of the idle state (string)
* power : Power consumed while in this idle state (in milliwatts)
* time : Total time spent in this idle state (in microseconds)

11
Documentation/device-mapper/verity.txt
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@ -109,6 +109,17 @@ fec_start <offset>
This is the offset, in <data_block_size> blocks, from the start of the
FEC device to the beginning of the encoding data.
check_at_most_once
Verify data blocks only the first time they are read from the data device,
rather than every time. This reduces the overhead of dm-verity so that it
can be used on systems that are memory and/or CPU constrained. However, it
provides a reduced level of security because only offline tampering of the
data device's content will be detected, not online tampering.
Hash blocks are still verified each time they are read from the hash device,
since verification of hash blocks is less performance critical than data
blocks, and a hash block will not be verified any more after all the data
blocks it covers have been verified anyway.
Theory of operation
===================

179
Documentation/devicetree/bindings/arm/arm,scmi.txt Normal file
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@ -0,0 +1,179 @@
System Control and Management Interface (SCMI) Message Protocol
----------------------------------------------------------
The SCMI is intended to allow agents such as OSPM to manage various functions
that are provided by the hardware platform it is running on, including power
and performance functions.
This binding is intended to define the interface the firmware implementing
the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control
and Management Interface Platform Design Document")[0] provide for OSPM in
the device tree.
Required properties:
The scmi node with the following properties shall be under the /firmware/ node.
- compatible : shall be "arm,scmi"
- mboxes: List of phandle and mailbox channel specifiers. It should contain
exactly one or two mailboxes, one for transmitting messages("tx")
and another optional for receiving the notifications("rx") if
supported.
- shmem : List of phandle pointing to the shared memory(SHM) area as per
generic mailbox client binding.
- #address-cells : should be '1' if the device has sub-nodes, maps to
protocol identifier for a given sub-node.
- #size-cells : should be '0' as 'reg' property doesn't have any size
associated with it.
Optional properties:
- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
about the generic mailbox controller and client driver bindings.
The mailbox is the only permitted method of calling the SCMI firmware.
Mailbox doorbell is used as a mechanism to alert the presence of a
messages and/or notification.
Each protocol supported shall have a sub-node with corresponding compatible
as described in the following sections. If the platform supports dedicated
communication channel for a particular protocol, the 3 properties namely:
mboxes, mbox-names and shmem shall be present in the sub-node corresponding
to that protocol.
Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
------------------------------------------------------------
This binding uses the common clock binding[1].
Required properties:
- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
Power domain bindings for the power domains based on SCMI Message Protocol
------------------------------------------------------------
This binding for the SCMI power domain providers uses the generic power
domain binding[2].
Required properties:
- #power-domain-cells : Should be 1. Contains the device or the power
domain ID value used by SCMI commands.
Sensor bindings for the sensors based on SCMI Message Protocol
--------------------------------------------------------------
SCMI provides an API to access the various sensors on the SoC.
Required properties:
- #thermal-sensor-cells: should be set to 1. This property follows the
thermal device tree bindings[3].
Valid cell values are raw identifiers (Sensor ID)
as used by the firmware. Refer to platform details
for your implementation for the IDs to use.
SRAM and Shared Memory for SCMI
-------------------------------
A small area of SRAM is reserved for SCMI communication between application
processors and SCP.
The properties should follow the generic mmio-sram description found in [4]
Each sub-node represents the reserved area for SCMI.
Required sub-node properties:
- reg : The base offset and size of the reserved area with the SRAM
- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
shared memory
[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/power/power_domain.txt
[3] Documentation/devicetree/bindings/thermal/thermal.txt
[4] Documentation/devicetree/bindings/sram/sram.txt
Example:
sram@50000000 {
compatible = "mmio-sram";
reg = <0x0 0x50000000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x10000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x200>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "arm,scmi-shmem";
reg = <0x200 0x200>;
};
};
mailbox@40000000 {
....
#mbox-cells = <1>;
reg = <0x0 0x40000000 0x0 0x10000>;
};
firmware {
...
scmi {
compatible = "arm,scmi";
mboxes = <&mailbox 0 &mailbox 1>;
mbox-names = "tx", "rx";
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
#address-cells = <1>;
#size-cells = <0>;
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
scmi_dvfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
};
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
scmi_sensors0: protocol@15 {
reg = <0x15>;
#thermal-sensor-cells = <1>;
};
};
};
cpu@0 {
...
reg = <0 0>;
clocks = <&scmi_dvfs 0>;
};
hdlcd@7ff60000 {
...
reg = <0 0x7ff60000 0 0x1000>;
clocks = <&scmi_clk 4>;
power-domains = <&scmi_devpd 1>;
};
thermal-zones {
soc_thermal {
polling-delay-passive = <100>;
polling-delay = <1000>;
/* sensor ID */
thermal-sensors = <&scmi_sensors0 3>;
...
};
};

42
Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp Normal file
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@ -0,0 +1,42 @@
=========================================================
Secondary CPU enable-method "nuvoton,npcm750-smp" binding
=========================================================
To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
defined in the "cpus" node.
Enable method name: "nuvoton,npcm750-smp"
Compatible machines: "nuvoton,npcm750"
Compatible CPUs: "arm,cortex-a9"
Related properties: (none)
Note:
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
"nuvoton,npcm750-gcr".
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "nuvoton,npcm750-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
clocks = <&clk NPCM7XX_CLK_CPU>;
clock-names = "clk_cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
clocks = <&clk NPCM7XX_CLK_CPU>;
clock-names = "clk_cpu";
reg = <1>;
next-level-cache = <&L2>;
};
};

2
Documentation/devicetree/bindings/arm/cpus.txt
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@ -185,6 +185,7 @@ described below.
"nvidia,tegra186-denver"
"qcom,krait"
"qcom,kryo"
"qcom,kryo385"
"qcom,scorpion"
- enable-method
Value type: <stringlist>
@ -198,6 +199,7 @@ described below.
"actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"allwinner,sun9i-a80-smp"
"amlogic,meson8-smp"
"amlogic,meson8b-smp"
"arm,realview-smp"

33
Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt Normal file
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@ -0,0 +1,33 @@
Hisilicon Hip06 Low Pin Count device
Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
provides I/O access to some legacy ISA devices.
Hip06 is based on arm64 architecture where there is no I/O space. So, the
I/O ports here are not CPU addresses, and there is no 'ranges' property in
LPC device node.
Required properties:
- compatible: value should be as follows:
(a) "hisilicon,hip06-lpc"
(b) "hisilicon,hip07-lpc"
- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
- reg: base memory range where the LPC register set is mapped.
Note:
The node name before '@' must be "isa" to represent the binding stick to the
ISA/EISA binding specification.
Example:
isa@a01b0000 {
compatible = "hisilicon,hip06-lpc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xa01b0000 0x0 0x1000>;
ipmi0: bt@e4 {
compatible = "ipmi-bt";
device_type = "ipmi";
reg = <0x01 0xe4 0x04>;
};
};

9
Documentation/devicetree/bindings/arm/mediatek.txt
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@ -50,6 +50,15 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
- Reference board for MT7623a with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
- Reference board for MT7623a with NAND:
Required root node properties:
- compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623";
- Reference board for MT7623n with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Reference board for MT7623n with NAND:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";

20
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
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@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- #clock-cells: Must be 1
@ -13,10 +14,19 @@ The AUDSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Required sub-nodes:
-------
For common binding part and usage, refer to
../sonud/mt2701-afe-pcm.txt.
Example:
audsys: audsys@11220000 {
compatible = "mediatek,mt7622-audsys", "syscon";
reg = <0 0x11220000 0 0x1000>;
#clock-cells = <1>;
};
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7622-audsys", "syscon";
reg = <0 0x11220000 0 0x2000>;
#clock-cells = <1>;
afe: audio-controller {
...
};
};

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
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@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt

2
Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
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@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-pciesys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The PCIESYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
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@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-ssusbsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The SSUSBSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

6
Documentation/devicetree/bindings/arm/npcm/npcm.txt Normal file
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@ -0,0 +1,6 @@
NPCM Platforms Device Tree Bindings
-----------------------------------
NPCM750 SoC
Required root node properties:
- compatible = "nuvoton,npcm750";

1
Documentation/devicetree/bindings/arm/omap/ctrl.txt
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@ -25,6 +25,7 @@ Required properties:
"ti,omap4-scm-padconf-wkup"
"ti,omap5-scm-core"
"ti,omap5-scm-padconf-core"
"ti,omap5-scm-wkup-pad-conf"
"ti,dra7-scm-core"
- reg: Contains Control Module register address range
(base address and length)

16
Documentation/devicetree/bindings/arm/omap/mpu.txt
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@ -13,6 +13,13 @@ Required properties:
Optional properties:
- sram: Phandle to the ocmcram node
am335x and am437x only:
- pm-sram: Phandles to ocmcram nodes to be used for power management.
First should be type 'protect-exec' for the driver to use to copy
and run PM functions, second should be regular pool to be used for
data region for code. See Documentation/devicetree/bindings/sram/sram.txt
for more details.
Examples:
- For an OMAP5 SMP system:
@ -36,3 +43,12 @@ mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
- For an AM335x system:
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
pm-sram = <&pm_sram_code
&pm_sram_data>;
};

1
Documentation/devicetree/bindings/arm/qcom.txt
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@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings:
msm8996
mdm9615
ipq8074
sdm845
The 'board' element must be one of the following strings:

12
Documentation/devicetree/bindings/arm/rockchip.txt
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@ -50,6 +50,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
- Firefly roc-rk3328-cc board:
Required root node properties:
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@ -181,10 +185,18 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
- Rockchip RK3399 Sapphire board standalone:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
- Rockchip RK3399 Sapphire Excavator board:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
- Theobroma Systems RK3368-uQ7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368";
- Theobroma Systems RK3399-Q7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";

6
Documentation/devicetree/bindings/arm/samsung/pmu.txt
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@ -43,6 +43,12 @@ following properties:
- interrupt-parent: a phandle indicating which interrupt controller
this PMU signals interrupts to.
Optional nodes:
- nodes defining the restart and poweroff syscon children
Example :
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";

4
Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
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@ -9,7 +9,11 @@ Required root node properties:
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
- "samsung,trats" - for Exynos4210-based Tizen Reference board.
- "samsung,universal_c210" - for Exynos4210-based Samsung board.
- "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board.
- "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board.
- "samsung,midas" - for Exynos4412-based Samsung Midas board.
- "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
- "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board.
- "samsung,trats2" - for Exynos4412-based Tizen Reference board.
- "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
- "samsung,xyref5260" - for Exynos5260-based Samsung board.

18
Documentation/devicetree/bindings/arm/shmobile.txt
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@ -39,8 +39,12 @@ SoCs:
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
- R-Car M3-N (R8A77965)
compatible = "renesas,r8a77965"
- R-Car V3M (R8A77970)
compatible = "renesas,r8a77970"
- R-Car V3H (R8A77980)
compatible = "renesas,r8a77980"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
@ -52,11 +56,13 @@ Boards:
- APE6-EVM
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
compatible = "renesas,armadillo800eva"
compatible = "renesas,armadillo800eva", "renesas,r8a7740"
- Blanche (RTP0RC7792SEB00010S)
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
compatible = "renesas,condor", "renesas,r8a77980"
- Draak (RTP0RC77995SEB0010S)
compatible = "renesas,draak", "renesas,r8a77995"
- Eagle (RTP0RC77970SEB0010S)
@ -102,19 +108,25 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
compatible = "renesas,salvator-x", "renesas,r8a7796"
- Salvator-X (RTP0RC7796SIPB0011S (M3N))
compatible = "renesas,salvator-x", "renesas,r8a77965"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7795"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7796"
- Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
compatible = "renesas,salvator-xs", "renesas,r8a77965"
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- SK-RZG1M (YR8A77430S000BE)
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- V3MSK
- Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
compatible = "renesas,stout", "renesas,r8a7790"
- V3MSK (Y-ASK-RCAR-V3M-WS10)
compatible = "renesas,v3msk", "renesas,r8a77970"
- Wheat
- Wheat (RTP0RC7792ASKB0000JE)
compatible = "renesas,wheat", "renesas,r8a7792"

1
Documentation/devicetree/bindings/arm/stm32.txt
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@ -7,3 +7,4 @@ using one of the following compatible strings:
st,stm32f469
st,stm32f746
st,stm32h743
st,stm32mp157

44
Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt Normal file
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@ -0,0 +1,44 @@
Allwinner SRAM for smp bringup:
------------------------------------------------
Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
primary core (cpu0). Once the core gets powered up it checks if a magic
value is set at a specific location. If it is then the BROM will jump
to the software entry address, instead of executing a standard boot.
Therefore a reserved section sub-node has to be added to the mmio-sram
declaration.
Note that this is separate from the Allwinner SRAM controller found in
../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
any device.
Also there are no "secure-only" properties. The implementation should
check if this SRAM is usable first.
Required sub-node properties:
- compatible : depending on the SoC this should be one of:
"allwinner,sun9i-a80-smp-sram"
The rest of the properties should follow the generic mmio-sram discription
found in ../../misc/sram.txt
Example:
sram_b: sram@20000 {
/* 256 KiB secure SRAM at 0x20000 */
compatible = "mmio-sram";
reg = <0x00020000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00020000 0x40000>;
smp-sram@1000 {
/*
* This is checked by BROM to determine if
* cpu0 should jump to SMP entry vector
*/
compatible = "allwinner,sun9i-a80-smp-sram";
reg = <0x1000 0x8>;
};
};

16
Documentation/devicetree/bindings/arm/tegra.txt
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@ -9,6 +9,12 @@ following compatible values:
nvidia,tegra20
nvidia,tegra30
nvidia,tegra114
nvidia,tegra124
nvidia,tegra132
nvidia,tegra210
nvidia,tegra186
nvidia,tegra194
Boards
-------------------------------------------
@ -26,8 +32,18 @@ board-specific compatible values:
nvidia,cardhu
nvidia,cardhu-a02
nvidia,cardhu-a04
nvidia,dalmore
nvidia,harmony
nvidia,jetson-tk1
nvidia,norrin
nvidia,p2371-0000
nvidia,p2371-2180
nvidia,p2571
nvidia,p2771-0000
nvidia,p2972-0000
nvidia,roth
nvidia,seaboard
nvidia,tn7
nvidia,ventana
toradex,apalis_t30
toradex,apalis_t30-eval

2
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
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@ -3,6 +3,7 @@ NVIDIA Tegra Power Management Controller (PMC)
Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra186-pmc": for Tegra186
- "nvidia,tegra194-pmc": for Tegra194
- reg: Must contain an (offset, length) pair of the register set for each
entry in reg-names.
- reg-names: Must include the following entries:
@ -10,6 +11,7 @@ Required properties:
- "wake"
- "aotag"
- "scratch"
- "misc" (Only for Tegra194)
Optional properties:
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.

56
Documentation/devicetree/bindings/arm/xilinx.txt
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@ -5,3 +5,59 @@ shall have the following properties.
Required root node properties:
- compatible = "xlnx,zynq-7000";
Additional compatible strings:
- Xilinx internal board cc108
"xlnx,zynq-cc108"
- Xilinx internal board zc770 with different FMC cards
"xlnx,zynq-zc770-xm010"
"xlnx,zynq-zc770-xm011"
"xlnx,zynq-zc770-xm012"
"xlnx,zynq-zc770-xm013"
- Digilent Zybo Z7 board
"digilent,zynq-zybo-z7"
---------------------------------------------------------------
Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
Boards with ZynqMP SOC based on an ARM Cortex A53 processor
shall have the following properties.
Required root node properties:
- compatible = "xlnx,zynqmp";
Additional compatible strings:
- Xilinx internal board zc1232
"xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232"
- Xilinx internal board zc1254
"xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254"
- Xilinx internal board zc1275
"xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275"
- Xilinx internal board zc1751
"xlnx,zynqmp-zc1751"
- Xilinx 96boards compatible board zcu100
"xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"
- Xilinx evaluation board zcu102
"xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102"
"xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102"
"xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102"
- Xilinx evaluation board zcu104
"xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104"
- Xilinx evaluation board zcu106
"xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106"
- Xilinx evaluation board zcu111
"xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111"

6
Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
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@ -73,7 +73,7 @@ Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
controllers with a simple-bus node since they are all connected to the same
chip-select (CS4), in this example external address decoding is provided:
gmi@70090000 {
gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@ -84,7 +84,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
bus@4,0 {
compatible = "simple-bus";
#address-cells = <1>;
@ -109,7 +108,7 @@ gmi@70090000 {
Example with one SJA1000 CAN controller connected to the GMI bus
on CS4:
gmi@70090000 {
gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@ -120,7 +119,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
can@4,0 {
reg = <4 0 0x100>;
nvidia,snor-mux-mode;

36
Documentation/devicetree/bindings/clock/imx6sll-clock.txt Normal file
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@ -0,0 +1,36 @@
* Clock bindings for Freescale i.MX6 SLL
Required properties:
- compatible: Should be "fsl,imx6sll-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
for the full list of i.MX6 SLL clock IDs.
Examples:
#include <dt-bindings/clock/imx6sll-clock.h>
clks: clock-controller@20c4000 {
compatible = "fsl,imx6sll-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
};
uart1: serial@2020000 {
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
<&clks IMX6SLL_CLK_UART1_SERIAL>;
clock-names = "ipg", "per";
};

20
Documentation/devicetree/bindings/clock/intc_stratix10.txt Normal file
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@ -0,0 +1,20 @@
Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be
"intel,stratix10-clkmgr"
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- #clock-cells : from common clock binding, shall be set to 1.
Example:
clkmgr: clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};

6
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
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@ -22,7 +22,9 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@ -32,8 +34,8 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
r8a7795, r8a7796, r8a77970, r8a77995)
- "extalr" (r8a7795, r8a7796, r8a77970)
r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2

1
Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
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@ -32,6 +32,7 @@ clock-output-names:
- "clkin_i2s" - external I2S clock - optional,
- "gmac_clkin" - external GMAC clock - optional
- "phy_50m_out" - output clock of the pll in the mac phy
- "hdmi_phy" - output clock of the hdmi phy pll - optional
Example: Clock controller node:

25
Documentation/devicetree/bindings/clock/silabs,si544.txt Normal file
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@ -0,0 +1,25 @@
Binding for Silicon Labs 544 programmable I2C clock generator.
Reference
This binding uses the common clock binding[1]. Details about the device can be
found in the datasheet[2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si544 datasheet
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
Required properties:
- compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
to the speed grade of the chip.
- reg: I2C device address.
- #clock-cells: From common clock bindings: Shall be 0.
Optional properties:
- clock-output-names: From common clock bindings. Recommended to be "si544".
Example:
si544: clock-controller@55 {
reg = <0x55>;
#clock-cells = <0>;
compatible = "silabs,si544b";
};

60
Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt Normal file
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@ -0,0 +1,60 @@
STMicroelectronics STM32 Peripheral Reset Clock Controller
==========================================================
The RCC IP is both a reset and a clock controller.
RCC makes also power management (resume/supend and wakeup interrupt).
Please also refer to reset.txt for common reset controller binding usage.
Please also refer to clock-bindings.txt for common clock controller
binding usage.
Required properties:
- compatible: "st,stm32mp1-rcc", "syscon"
- reg: should be register base and length as documented in the datasheet
- #clock-cells: 1, device nodes should specify the clock in their
"clocks" property, containing a phandle to the clock device node,
an index specifying the clock to use.
- #reset-cells: Shall be 1
- interrupts: Should contain a general interrupt line and a interrupt line
to the wake-up of processor (CSTOP).
Example:
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
<GIC_SPI 145 IRQ_TYPE_NONE>;
};
Specifying clocks
=================
All available clocks are defined as preprocessor macros in
dt-bindings/clock/stm32mp1-clks.h header and can be used in device
tree sources.
Specifying softreset control of devices
=======================================
Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the reset device node and an index specifying
which channel to use.
The index is the bit number within the RCC registers bank, starting from RCC
base address.
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register.
For example on STM32MP1, for LTDC reset:
ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
= 0x180 / 4 * 32 + 0 = 3072
The list of valid indices for STM32MP1 is available in:
include/dt-bindings/reset-controller/stm32mp1-resets.h
This file implements defines like:
#define LTDC_R 3072

4
Documentation/devicetree/bindings/clock/sunxi-ccu.txt
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@ -20,6 +20,7 @@ Required properties :
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
@ -31,6 +32,9 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
For the main CCU on H6, one more clock is needed:
- "iosc": the SoC's internal frequency oscillator
For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator

93
Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt Normal file
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@ -0,0 +1,93 @@
Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
registers call CFGCHIPn. Some of these registers function as clock
gates. This document describes the bindings for those clocks.
All of the clock nodes described below must be child nodes of a CFGCHIP node
(compatible = "ti,da830-cfgchip").
USB PHY clocks
--------------
Required properties:
- compatible: shall be "ti,da830-usb-phy-clocks".
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "fck", "usb_refclkin", "auxclk"
This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
eHRPWM Time Base Clock (TBCLK)
------------------------------
Required properties:
- compatible: shall be "ti,da830-tbclksync".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandle to the parent clock
- clock-names: shall be "fck"
PLL DIV4.5 divider
------------------
Required properties:
- compatible: shall be "ti,da830-div4p5ena".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandle to the parent clock
- clock-names: shall be "pll0_pllout"
EMIFA clock source (ASYNC1)
---------------------------
Required properties:
- compatible: shall be "ti,da850-async1-clksrc".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "pll0_sysclk3", "div4.5"
ASYNC3 clock source
-------------------
Required properties:
- compatible: shall be "ti,da850-async3-clksrc".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
Examples:
cfgchip: syscon@1417c {
compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
reg = <0x1417c 0x14>;
usb_phy_clk: usb-phy-clocks {
compatible = "ti,da830-usb-phy-clocks";
#clock-cells = <1>;
clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
clock-names = "fck", "usb_refclkin", "auxclk";
};
ehrpwm_tbclk: ehrpwm_tbclk {
compatible = "ti,da830-tbclksync";
#clock-cells = <0>;
clocks = <&psc1 17>;
clock-names = "fck";
};
div4p5_clk: div4.5 {
compatible = "ti,da830-div4p5ena";
#clock-cells = <0>;
clocks = <&pll0_pllout>;
clock-names = "pll0_pllout";
};
async1_clk: async1 {
compatible = "ti,da850-async1-clksrc";
#clock-cells = <0>;
clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
clock-names = "pll0_sysclk3", "div4.5";
};
async3_clk: async3 {
compatible = "ti,da850-async3-clksrc";
#clock-cells = <0>;
clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
clock-names = "pll0_sysclk2", "pll1_sysclk2";
};
};
Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt

96
Documentation/devicetree/bindings/clock/ti/davinci/pll.txt Normal file
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@ -0,0 +1,96 @@
Binding for TI DaVinci PLL Controllers
The PLL provides clocks to most of the components on the SoC. In addition
to the PLL itself, this controller also contains bypasses, gates, dividers,
an multiplexers for various clock signals.
Required properties:
- compatible: shall be one of:
- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
- reg: physical base address and size of the controller's register area.
- clocks: phandles corresponding to the clock names
- clock-names: names of the clock sources - depends on compatible string
- for "ti,da850-pll0", shall be "clksrc", "extclksrc"
- for "ti,da850-pll1", shall be "clksrc"
Optional properties:
- ti,clkmode-square-wave: Indicates that the the board is supplying a square
wave input on the OSCIN pin instead of using a crystal oscillator.
This property is only valid when compatible = "ti,da850-pll0".
Optional child nodes:
pllout
Describes the main PLL clock output (before POSTDIV). The node name must
be "pllout".
Required properties:
- #clock-cells: shall be 0
sysclk
Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
domains. The node name must be "sysclk". Consumers of this node should
use "n" in "SYSCLKn" as the index parameter for the clock cell.
Required properties:
- #clock-cells: shall be 1
auxclk
Describes the AUXCLK output of the PLL. The node name must be "auxclk".
This child node is only valid when compatible = "ti,da850-pll0".
Required properties:
- #clock-cells: shall be 0
obsclk
Describes the OBSCLK output of the PLL. The node name must be "obsclk".
Required properties:
- #clock-cells: shall be 0
Examples:
pll0: clock-controller@11000 {
compatible = "ti,da850-pll0";
reg = <0x11000 0x1000>;
clocks = <&ref_clk>, <&pll1_sysclk 3>;
clock-names = "clksrc", "extclksrc";
ti,clkmode-square-wave;
pll0_pllout: pllout {
#clock-cells = <0>;
};
pll0_sysclk: sysclk {
#clock-cells = <1>;
};
pll0_auxclk: auxclk {
#clock-cells = <0>;
};
pll0_obsclk: obsclk {
#clock-cells = <0>;
};
};
pll1: clock-controller@21a000 {
compatible = "ti,da850-pll1";
reg = <0x21a000 0x1000>;
clocks = <&ref_clk>;
clock-names = "clksrc";
pll0_sysclk: sysclk {
#clock-cells = <1>;
};
pll0_obsclk: obsclk {
#clock-cells = <0>;
};
};
Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt

71
Documentation/devicetree/bindings/clock/ti/davinci/psc.txt Normal file
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@ -0,0 +1,71 @@
Binding for TI DaVinci Power Sleep Controller (PSC)
The PSC provides power management, clock gating and reset functionality. It is
primarily used for clocking.
Required properties:
- compatible: shall be one of:
- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
- reg: physical base address and size of the controller's register area
- #clock-cells: from common clock binding; shall be set to 1
- #power-domain-cells: from generic power domain binding; shall be set to 1.
- clocks: phandles to clocks corresponding to the clock-names property
- clock-names: list of parent clock names - depends on compatible value
- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
"pll0_sysclk4", "pll0_sysclk6", "async1"
- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
Optional properties:
- #reset-cells: from reset binding; shall be set to 1 - only applicable when
at least one local domain provides a local reset.
Consumers:
Clock, power domain and reset consumers shall use the local power domain
module ID (LPSC) as the index corresponding to the clock cell. Refer to
the device-specific datasheet to find these numbers. NB: Most local
domains only provide a clock/power domain and not a reset.
Examples:
psc0: clock-controller@10000 {
compatible = "ti,da850-psc0";
reg = <0x10000 0x1000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
<&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
clock_names = "pll0_sysclk1", "pll0_sysclk2",
"pll0_sysclk4", "pll0_sysclk6", "async1";
};
psc1: clock-controller@227000 {
compatible = "ti,da850-psc1";
reg = <0x227000 0x1000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
};
/* consumer */
dsp: dsp@11800000 {
compatible = "ti,da850-dsp";
reg = <0x11800000 0x40000>,
<0x11e00000 0x8000>,
<0x11f00000 0x8000>,
<0x01c14044 0x4>,
<0x01c14174 0x8>;
reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
interrupt-parent = <&intc>;
interrupts = <28>;
clocks = <&psc0 15>;
power-domains = <&psc0 15>;
resets = <&psc0 15>;
};
Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
- Documentation/devicetree/bindings/power/power_domain.txt
- Documentation/devicetree/bindings/reset/reset.txt

3
Documentation/devicetree/bindings/clock/ti/divider.txt
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@ -75,6 +75,9 @@ Optional properties:
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
see [2]
- ti,set-rate-parent : clk_set_rate is propagated to parent
- ti,latch-bit : latch the divider value to HW, only needed if the register
access requires this. As an example dra76x DPLL_GMAC H14 divider implements
such behavior.
Examples:
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {

3
Documentation/devicetree/bindings/clock/ti/mux.txt
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@ -48,6 +48,9 @@ Optional properties:
zero
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
not supported by the composite-mux-clock subtype
- ti,latch-bit : latch the mux value to HW, only needed if the register
access requires this. As an example, dra7x DPLL_GMAC H14 muxing
implements such behavior.
Examples:

17
Documentation/devicetree/bindings/crypto/fsl-sec4.txt
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@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
value type: <u32>
Definition: LP register offset. default it is 0x34.
- clocks
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <prop_encoded-array>
Definition: a clock specifier describing the clock required for
enabling and disabling SNVS LP RTC.
- clock-names
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <string>
Definition: clock name string should be "snvs-rtc".
EXAMPLE
sec_mon_rtc_lp@1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
interrupts = <93 2>;
regmap = <&snvs>;
offset = <0x34>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
=====================================================================
@ -543,6 +558,8 @@ FULL EXAMPLE
regmap = <&sec_mon>;
offset = <0x34>;
interrupts = <93 2>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
snvs-pwrkey@020cc000 {

4
Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
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@ -74,8 +74,8 @@ Example:
bcm2835_i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
reg = < 0x7e203000 0x20>,
< 0x7e101098 0x02>;
reg = < 0x7e203000 0x24>;
clocks = <&clocks BCM2835_CLOCK_PCM>;
dmas = <&dma 2>,
<&dma 3>;

33
Documentation/devicetree/bindings/dma/mtk-hsdma.txt Normal file
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@ -0,0 +1,33 @@
MediaTek High-Speed DMA Controller
==================================
This device follows the generic DMA bindings defined in dma/dma.txt.
Required properties:
- compatible: Must be one of
"mediatek,mt7622-hsdma": for MT7622 SoC
"mediatek,mt7623-hsdma": for MT7623 SoC
- reg: Should contain the register's base address and length.
- interrupts: Should contain a reference to the interrupt used by this
device.
- clocks: Should be the clock specifiers corresponding to the entry in
clock-names property.
- clock-names: Should contain "hsdma" entries.
- power-domains: Phandle to the power domain that the device is part of
- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
in dmas property of a client device represents the channel
number.
Example:
hsdma: dma-controller@1b007000 {
compatible = "mediatek,mt7623-hsdma";
reg = <0 0x1b007000 0 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
clocks = <&ethsys CLK_ETHSYS_HSDMA>;
clock-names = "hsdma";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
#dma-cells = <1>;
};
DMA clients must use the format described in dma/dma.txt file.

4
Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
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@ -15,6 +15,10 @@ Required properties:
the secure world.
- qcom,controlled-remotely : optional, indicates that the bam is controlled by
remote proccessor i.e. execution environment.
- num-channels : optional, indicates supported number of DMA channels in a
remotely controlled bam.
- qcom,num-ees : optional, indicates supported number of Execution Environments
in a remotely controlled bam.
Example:

2
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
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@ -18,6 +18,7 @@ Required Properties:
Examples with soctypes are:
- "renesas,dmac-r8a7743" (RZ/G1M)
- "renesas,dmac-r8a7745" (RZ/G1E)
- "renesas,dmac-r8a77470" (RZ/G1C)
- "renesas,dmac-r8a7790" (R-Car H2)
- "renesas,dmac-r8a7791" (R-Car M2-W)
- "renesas,dmac-r8a7792" (R-Car V2H)
@ -26,6 +27,7 @@ Required Properties:
- "renesas,dmac-r8a7795" (R-Car H3)
- "renesas,dmac-r8a7796" (R-Car M3-W)
- "renesas,dmac-r8a77970" (R-Car V3M)
- "renesas,dmac-r8a77980" (R-Car V3H)
- reg: base address and length of the registers block for the DMAC

1
Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
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@ -11,6 +11,7 @@ Required Properties:
- "renesas,r8a7794-usb-dmac" (R-Car E2)
- "renesas,r8a7795-usb-dmac" (R-Car H3)
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
- "renesas,r8a77965-usb-dmac" (R-Car M3-N)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.

41
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt Normal file
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@ -0,0 +1,41 @@
Synopsys DesignWare AXI DMA Controller
Required properties:
- compatible: "snps,axi-dma-1.01a"
- reg: Address range of the DMAC registers. This should include
all of the per-channel registers.
- interrupt: Should contain the DMAC interrupt number.
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device.
- dma-channels: Number of channels supported by hardware.
- snps,dma-masters: Number of AXI masters supported by the hardware.
- snps,data-width: Maximum AXI data width supported by hardware.
(0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
- snps,priority: Priority of channel. Array size is equal to the number of
dma-channels. Priority value must be programmed within [0:dma-channels-1]
range. (0 - minimum priority)
- snps,block-size: Maximum block size supported by the controller channel.
Array size is equal to the number of dma-channels.
Optional properties:
- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
in this property. If this property is missing the maximum AXI burst length
supported by DMAC is used. [1:256]
Example:
dmac: dma-controller@80000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x80000 0x400>;
clocks = <&core_clk>, <&cfgr_clk>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <27>;
dma-channels = <4>;
snps,dma-masters = <2>;
snps,data-width = <3>;
snps,block-size = <4096 4096 4096 4096>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <16>;
};

6
Documentation/devicetree/bindings/dma/stm32-dma.txt
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@ -62,14 +62,14 @@ channel: a phandle to the DMA controller plus the following four integer cells:
0x1: medium
0x2: high
0x3: very high
4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
dependent:
-bit 0-1: Fifo threshold
4. A 32bit bitfield value specifying DMA features which are device dependent:
-bit 0-1: DMA FIFO threshold selection
0x0: 1/4 full FIFO
0x1: 1/2 full FIFO
0x2: 3/4 full FIFO
0x3: full FIFO
Example:
usart1: serial@40011000 {

4
Documentation/devicetree/bindings/eeprom/at24.txt
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@ -41,12 +41,16 @@ Required properties:
"nxp",
"ramtron",
"renesas",
"rohm",
"st",
Some vendors use different model names for chips which are just
variants of the above. Known such exceptions are listed below:
"nxp,se97b" - the fallback is "atmel,24c02",
"renesas,r1ex24002" - the fallback is "atmel,24c02"
"renesas,r1ex24128" - the fallback is "atmel,24c128"
"rohm,br24t01" - the fallback is "atmel,24c01"
- reg: The I2C address of the EEPROM.

1
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
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@ -10,6 +10,7 @@ Required properties:
* And, optionally, one of the vendor specific compatible:
+ allwinner,sun4i-a10-mali
+ allwinner,sun7i-a20-mali
+ allwinner,sun8i-h3-mali
+ allwinner,sun50i-h5-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali

2
Documentation/devicetree/bindings/i2c/i2c-rcar.txt
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@ -13,7 +13,9 @@ Required properties:
"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
"renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
"renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
device.

1
Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
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@ -13,6 +13,7 @@ Required properties:
- "renesas,iic-r8a7794" (R-Car E2)
- "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-r8a7796" (R-Car M3-W)
- "renesas,iic-r8a77965" (R-Car M3-N)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
compatible device)

29
Documentation/devicetree/bindings/i2c/i2c-synquacer.txt Normal file
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@ -0,0 +1,29 @@
Socionext SynQuacer I2C
Required properties:
- compatible : Must be "socionext,synquacer-i2c"
- reg : Offset and length of the register set for the device
- interrupts : A single interrupt specifier
- #address-cells : Must be <1>;
- #size-cells : Must be <0>;
- clock-names : Must contain "pclk".
- clocks : Must contain an entry for each name in clock-names.
(See the common clock bindings.)
Optional properties:
- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
Fast modes are supported, possible values are 100000 and
400000.
Example :
i2c@51210000 {
compatible = "socionext,synquacer-i2c";
reg = <0x51210000 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "pclk";
clocks = <&clk_i2c>;
clock-frequency = <400000>;
};

8
Documentation/devicetree/bindings/input/gpio-keys.txt
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@ -26,6 +26,14 @@ Optional subnode-properties:
If not specified defaults to 5.
- wakeup-source: Boolean, button can wake-up the system.
(Legacy property supported: "gpio-key,wakeup")
- wakeup-event-action: Specifies whether the key should wake the
system when asserted, when deasserted, or both. This property is
only valid for keys that wake up the system (e.g., when the
"wakeup-source" property is also provided).
Supported values are defined in linux-event-codes.h:
EV_ACT_ASSERTED - asserted
EV_ACT_DEASSERTED - deasserted
EV_ACT_ANY - both asserted and deasserted
- linux,can-disable: Boolean, indicates that button is connected
to dedicated (not shared) interrupt which can be disabled to
suppress events from the button.

22
Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt Normal file
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@ -0,0 +1,22 @@
Zodiac Inflight Innovations RAVE Supervisory Processor Power Button Bindings
RAVE SP input device is a "MFD cell" device corresponding to power
button functionality of RAVE Supervisory Processor. It is expected
that its Device Tree node is specified as a child of the node
corresponding to the parent RAVE SP device (as documented in
Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
Required properties:
- compatible: Should be "zii,rave-sp-pwrbutton"
Example:
rave-sp {
compatible = "zii,rave-sp-rdu1";
current-speed = <38400>;
pwrbutton {
compatible = "zii,rave-sp-pwrbutton";
};
}

5
Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
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@ -11,6 +11,8 @@ Required Properties:
the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
- "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
- "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
- "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
- "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
- "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
@ -19,7 +21,8 @@ Required Properties:
- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
- "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.
- "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
IPMMU.
- reg: Base address and size of the IPMMU registers.
- interrupts: Specifiers for the MMU fault interrupts. For instances that

7
Documentation/devicetree/bindings/iommu/rockchip,iommu.txt
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@ -14,6 +14,11 @@ Required properties:
"single-master" device, and needs no additional information
to associate with its master device. See:
Documentation/devicetree/bindings/iommu/iommu.txt
- clocks : A list of clocks required for the IOMMU to be accessible by
the host CPU.
- clock-names : Should contain the following:
"iface" - Main peripheral bus clock (PCLK/HCL) (required)
"aclk" - AXI bus clock (required)
Optional properties:
- rockchip,disable-mmu-reset : Don't use the mmu reset operation.
@ -27,5 +32,7 @@ Example:
reg = <0xff940300 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
};

51
Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt Normal file
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@ -0,0 +1,51 @@
Hisilicon Hi3660 Mailbox Controller
Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages
are passed between processors, including application & communication
processors, MCU, HIFI, etc. Each channel is unidirectional and accessed
by using MMIO registers; it supports maximum to 8 words message.
Controller
----------
Required properties:
- compatible: : Shall be "hisilicon,hi3660-mbox"
- reg: : Offset and length of the device's register set
- #mbox-cells: : Must be 3
<&phandle channel dst_irq ack_irq>
phandle : Label name of controller
channel : Channel number
dst_irq : Remote interrupt vector
ack_irq : Local interrupt vector
- interrupts: : Contains the two IRQ lines for mailbox.
Example:
mailbox: mailbox@e896b000 {
compatible = "hisilicon,hi3660-mbox";
reg = <0x0 0xe896b000 0x0 0x1000>;
interrupts = <0x0 0xc0 0x4>,
<0x0 0xc1 0x4>;
#mbox-cells = <3>;
};
Client
------
Required properties:
- compatible : See the client docs
- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
Cells must match 'mbox-cells' (See Controller docs above)
Optional properties
- mbox-names : Name given to channels seen in the 'mboxes' property.
Example:
stub_clock: stub_clock@e896b500 {
compatible = "hisilicon,hi3660-stub-clk";
reg = <0x0 0xe896b500 0x0 0x0100>;
#clock-cells = <1>;
mboxes = <&mailbox 13 3 0>;
};

28
Documentation/devicetree/bindings/mailbox/mailbox.txt
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@ -23,6 +23,11 @@ Required property:
Optional property:
- mbox-names: List of identifier strings for each mailbox channel.
- shmem : List of phandle pointing to the shared memory(SHM) area between the
users of these mailboxes for IPC, one for each mailbox. This shared
memory can be part of any memory reserved for the purpose of this
communication between the mailbox client and the remote.
Example:
pwr_cntrl: power {
@ -30,3 +35,26 @@ Example:
mbox-names = "pwr-ctrl", "rpc";
mboxes = <&mailbox 0 &mailbox 1>;
};
Example with shared memory(shmem):
sram: sram@50000000 {
compatible = "mmio-sram";
reg = <0x50000000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50000000 0x10000>;
cl_shmem: shmem@0 {
compatible = "client-shmem";
reg = <0x0 0x200>;
};
};
client@2e000000 {
...
mboxes = <&mailbox 0>;
shmem = <&cl_shmem>;
..
};

13
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
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@ -3,7 +3,9 @@
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it.
of the EMIF IP and memory parts attached to it. Certain revisions
of the EMIF controller also contain optional ECC support, which
corrects one bit errors and detects two bit errors.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
@ -11,6 +13,8 @@ Required properties:
compatible should be one of the following:
"ti,emif-am3352"
"ti,emif-am4372"
"ti,emif-dra7xx"
"ti,emif-keystone"
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
@ -22,6 +26,7 @@ Required properties:
- ti,hwmods : For TI hwmods processing and omap device creation
the value shall be "emif<n>" where <n> is the number of the EMIF
instance with base 1.
- interrupts : interrupt used by the controller
Required only for "ti,emif-am3352" and "ti,emif-am4372":
- sram : Phandles for generic sram driver nodes,
@ -71,3 +76,9 @@ emif: emif@4c000000 {
sram = <&pm_sram_code
&pm_sram_data>;
};
emif1: emif@4c000000 {
compatible = "ti,emif-dra7xx";
reg = <0x4c000000 0x200>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};

21
Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
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@ -176,3 +176,24 @@ lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
LPC reset control
-----------------
The UARTs present in the ASPEED SoC can have their resets tied to the reset
state of the LPC bus. Some systems may chose to modify this configuration.
Required properties:
- compatible: "aspeed,ast2500-lpc-reset" or
"aspeed,ast2400-lpc-reset"
- reg: offset and length of the IP in the LHC memory region
- #reset-controller indicates the number of reset cells expected
Example:
lpc_reset: reset-controller@18 {
compatible = "aspeed,ast2500-lpc-reset";
reg = <0x18 0x4>;
#reset-cells = <1>;
};

43
Documentation/devicetree/bindings/mips/mscc.txt Normal file
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@ -0,0 +1,43 @@
* Microsemi MIPS CPUs
Boards with a SoC of the Microsemi MIPS family shall have the following
properties:
Required properties:
- compatible: "mscc,ocelot"
* Other peripherals:
o CPU chip regs:
The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
functionalities: chip ID, general purpose register for software use, reset
controller, hardware status and configuration, efuses.
Required properties:
- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
- reg : Should contain registers location and length
Example:
syscon@71070000 {
compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
reg = <0x71070000 0x1c>;
};
o CPU system control:
The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
endianness, CPU bus control, CPU status.
Required properties:
- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
- reg : Should contain registers location and length
Example:
syscon@70000000 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x70000000 0x2c>;
};

4
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
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@ -21,7 +21,7 @@ Required Properties:
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
Optional Properties:
* clocks: from common clock binding: if ciu_drive and ciu_sample are
* clocks: from common clock binding: if ciu-drive and ciu-sample are
specified in clock-names, should contain handles to these clocks.
* clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt
@ -29,7 +29,7 @@ Optional Properties:
to control the clock phases, "ciu-sample" is required for tuning high-
speed modes.
* rockchip,default-sample-phase: The default phase to set ciu_sample at
* rockchip,default-sample-phase: The default phase to set ciu-sample at
probing, low speeds or in case where all phases work at tuning time.
If not specified 0 deg will be used.

24
Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
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@ -39,3 +39,27 @@ qspi0: quadspi@40044000 {
....
};
};
Example showing the usage of two SPI NOR devices:
&qspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
reg = <0>;
};
flash1: n25q256a@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
reg = <1>;
};
};

5
Documentation/devicetree/bindings/mtd/marvell-nand.txt
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@ -14,7 +14,10 @@ Required properties:
- #address-cells: shall be set to 1. Encode the NAND CS.
- #size-cells: shall be set to 0.
- interrupts: shall define the NAND controller interrupt.
- clocks: shall reference the NAND controller clock.
- clocks: shall reference the NAND controller clocks, the second one is
is only needed for the Armada 7K/8K SoCs
- clock-names: mandatory if there is a second clock, in this case there
should be one clock named "core" and another one named "reg"
- marvell,system-controller: Set to retrieve the syscon node that handles
NAND controller related registers (only required with the
"marvell,armada-8k-nand[-controller]" compatibles).

7
Documentation/devicetree/bindings/mtd/mtd-physmap.txt
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@ -41,6 +41,13 @@ additional (optional) property is defined:
- erase-size : The chip's physical erase block size in bytes.
The device tree may optionally contain endianness property.
little-endian or big-endian : It Represents the endianness that should be used
by the controller to properly read/write data
from/to the flash. If this property is missing,
the endianness is chosen by the system
(potentially based on extra configuration options).
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.

50
Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
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@ -1,50 +0,0 @@
PXA3xx NAND DT bindings
Required properties:
- compatible: Should be set to one of the following:
marvell,pxa3xx-nand
marvell,armada370-nand
marvell,armada-8k-nand
- reg: The register base for the controller
- interrupts: The interrupt to map
- #address-cells: Set to <1> if the node includes partitions
- marvell,system-controller: Set to retrieve the syscon node that handles
NAND controller related registers (only required
with marvell,armada-8k-nand compatible).
Optional properties:
- dmas: dma data channel, see dma.txt binding doc
- marvell,nand-enable-arbiter: Set to enable the bus arbiter
- marvell,nand-keep-config: Set to keep the NAND controller config as set
by the bootloader
- num-cs: Number of chipselect lines to use
- nand-on-flash-bbt: boolean to enable on flash bbt option if
not present false
- nand-ecc-strength: number of bits to correct per ECC step
- nand-ecc-step-size: number of data bytes covered by a single ECC step
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <1>, nand-ecc-step-size = <512>
- nand-ecc-strength = <4>, nand-ecc-step-size = <512>
- nand-ecc-strength = <8>, nand-ecc-step-size = <512>
Example:
nand0: nand@43100000 {
compatible = "marvell,pxa3xx-nand";
reg = <0x43100000 90>;
interrupts = <45>;
dmas = <&pdma 97 0>;
dma-names = "data";
#address-cells = <1>;
marvell,nand-enable-arbiter;
marvell,nand-keep-config;
num-cs = <1>;
/* partitions (optional) */
};

4
Documentation/devicetree/bindings/mtd/sunxi-nand.txt
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@ -24,8 +24,8 @@ Optional properties:
- allwinner,rb : shall contain the native Ready/Busy ids.
or
- rb-gpios : shall contain the gpios used as R/B pins.
- nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft",
"soft_bch" or "none")
- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
"none")
see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.

6
Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
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@ -6,7 +6,11 @@ the definition of the PHY node in booting-without-of.txt for an example
of how to define a PHY.
Required properties:
- reg : Offset and length of the register set for the device
- reg : Offset and length of the register set for the device, and optionally
the offset and length of the TBIPA register (TBI PHY address
register). If TBIPA register is not specified, the driver will
attempt to infer it from the register set specified (your mileage may
vary).
- compatible : Should define the compatible device type for the
mdio. Currently supported strings/devices are:
- "fsl,gianfar-tbi"

1
Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
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@ -34,6 +34,7 @@ Required properties
Optional properties:
- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
- vpcie-supply: The regulator in charge of PCIe port power.
- phys: List of phandle and phy mode specifier, should be 0.
- phy-names: Must be "phy".

11
Documentation/devicetree/bindings/pci/mediatek-pcie.txt
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@ -78,7 +78,7 @@ Examples for MT7623:
#reset-cells = <1>;
};
pcie: pcie-controller@1a140000 {
pcie: pcie@1a140000 {
compatible = "mediatek,mt7623-pcie";
device_type = "pci";
reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
@ -111,7 +111,6 @@ Examples for MT7623:
0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
pcie@0,0 {
device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@ -123,7 +122,6 @@ Examples for MT7623:
};
pcie@1,0 {
device_type = "pci";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@ -135,7 +133,6 @@ Examples for MT7623:
};
pcie@2,0 {
device_type = "pci";
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@ -148,6 +145,7 @@ Examples for MT7623:
};
Examples for MT2712:
pcie: pcie@11700000 {
compatible = "mediatek,mt2712-pcie";
device_type = "pci";
@ -169,7 +167,6 @@ Examples for MT2712:
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
pcie0: pcie@0,0 {
device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@ -189,7 +186,6 @@ Examples for MT2712:
};
pcie1: pcie@1,0 {
device_type = "pci";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@ -210,6 +206,7 @@ Examples for MT2712:
};
Examples for MT7622:
pcie: pcie@1a140000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
@ -243,7 +240,6 @@ Examples for MT7622:
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
pcie0: pcie@0,0 {
device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@ -263,7 +259,6 @@ Examples for MT7622:
};
pcie1: pcie@1,0 {
device_type = "pci";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;

4
Documentation/devicetree/bindings/pci/qcom,pcie.txt
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@ -189,6 +189,10 @@
Value type: <phandle>
Definition: A phandle to the analog power supply for IC which generates
reference clock
- vddpe-3v3-supply:
Usage: optional
Value type: <phandle>
Definition: A phandle to the PCIe endpoint power supply
- phys:
Usage: required for apq8084

6
Documentation/devicetree/bindings/pci/rcar-pci.txt
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@ -1,13 +1,15 @@
* Renesas R-Car PCIe interface
Required properties:
compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
"renesas,pcie-r8a7779" for the R8A7779 SoC;
"renesas,pcie-r8a7790" for the R8A7790 SoC;
"renesas,pcie-r8a7791" for the R8A7791 SoC;
"renesas,pcie-r8a7793" for the R8A7793 SoC;
"renesas,pcie-r8a7795" for the R8A7795 SoC;
"renesas,pcie-r8a7796" for the R8A7796 SoC;
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
RZ/G1 compatible device.
"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
When compatible with the generic version, nodes must list the

0
Documentation/devicetree/bindings/arm/ccn.txt → Documentation/devicetree/bindings/perf/arm-ccn.txt
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4
Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
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@ -21,7 +21,9 @@ Required properties :
- timer: The timeout clock (clk_m). Present if phy_type == utmi.
- utmi-pads: The clock needed to access the UTMI pad control registers.
Present if phy_type == utmi.
- ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
- ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
with pad group aka "nvidia,pins" cdev2 and pin mux option config aka
"nvidia,function" pllp_out4).
Present if phy_type == ulpi, and ULPI link mode is in use.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.

1
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
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@ -11,6 +11,7 @@ Required properies:
"st,stm32f429-pinctrl"
"st,stm32f469-pinctrl"
"st,stm32f746-pinctrl"
"st,stm32f769-pinctrl"
"st,stm32h743-pinctrl"
"st,stm32mp157-pinctrl"
"st,stm32mp157-z-pinctrl"

65
Documentation/devicetree/bindings/pmem/pmem-region.txt Normal file
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@ -0,0 +1,65 @@
Device-tree bindings for persistent memory regions
-----------------------------------------------------
Persistent memory refers to a class of memory devices that are:
a) Usable as main system memory (i.e. cacheable), and
b) Retain their contents across power failure.
Given b) it is best to think of persistent memory as a kind of memory mapped
storage device. To ensure data integrity the operating system needs to manage
persistent regions separately to the normal memory pool. To aid with that this
binding provides a standardised interface for discovering where persistent
memory regions exist inside the physical address space.
Bindings for the region nodes:
-----------------------------
Required properties:
- compatible = "pmem-region"
- reg = <base, size>;
The reg property should specificy an address range that is
translatable to a system physical address range. This address
range should be mappable as normal system memory would be
(i.e cacheable).
If the reg property contains multiple address ranges
each address range will be treated as though it was specified
in a separate device node. Having multiple address ranges in a
node implies no special relationship between the two ranges.
Optional properties:
- Any relevant NUMA assocativity properties for the target platform.
- volatile; This property indicates that this region is actually
backed by non-persistent memory. This lets the OS know that it
may skip the cache flushes required to ensure data is made
persistent after a write.
If this property is absent then the OS must assume that the region
is backed by non-volatile memory.
Examples:
--------------------
/*
* This node specifies one 4KB region spanning from
* 0x5000 to 0x5fff that is backed by non-volatile memory.
*/
pmem@5000 {
compatible = "pmem-region";
reg = <0x00005000 0x00001000>;
};
/*
* This node specifies two 4KB regions that are backed by
* volatile (normal) memory.
*/
pmem@6000 {
compatible = "pmem-region";
reg = < 0x00006000 0x00001000
0x00008000 0x00001000 >;
volatile;
};

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