drm/tegra: Implement more tiling modes
Tegra124 supports a block-linear mode in addition to the regular pitch linear and tiled modes. Add support for these by moving the internal representation into a structure rather than a simple flag. Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
Родитель
0c6b1e4ba7
Коммит
c134f019ab
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@ -18,6 +18,7 @@
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struct tegra_dc_soc_info {
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bool supports_interlacing;
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bool supports_cursor;
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bool supports_block_linear;
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};
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struct tegra_plane {
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@ -212,15 +213,44 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
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tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
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tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
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if (window->tiled) {
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value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
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DC_WIN_BUFFER_ADDR_MODE_TILE;
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} else {
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value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
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DC_WIN_BUFFER_ADDR_MODE_LINEAR;
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}
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if (dc->soc->supports_block_linear) {
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unsigned long height = window->tiling.value;
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tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
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switch (window->tiling.mode) {
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case TEGRA_BO_TILING_MODE_PITCH:
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value = DC_WINBUF_SURFACE_KIND_PITCH;
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break;
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case TEGRA_BO_TILING_MODE_TILED:
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value = DC_WINBUF_SURFACE_KIND_TILED;
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break;
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case TEGRA_BO_TILING_MODE_BLOCK:
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value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
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DC_WINBUF_SURFACE_KIND_BLOCK;
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break;
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}
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tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
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} else {
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switch (window->tiling.mode) {
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case TEGRA_BO_TILING_MODE_PITCH:
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value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
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DC_WIN_BUFFER_ADDR_MODE_LINEAR;
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break;
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case TEGRA_BO_TILING_MODE_TILED:
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value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
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DC_WIN_BUFFER_ADDR_MODE_TILE;
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break;
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case TEGRA_BO_TILING_MODE_BLOCK:
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DRM_ERROR("hardware doesn't support block linear mode\n");
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return -EINVAL;
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}
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tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
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}
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value = WIN_ENABLE;
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@ -288,6 +318,7 @@ static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
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struct tegra_dc *dc = to_tegra_dc(crtc);
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struct tegra_dc_window window;
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unsigned int i;
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int err;
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memset(&window, 0, sizeof(window));
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window.src.x = src_x >> 16;
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@ -301,7 +332,10 @@ static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
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window.format = tegra_dc_format(fb->pixel_format, &window.swap);
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window.bits_per_pixel = fb->bits_per_pixel;
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window.bottom_up = tegra_fb_is_bottom_up(fb);
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window.tiled = tegra_fb_is_tiled(fb);
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err = tegra_fb_get_tiling(fb, &window.tiling);
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if (err < 0)
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return err;
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for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
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struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
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@ -402,8 +436,14 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
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{
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struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
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unsigned int h_offset = 0, v_offset = 0;
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struct tegra_bo_tiling tiling;
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unsigned int format, swap;
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unsigned long value;
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int err;
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err = tegra_fb_get_tiling(fb, &tiling);
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if (err < 0)
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return err;
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tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
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@ -417,15 +457,44 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
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tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
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tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
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if (tegra_fb_is_tiled(fb)) {
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value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
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DC_WIN_BUFFER_ADDR_MODE_TILE;
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} else {
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value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
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DC_WIN_BUFFER_ADDR_MODE_LINEAR;
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}
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if (dc->soc->supports_block_linear) {
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unsigned long height = tiling.value;
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tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
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switch (tiling.mode) {
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case TEGRA_BO_TILING_MODE_PITCH:
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value = DC_WINBUF_SURFACE_KIND_PITCH;
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break;
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case TEGRA_BO_TILING_MODE_TILED:
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value = DC_WINBUF_SURFACE_KIND_TILED;
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break;
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case TEGRA_BO_TILING_MODE_BLOCK:
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value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
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DC_WINBUF_SURFACE_KIND_BLOCK;
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break;
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}
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tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
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} else {
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switch (tiling.mode) {
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case TEGRA_BO_TILING_MODE_PITCH:
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value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
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DC_WIN_BUFFER_ADDR_MODE_LINEAR;
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break;
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case TEGRA_BO_TILING_MODE_TILED:
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value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
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DC_WIN_BUFFER_ADDR_MODE_TILE;
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break;
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case TEGRA_BO_TILING_MODE_BLOCK:
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DRM_ERROR("hardware doesn't support block linear mode\n");
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return -EINVAL;
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}
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tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
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}
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/* make sure bottom-up buffers are properly displayed */
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if (tegra_fb_is_bottom_up(fb)) {
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@ -1277,16 +1346,19 @@ static const struct host1x_client_ops dc_client_ops = {
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static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
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.supports_interlacing = false,
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.supports_cursor = false,
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.supports_block_linear = false,
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};
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static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
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.supports_interlacing = false,
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.supports_cursor = false,
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.supports_block_linear = false,
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};
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static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
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.supports_interlacing = true,
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.supports_cursor = true,
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.supports_block_linear = true,
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};
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static const struct of_device_id tegra_dc_of_match[] = {
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@ -428,6 +428,11 @@
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#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
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#define DC_WINBUF_UFLOW_STATUS 0x80a
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#define DC_WINBUF_SURFACE_KIND 0x80b
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#define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
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#define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
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#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
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#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
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#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
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#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
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@ -19,6 +19,8 @@
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fixed.h>
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#include "gem.h"
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struct reset_control;
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struct tegra_fb {
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@ -160,7 +162,8 @@ struct tegra_dc_window {
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unsigned int stride[2];
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unsigned long base[3];
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bool bottom_up;
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bool tiled;
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struct tegra_bo_tiling tiling;
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};
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/* from dc.c */
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@ -279,7 +282,8 @@ int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
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struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
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unsigned int index);
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bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer);
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bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer);
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int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
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struct tegra_bo_tiling *tiling);
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int tegra_drm_fb_prepare(struct drm_device *drm);
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int tegra_drm_fb_init(struct drm_device *drm);
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void tegra_drm_fb_exit(struct drm_device *drm);
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@ -46,14 +46,15 @@ bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer)
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return false;
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}
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bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer)
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int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
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struct tegra_bo_tiling *tiling)
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{
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struct tegra_fb *fb = to_tegra_fb(framebuffer);
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if (fb->planes[0]->flags & TEGRA_BO_TILED)
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return true;
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/* TODO: handle YUV formats? */
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*tiling = fb->planes[0]->tiling;
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return false;
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return 0;
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}
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static void tegra_fb_destroy(struct drm_framebuffer *framebuffer)
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@ -126,7 +126,7 @@ struct tegra_bo *tegra_bo_create(struct drm_device *drm, unsigned int size,
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goto err_mmap;
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if (flags & DRM_TEGRA_GEM_CREATE_TILED)
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bo->flags |= TEGRA_BO_TILED;
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bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED;
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if (flags & DRM_TEGRA_GEM_CREATE_BOTTOM_UP)
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bo->flags |= TEGRA_BO_BOTTOM_UP;
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@ -16,8 +16,18 @@
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#include <drm/drm.h>
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#include <drm/drmP.h>
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#define TEGRA_BO_TILED (1 << 0)
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#define TEGRA_BO_BOTTOM_UP (1 << 1)
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#define TEGRA_BO_BOTTOM_UP (1 << 0)
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enum tegra_bo_tiling_mode {
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TEGRA_BO_TILING_MODE_PITCH,
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TEGRA_BO_TILING_MODE_TILED,
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TEGRA_BO_TILING_MODE_BLOCK,
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};
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struct tegra_bo_tiling {
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enum tegra_bo_tiling_mode mode;
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unsigned long value;
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};
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struct tegra_bo {
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struct drm_gem_object gem;
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@ -26,6 +36,8 @@ struct tegra_bo {
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struct sg_table *sgt;
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dma_addr_t paddr;
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void *vaddr;
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struct tegra_bo_tiling tiling;
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};
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static inline struct tegra_bo *to_tegra_bo(struct drm_gem_object *gem)
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