omapdss: HDMI: create a PLL library
HDMI PLL is a block common to DSS in OMAP4, OMAP5 and DRA7x. Move the existing PLL functions from ti_hdmi_4xxx_ip.c and hdmi.c to a separate file. These funcs are called directly from the hdmi driver rather than hdmi_ip_ops function pointer calls. Add the PLL library function declarations to ti_hdmi.h. These will be shared amongst the omap4/5 hdmi platform drivers. Remove the PLL function pointer ops from the ti_hdmi_ip_ops struct. These will be shared amongst the omap4/5 hdmi platform drivers and other libraries. The DT/hwmod information for hdmi doesn't split the address space according to the required sub blocks. Keep the address offset and size information in the driver for now. This will be removed when the driver gets the information correctly from DT/hwmod. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Archit Taneja
Tomi Valkeinen
Родитель
f382d9eb82
Коммит
c1577c1ea0
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@ -10,5 +10,5 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
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omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
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omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
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omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
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omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o hdmi_wp.o ti_hdmi_4xxx_ip.o
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omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o hdmi_wp.o hdmi_pll.o ti_hdmi_4xxx_ip.o
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ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG
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@ -797,10 +797,7 @@ static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
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.phy_enable = ti_hdmi_4xxx_phy_enable,
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.phy_disable = ti_hdmi_4xxx_phy_disable,
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.read_edid = ti_hdmi_4xxx_read_edid,
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.pll_enable = ti_hdmi_4xxx_pll_enable,
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.pll_disable = ti_hdmi_4xxx_pll_disable,
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.dump_core = ti_hdmi_4xxx_core_dump,
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.dump_pll = ti_hdmi_4xxx_pll_dump,
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.dump_phy = ti_hdmi_4xxx_phy_dump,
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#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
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.audio_start = ti_hdmi_4xxx_audio_start,
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@ -42,7 +42,6 @@
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#define HDMI_CORE_SYS 0x400
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#define HDMI_CORE_AV 0x900
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#define HDMI_PLLCTRL 0x200
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#define HDMI_PHY 0x300
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/* HDMI EDID Length move this */
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@ -53,9 +52,6 @@
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#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
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#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
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#define HDMI_DEFAULT_REGN 16
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#define HDMI_DEFAULT_REGM2 1
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static struct {
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struct mutex lock;
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struct platform_device *pdev;
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@ -428,52 +424,6 @@ end: return cm;
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}
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static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
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struct hdmi_pll_info *pi)
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{
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unsigned long clkin, refclk;
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u32 mf;
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clkin = clk_get_rate(hdmi.sys_clk) / 10000;
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/*
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* Input clock is predivided by N + 1
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* out put of which is reference clk
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*/
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pi->regn = HDMI_DEFAULT_REGN;
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refclk = clkin / pi->regn;
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pi->regm2 = HDMI_DEFAULT_REGM2;
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/*
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* multiplier is pixel_clk/ref_clk
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* Multiplying by 100 to avoid fractional part removal
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*/
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pi->regm = phy * pi->regm2 / refclk;
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/*
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* fractional multiplier is remainder of the difference between
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* multiplier and actual phy(required pixel clock thus should be
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* multiplied by 2^18(262144) divided by the reference clock
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*/
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mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
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pi->regmf = pi->regm2 * mf / refclk;
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/*
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* Dcofreq should be set to 1 if required pixel clock
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* is greater than 1000MHz
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*/
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pi->dcofreq = phy > 1000 * 100;
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pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
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/* Set the reference clock to sysclk reference */
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pi->refsel = HDMI_REFSEL_SYSCLK;
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DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
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DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
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}
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static int hdmi_power_on_core(struct omap_dss_device *dssdev)
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{
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int r;
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@ -526,12 +476,12 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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phy = p->pixel_clock;
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hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
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hdmi_pll_compute(&hdmi.ip_data.pll, clk_get_rate(hdmi.sys_clk), phy);
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hdmi_wp_video_stop(&hdmi.ip_data.wp);
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/* config the PLL and PHY hdmi_set_pll_pwrfirst */
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r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
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r = hdmi_pll_enable(&hdmi.ip_data.pll, &hdmi.ip_data.wp);
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if (r) {
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DSSDBG("Failed to lock PLL\n");
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goto err_pll_enable;
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@ -566,7 +516,7 @@ err_mgr_enable:
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err_vid_enable:
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hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
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err_phy_enable:
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hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
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hdmi_pll_disable(&hdmi.ip_data.pll, &hdmi.ip_data.wp);
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err_pll_enable:
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hdmi_power_off_core(dssdev);
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return -EIO;
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@ -580,7 +530,7 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev)
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hdmi_wp_video_stop(&hdmi.ip_data.wp);
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hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
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hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
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hdmi_pll_disable(&hdmi.ip_data.pll, &hdmi.ip_data.wp);
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hdmi_power_off_core(dssdev);
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}
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@ -642,7 +592,7 @@ static void hdmi_dump_regs(struct seq_file *s)
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}
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hdmi_wp_dump(&hdmi.ip_data.wp, s);
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hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
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hdmi_pll_dump(&hdmi.ip_data.pll, s);
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hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
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hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
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@ -1095,6 +1045,10 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev)
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if (r)
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return r;
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r = hdmi_pll_init(pdev, &hdmi.ip_data.pll);
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if (r)
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return r;
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hdmi.ip_data.irq = platform_get_irq(pdev, 0);
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if (hdmi.ip_data.irq < 0) {
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DSSERR("platform_get_irq failed\n");
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@ -1111,7 +1065,6 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev)
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hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
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hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
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hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
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hdmi.ip_data.phy_offset = HDMI_PHY;
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hdmi_init_output(pdev);
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@ -0,0 +1,261 @@
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/*
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* HDMI PLL
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*
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* Copyright (C) 2013 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <video/omapdss.h>
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#include "dss.h"
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#include "ti_hdmi.h"
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#include "ti_hdmi_4xxx_ip.h"
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#define HDMI_DEFAULT_REGN 16
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#define HDMI_DEFAULT_REGM2 1
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static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,
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u32 val)
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{
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__raw_writel(val, base_addr + idx);
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}
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static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)
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{
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return __raw_readl(base_addr + idx);
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}
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#define REG_FLD_MOD(base, idx, val, start, end) \
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hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
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val, start, end))
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#define REG_GET(base, idx, start, end) \
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FLD_GET(hdmi_read_reg(base, idx), start, end)
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static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
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const u16 idx, int b2, int b1, u32 val)
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{
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u32 t = 0;
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while (val != REG_GET(base_addr, idx, b2, b1)) {
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udelay(1);
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if (t++ > 10000)
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return !val;
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}
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return val;
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}
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void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
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{
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#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
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hdmi_read_reg(pll->base, r))
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DUMPPLL(PLLCTRL_PLL_CONTROL);
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DUMPPLL(PLLCTRL_PLL_STATUS);
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DUMPPLL(PLLCTRL_PLL_GO);
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DUMPPLL(PLLCTRL_CFG1);
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DUMPPLL(PLLCTRL_CFG2);
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DUMPPLL(PLLCTRL_CFG3);
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DUMPPLL(PLLCTRL_SSC_CFG1);
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DUMPPLL(PLLCTRL_SSC_CFG2);
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DUMPPLL(PLLCTRL_CFG4);
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}
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void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy)
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{
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struct hdmi_pll_info *pi = &pll->info;
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unsigned long refclk;
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u32 mf;
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/* use our funky units */
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clkin /= 10000;
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/*
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* Input clock is predivided by N + 1
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* out put of which is reference clk
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*/
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pi->regn = HDMI_DEFAULT_REGN;
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refclk = clkin / pi->regn;
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pi->regm2 = HDMI_DEFAULT_REGM2;
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/*
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* multiplier is pixel_clk/ref_clk
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* Multiplying by 100 to avoid fractional part removal
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*/
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pi->regm = phy * pi->regm2 / refclk;
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/*
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* fractional multiplier is remainder of the difference between
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* multiplier and actual phy(required pixel clock thus should be
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* multiplied by 2^18(262144) divided by the reference clock
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*/
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mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
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pi->regmf = pi->regm2 * mf / refclk;
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/*
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* Dcofreq should be set to 1 if required pixel clock
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* is greater than 1000MHz
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*/
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pi->dcofreq = phy > 1000 * 100;
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pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
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/* Set the reference clock to sysclk reference */
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pi->refsel = HDMI_REFSEL_SYSCLK;
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DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
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DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
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}
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static int hdmi_pll_config(struct hdmi_pll_data *pll)
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{
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u32 r;
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struct hdmi_pll_info *fmt = &pll->info;
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/* PLL start always use manual mode */
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REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
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r = hdmi_read_reg(pll->base, PLLCTRL_CFG1);
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r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
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r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
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hdmi_write_reg(pll->base, PLLCTRL_CFG1, r);
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r = hdmi_read_reg(pll->base, PLLCTRL_CFG2);
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r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
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r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
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r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
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r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
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if (fmt->dcofreq) {
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/* divider programming for frequency beyond 1000Mhz */
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REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
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r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
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} else {
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r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
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}
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hdmi_write_reg(pll->base, PLLCTRL_CFG2, r);
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r = hdmi_read_reg(pll->base, PLLCTRL_CFG4);
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r = FLD_MOD(r, fmt->regm2, 24, 18);
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r = FLD_MOD(r, fmt->regmf, 17, 0);
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hdmi_write_reg(pll->base, PLLCTRL_CFG4, r);
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/* go now */
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REG_FLD_MOD(pll->base, PLLCTRL_PLL_GO, 0x1, 0, 0);
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/* wait for bit change */
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if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO,
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0, 0, 1) != 1) {
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pr_err("PLL GO bit not set\n");
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return -ETIMEDOUT;
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}
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/* Wait till the lock bit is set in PLL status */
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if (hdmi_wait_for_bit_change(pll->base,
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PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
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pr_err("cannot lock PLL\n");
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pr_err("CFG1 0x%x\n",
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hdmi_read_reg(pll->base, PLLCTRL_CFG1));
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pr_err("CFG2 0x%x\n",
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hdmi_read_reg(pll->base, PLLCTRL_CFG2));
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pr_err("CFG4 0x%x\n",
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hdmi_read_reg(pll->base, PLLCTRL_CFG4));
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return -ETIMEDOUT;
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}
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pr_debug("PLL locked!\n");
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return 0;
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}
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static int hdmi_pll_reset(struct hdmi_pll_data *pll)
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{
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/* SYSRESET controlled by power FSM */
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REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
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/* READ 0x0 reset is in progress */
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if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1)
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!= 1) {
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pr_err("Failed to sysreset PLL\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
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{
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u16 r = 0;
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r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
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if (r)
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return r;
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r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
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if (r)
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return r;
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r = hdmi_pll_reset(pll);
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if (r)
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return r;
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r = hdmi_pll_config(pll);
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if (r)
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return r;
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return 0;
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}
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void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
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{
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hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
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}
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#define PLL_OFFSET 0x200
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#define PLL_SIZE 0x100
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int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll)
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{
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struct resource *res;
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struct resource temp_res;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_pllctrl");
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if (!res) {
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DSSDBG("can't get PLL mem resource by name\n");
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/*
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* if hwmod/DT doesn't have the memory resource information
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* split into HDMI sub blocks by name, we try again by getting
|
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* the platform's first resource. this code will be removed when
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* the driver can get the mem resources by name
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*/
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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DSSERR("can't get PLL mem resource\n");
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return -EINVAL;
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}
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temp_res.start = res->start + PLL_OFFSET;
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temp_res.end = temp_res.start + PLL_SIZE - 1;
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res = &temp_res;
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}
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pll->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
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if (!pll->base) {
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DSSERR("can't ioremap PLLCTRL\n");
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return -ENOMEM;
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}
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return 0;
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}
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@ -155,14 +155,8 @@ struct ti_hdmi_ip_ops {
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int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len);
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int (*pll_enable)(struct hdmi_ip_data *ip_data);
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void (*pll_disable)(struct hdmi_ip_data *ip_data);
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void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
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@ -223,17 +217,22 @@ struct hdmi_wp_data {
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void __iomem *base;
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};
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struct hdmi_pll_data {
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void __iomem *base;
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struct hdmi_pll_info info;
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};
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struct hdmi_ip_data {
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struct hdmi_wp_data wp;
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struct hdmi_pll_data pll;
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unsigned long core_sys_offset;
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unsigned long core_av_offset;
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unsigned long pll_offset;
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unsigned long phy_offset;
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int irq;
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const struct ti_hdmi_ip_ops *ops;
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struct hdmi_config cfg;
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struct hdmi_pll_info pll_data;
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struct hdmi_core_infoframe_avi avi_cfg;
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/* ti_hdmi_4xxx_ip private data. These should be in a separate struct */
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@ -260,13 +259,17 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
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struct omap_video_timings *timings, struct hdmi_config *param);
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int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
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/* HDMI PLL funcs */
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int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
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void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
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void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
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void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy);
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int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
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int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
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int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len);
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int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
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@ -75,11 +75,6 @@ static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
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return ip_data->wp.base + ip_data->phy_offset;
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}
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static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
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{
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return ip_data->wp.base + ip_data->pll_offset;
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}
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static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
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{
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return ip_data->wp.base + ip_data->core_av_offset;
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@ -90,117 +85,6 @@ static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
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return ip_data->wp.base + ip_data->core_sys_offset;
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}
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static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
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{
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u32 r;
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void __iomem *pll_base = hdmi_pll_base(ip_data);
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struct hdmi_pll_info *fmt = &ip_data->pll_data;
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/* PLL start always use manual mode */
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REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
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r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
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r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
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r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
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hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
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r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
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r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
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r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
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r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
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r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
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if (fmt->dcofreq) {
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/* divider programming for frequency beyond 1000Mhz */
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REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
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r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
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} else {
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r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
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}
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hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
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r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
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r = FLD_MOD(r, fmt->regm2, 24, 18);
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r = FLD_MOD(r, fmt->regmf, 17, 0);
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hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
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/* go now */
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REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
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/* wait for bit change */
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if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
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0, 0, 1) != 1) {
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pr_err("PLL GO bit not set\n");
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return -ETIMEDOUT;
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||||
}
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||||
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||||
/* Wait till the lock bit is set in PLL status */
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if (hdmi_wait_for_bit_change(pll_base,
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PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
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pr_err("cannot lock PLL\n");
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||||
pr_err("CFG1 0x%x\n",
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hdmi_read_reg(pll_base, PLLCTRL_CFG1));
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||||
pr_err("CFG2 0x%x\n",
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hdmi_read_reg(pll_base, PLLCTRL_CFG2));
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||||
pr_err("CFG4 0x%x\n",
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hdmi_read_reg(pll_base, PLLCTRL_CFG4));
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||||
return -ETIMEDOUT;
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||||
}
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||||
|
||||
pr_debug("PLL locked!\n");
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||||
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||||
return 0;
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||||
}
|
||||
|
||||
|
||||
static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
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||||
{
|
||||
/* SYSRESET controlled by power FSM */
|
||||
REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
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||||
|
||||
/* READ 0x0 reset is in progress */
|
||||
if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
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||||
PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
|
||||
pr_err("Failed to sysreset PLL\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
|
||||
{
|
||||
u16 r = 0;
|
||||
|
||||
r = hdmi_wp_set_pll_pwr(&ip_data->wp, HDMI_PLLPWRCMD_ALLOFF);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = hdmi_wp_set_pll_pwr(&ip_data->wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
|
||||
if (r)
|
||||
return r;
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||||
|
||||
r = hdmi_pll_reset(ip_data);
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||||
if (r)
|
||||
return r;
|
||||
|
||||
r = hdmi_pll_init(ip_data);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
|
||||
{
|
||||
hdmi_wp_set_pll_pwr(&ip_data->wp, HDMI_PLLPWRCMD_ALLOFF);
|
||||
}
|
||||
|
||||
static irqreturn_t hdmi_irq_handler(int irq, void *data)
|
||||
{
|
||||
struct hdmi_ip_data *ip_data = data;
|
||||
|
|
@ -717,22 +601,6 @@ void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
|
|||
hdmi_core_av_packet_config(ip_data, repeat_cfg);
|
||||
}
|
||||
|
||||
void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
|
||||
{
|
||||
#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
|
||||
hdmi_read_reg(hdmi_pll_base(ip_data), r))
|
||||
|
||||
DUMPPLL(PLLCTRL_PLL_CONTROL);
|
||||
DUMPPLL(PLLCTRL_PLL_STATUS);
|
||||
DUMPPLL(PLLCTRL_PLL_GO);
|
||||
DUMPPLL(PLLCTRL_CFG1);
|
||||
DUMPPLL(PLLCTRL_CFG2);
|
||||
DUMPPLL(PLLCTRL_CFG3);
|
||||
DUMPPLL(PLLCTRL_SSC_CFG1);
|
||||
DUMPPLL(PLLCTRL_SSC_CFG2);
|
||||
DUMPPLL(PLLCTRL_CFG4);
|
||||
}
|
||||
|
||||
void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
|
||||
{
|
||||
int i;
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|
|
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