ath9k: Try to fix whitespace damage
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Sujith
John W. Linville
Родитель
54e4cec69e
Коммит
c16c9d0657
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@ -2854,7 +2854,6 @@ static struct eeprom_ops eep_def_ops = {
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.get_spur_channel = ath9k_hw_def_get_spur_channel
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};
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static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
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{
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return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
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@ -2871,6 +2870,7 @@ static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
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u16 *eep_data;
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int addr, eep_start_loc = AR9287_EEP_START_LOC;
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eep_data = (u16 *)eep;
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if (!ath9k_hw_use_flash(ah)) {
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DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
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"Reading from EEPROM, not flash\n");
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@ -2887,6 +2887,7 @@ static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
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}
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return true;
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}
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static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
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{
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u32 sum = 0, el, integer;
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@ -3059,6 +3060,7 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
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{
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#define TMP_VAL_VPD_TABLE \
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((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
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int i, j, k;
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int16_t ss;
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u16 idxL = 0, idxR = 0, numPiers;
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@ -3079,6 +3081,7 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
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[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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for (numPiers = 0; numPiers < availPiers; numPiers++) {
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if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
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break;
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@ -3214,7 +3217,9 @@ static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
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u16 idxL = 0, idxR = 0, numPiers;
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bool match;
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struct chan_centers centers;
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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for (numPiers = 0; numPiers < availPiers; numPiers++) {
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if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
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break;
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@ -3272,9 +3277,9 @@ static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
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}
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}
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static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
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struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset)
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struct ath9k_channel *chan,
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int16_t *pTxPowerIndexOffset)
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{
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struct cal_data_per_freq_ar9287 *pRawDataset;
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struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
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@ -3430,7 +3435,6 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
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*pTxPowerIndexOffset = 0;
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}
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static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
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struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl,
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u16 AntennaReduction, u16 twiceMaxRegulatoryPower,
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@ -3440,8 +3444,8 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
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#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
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u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
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static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9,
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AR5416_MAX_RATE_POWER };
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static const u16 tpScaleReductionTable[5] =
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{ 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
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int i;
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int16_t twiceLargestAntenna;
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struct cal_ctl_data_ar9287 *rep;
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@ -3452,8 +3456,9 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
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struct cal_target_power_ht targetPowerHt20,
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targetPowerHt40 = {0, {0, 0, 0, 0} };
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u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
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u16 ctlModesFor11g[] = {CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
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CTL_11G_EXT, CTL_2GHT40};
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u16 ctlModesFor11g[] =
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{CTL_11B, CTL_11G, CTL_2GHT20,
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CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40};
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u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
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struct chan_centers centers;
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int tx_chainmask;
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@ -3489,8 +3494,8 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
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scaledPower = max((u16)0, scaledPower);
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if (IS_CHAN_2GHZ(chan)) {
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numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
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SUB_NUM_CTL_MODES_AT_2G_40;
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numCtlModes =
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ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
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pCtlMode = ctlModesFor11g;
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ath9k_hw_get_legacy_target_powers(ah, chan,
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@ -3524,7 +3529,6 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
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}
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for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
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bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
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(pCtlMode[ctlMode] == CTL_2GHT40);
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if (isHt40CtlMode)
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@ -3534,14 +3538,15 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
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else
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freq = centers.ctl_center;
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if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
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ah->eep_ops->get_eeprom_rev(ah) <= 2)
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twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
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DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
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"LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d,"
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"EXT_ADDITIVE %d\n", ctlMode, numCtlModes,
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isHt40CtlMode, (pCtlMode[ctlMode] & EXT_ADDITIVE));
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for (i = 0; (i < AR9287_NUM_CTLS)
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&& pEepData->ctlIndex[i]; i++) {
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DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
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@ -3592,7 +3597,6 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
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ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
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scaledPower, minCtlPower);
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switch (pCtlMode[ctlMode]) {
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case CTL_11B:
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@ -3650,9 +3654,13 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
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}
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}
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ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
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ratesArray[rate18mb] = ratesArray[rate24mb] =
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ratesArray[rate6mb] =
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ratesArray[rate9mb] =
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ratesArray[rate12mb] =
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ratesArray[rate18mb] =
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ratesArray[rate24mb] =
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targetPowerOfdm.tPow2x[0];
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ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
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ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
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ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
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@ -3680,23 +3688,27 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
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if (IS_CHAN_2GHZ(chan))
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ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
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}
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#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
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#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
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}
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static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
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struct ath9k_channel *chan, u16 cfgCtl,
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u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower,
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u8 twiceAntennaReduction,
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u8 twiceMaxRegulatoryPower,
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u8 powerLimit)
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{
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#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
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#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
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struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
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struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
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int16_t ratesArray[Ar5416RateSize];
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int16_t txPowerIndexOffset = 0;
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u8 ht40PowerIncForPdadc = 2;
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int i;
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memset(ratesArray, 0, sizeof(ratesArray));
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if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
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@ -3709,7 +3721,6 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
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twiceMaxRegulatoryPower,
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powerLimit);
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ath9k_hw_set_AR9287_power_cal_table(ah, chan, &txPowerIndexOffset);
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for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
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@ -3723,49 +3734,42 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
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ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
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}
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
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ATH9K_POW_SM(ratesArray[rate18mb], 24)
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| ATH9K_POW_SM(ratesArray[rate12mb], 16)
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| ATH9K_POW_SM(ratesArray[rate9mb], 8)
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| ATH9K_POW_SM(ratesArray[rate6mb], 0)
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);
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| ATH9K_POW_SM(ratesArray[rate6mb], 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
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ATH9K_POW_SM(ratesArray[rate54mb], 24)
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| ATH9K_POW_SM(ratesArray[rate48mb], 16)
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| ATH9K_POW_SM(ratesArray[rate36mb], 8)
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| ATH9K_POW_SM(ratesArray[rate24mb], 0)
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);
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| ATH9K_POW_SM(ratesArray[rate24mb], 0));
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if (IS_CHAN_2GHZ(chan)) {
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
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ATH9K_POW_SM(ratesArray[rate2s], 24)
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| ATH9K_POW_SM(ratesArray[rate2l], 16)
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| ATH9K_POW_SM(ratesArray[rateXr], 8)
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| ATH9K_POW_SM(ratesArray[rate1l], 0)
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);
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| ATH9K_POW_SM(ratesArray[rate1l], 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
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ATH9K_POW_SM(ratesArray[rate11s], 24)
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| ATH9K_POW_SM(ratesArray[rate11l], 16)
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| ATH9K_POW_SM(ratesArray[rate5_5s], 8)
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| ATH9K_POW_SM(ratesArray[rate5_5l], 0)
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);
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| ATH9K_POW_SM(ratesArray[rate5_5l], 0));
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}
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
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ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
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| ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
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| ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
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| ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
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);
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| ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
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ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
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| ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
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| ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
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| ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
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);
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| ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
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if (IS_CHAN_HT40(chan)) {
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if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
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@ -3773,15 +3777,13 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
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ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
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| ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
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| ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
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| ATH9K_POW_SM(ratesArray[rateHt40_0], 0)
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);
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| ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
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ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
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| ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
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| ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
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| ATH9K_POW_SM(ratesArray[rateHt40_4], 0)
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);
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| ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
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} else {
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
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ATH9K_POW_SM(ratesArray[rateHt40_3] +
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@ -3791,8 +3793,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
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| ATH9K_POW_SM(ratesArray[rateHt40_1] +
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ht40PowerIncForPdadc, 8)
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| ATH9K_POW_SM(ratesArray[rateHt40_0] +
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ht40PowerIncForPdadc, 0)
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);
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ht40PowerIncForPdadc, 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
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ATH9K_POW_SM(ratesArray[rateHt40_7] +
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@ -3802,20 +3803,16 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
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| ATH9K_POW_SM(ratesArray[rateHt40_5] +
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ht40PowerIncForPdadc, 8)
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| ATH9K_POW_SM(ratesArray[rateHt40_4] +
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ht40PowerIncForPdadc, 0)
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);
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ht40PowerIncForPdadc, 0));
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}
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
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ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
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| ATH9K_POW_SM(ratesArray[rateExtCck], 16)
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| ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
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| ATH9K_POW_SM(ratesArray[rateDupCck], 0)
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);
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| ATH9K_POW_SM(ratesArray[rateDupCck], 0));
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}
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if (IS_CHAN_2GHZ(chan))
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i = rate1l;
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else
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@ -3848,7 +3845,6 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
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static void ath9k_hw_AR9287_set_addac(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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return;
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}
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static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
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@ -3856,7 +3852,6 @@ static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
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{
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struct ar9287_eeprom *eep = &ah->eeprom.map9287;
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struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
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u16 antWrites[AR9287_ANT_16S];
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u32 regChainOffset;
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u8 txRxAttenLocal;
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@ -3886,7 +3881,6 @@ static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
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antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
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}
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REG_WRITE(ah, AR_PHY_SWITCH_COM,
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ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
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@ -4000,18 +3994,15 @@ static u8 ath9k_hw_AR9287_get_num_ant_config(struct ath_hw *ah,
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return 1;
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}
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static u16 ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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struct ar9287_eeprom *eep = &ah->eeprom.map9287;
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struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
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return pModal->antCtrlCommon & 0xFFFF;
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}
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static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
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u16 i, bool is2GHz)
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{
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|
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@ -4055,10 +4046,10 @@ static struct eeprom_ops eep_AR9287_ops = {
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.get_spur_channel = ath9k_hw_AR9287_get_spur_channel
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};
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int ath9k_hw_eeprom_init(struct ath_hw *ah)
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{
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int status;
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if (AR_SREV_9287(ah)) {
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ah->eep_map = EEP_MAP_AR9287;
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ah->eep_ops = &eep_AR9287_ops;
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|
|
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@ -421,7 +421,6 @@ struct modal_eep_4k_header {
|
|||
u16 db1_234;
|
||||
u16 db2_234;
|
||||
u8 futureModal[4];
|
||||
|
||||
struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
|
||||
} __packed;
|
||||
|
||||
|
|
@ -483,8 +482,6 @@ struct modal_eep_ar9287_header {
|
|||
struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
|
||||
} __packed;
|
||||
|
||||
|
||||
|
||||
struct cal_data_per_freq {
|
||||
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
||||
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
||||
|
|
@ -525,7 +522,6 @@ struct cal_data_op_loop_ar9287 {
|
|||
u8 empty[2][5];
|
||||
} __packed;
|
||||
|
||||
|
||||
struct cal_data_per_freq_ar9287 {
|
||||
u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
|
||||
u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
|
||||
|
|
@ -620,7 +616,6 @@ struct ar9287_eeprom {
|
|||
u8 padding;
|
||||
} __packed;
|
||||
|
||||
|
||||
enum reg_ext_bitmap {
|
||||
REG_EXT_JAPAN_MIDBAND = 1,
|
||||
REG_EXT_FCC_DFS_HT40 = 2,
|
||||
|
|
|
|||
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