OMAP3: PM: PRCM context save/restore
Add context save and restore for PRCM module to support off-mode. Additional registers (CM_CLKSEL4, CM_CLKEN, CM_CLKEN2) added by Tero Kristo. Missing CM_CLKEN_PLL_IVA2 register added by Kalle Jokiniemi. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Rajendra Nayak
Kevin Hilman
Родитель
0addd61bc2
Коммит
c171a25861
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@ -7,6 +7,9 @@
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*
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* Written by Tony Lindgren <tony.lindgren@nokia.com>
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -21,8 +24,11 @@
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#include <plat/common.h>
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#include <plat/prcm.h>
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#include <plat/irqs.h>
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#include <plat/control.h>
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#include "clock.h"
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#include "cm.h"
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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@ -31,6 +37,88 @@ static void __iomem *cm_base;
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#define MAX_MODULE_ENABLE_WAIT 100000
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struct omap3_prcm_regs {
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u32 control_padconf_sys_nirq;
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u32 iva2_cm_clksel2;
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u32 cm_sysconfig;
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u32 sgx_cm_clksel;
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u32 wkup_cm_clksel;
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u32 dss_cm_clksel;
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u32 cam_cm_clksel;
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u32 per_cm_clksel;
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u32 emu_cm_clksel;
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u32 emu_cm_clkstctrl;
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u32 pll_cm_autoidle2;
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u32 pll_cm_clksel4;
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u32 pll_cm_clksel5;
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u32 pll_cm_clken;
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u32 pll_cm_clken2;
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u32 cm_polctrl;
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u32 iva2_cm_fclken;
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u32 iva2_cm_clken_pll;
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u32 core_cm_fclken1;
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u32 core_cm_fclken3;
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u32 sgx_cm_fclken;
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u32 wkup_cm_fclken;
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u32 dss_cm_fclken;
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u32 cam_cm_fclken;
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u32 per_cm_fclken;
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u32 usbhost_cm_fclken;
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u32 core_cm_iclken1;
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u32 core_cm_iclken2;
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u32 core_cm_iclken3;
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u32 sgx_cm_iclken;
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u32 wkup_cm_iclken;
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u32 dss_cm_iclken;
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u32 cam_cm_iclken;
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u32 per_cm_iclken;
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u32 usbhost_cm_iclken;
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u32 iva2_cm_autiidle2;
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u32 mpu_cm_autoidle2;
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u32 pll_cm_autoidle;
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u32 iva2_cm_clkstctrl;
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u32 mpu_cm_clkstctrl;
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u32 core_cm_clkstctrl;
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u32 sgx_cm_clkstctrl;
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u32 dss_cm_clkstctrl;
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u32 cam_cm_clkstctrl;
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u32 per_cm_clkstctrl;
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u32 neon_cm_clkstctrl;
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u32 usbhost_cm_clkstctrl;
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u32 core_cm_autoidle1;
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u32 core_cm_autoidle2;
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u32 core_cm_autoidle3;
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u32 wkup_cm_autoidle;
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u32 dss_cm_autoidle;
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u32 cam_cm_autoidle;
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u32 per_cm_autoidle;
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u32 usbhost_cm_autoidle;
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u32 sgx_cm_sleepdep;
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u32 dss_cm_sleepdep;
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u32 cam_cm_sleepdep;
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u32 per_cm_sleepdep;
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u32 usbhost_cm_sleepdep;
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u32 cm_clkout_ctrl;
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u32 prm_clkout_ctrl;
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u32 sgx_pm_wkdep;
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u32 dss_pm_wkdep;
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u32 cam_pm_wkdep;
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u32 per_pm_wkdep;
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u32 neon_pm_wkdep;
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u32 usbhost_pm_wkdep;
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u32 core_pm_mpugrpsel1;
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u32 iva2_pm_ivagrpsel1;
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u32 core_pm_mpugrpsel3;
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u32 core_pm_ivagrpsel3;
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u32 wkup_pm_mpugrpsel;
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u32 wkup_pm_ivagrpsel;
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u32 per_pm_mpugrpsel;
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u32 per_pm_ivagrpsel;
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u32 wkup_pm_wken;
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};
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struct omap3_prcm_regs prcm_context;
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u32 omap_prcm_get_reset_sources(void)
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{
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/* XXX This presumably needs modification for 34XX */
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@ -168,3 +256,304 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
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prm_base = omap2_globals->prm;
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cm_base = omap2_globals->cm;
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}
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#ifdef CONFIG_ARCH_OMAP3
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void omap3_prcm_save_context(void)
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{
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prcm_context.control_padconf_sys_nirq =
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omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
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prcm_context.iva2_cm_clksel2 =
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cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
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prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
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prcm_context.sgx_cm_clksel =
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cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
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prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
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prcm_context.dss_cm_clksel =
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cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
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prcm_context.cam_cm_clksel =
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cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
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prcm_context.per_cm_clksel =
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cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
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prcm_context.emu_cm_clksel =
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cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
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prcm_context.emu_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
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prcm_context.pll_cm_autoidle2 =
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cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
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prcm_context.pll_cm_clksel4 =
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cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
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prcm_context.pll_cm_clksel5 =
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cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
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prcm_context.pll_cm_clken =
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cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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prcm_context.pll_cm_clken2 =
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cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
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prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
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prcm_context.iva2_cm_fclken =
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cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
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prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
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OMAP3430_CM_CLKEN_PLL);
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prcm_context.core_cm_fclken1 =
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cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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prcm_context.core_cm_fclken3 =
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cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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prcm_context.sgx_cm_fclken =
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cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
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prcm_context.wkup_cm_fclken =
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cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
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prcm_context.dss_cm_fclken =
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cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
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prcm_context.cam_cm_fclken =
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cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
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prcm_context.per_cm_fclken =
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cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
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prcm_context.usbhost_cm_fclken =
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cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
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prcm_context.core_cm_iclken1 =
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cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
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prcm_context.core_cm_iclken2 =
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cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
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prcm_context.core_cm_iclken3 =
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cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
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prcm_context.sgx_cm_iclken =
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cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
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prcm_context.wkup_cm_iclken =
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cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
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prcm_context.dss_cm_iclken =
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cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
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prcm_context.cam_cm_iclken =
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cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
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prcm_context.per_cm_iclken =
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cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
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prcm_context.usbhost_cm_iclken =
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cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
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prcm_context.iva2_cm_autiidle2 =
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cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
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prcm_context.mpu_cm_autoidle2 =
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cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
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prcm_context.pll_cm_autoidle =
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cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
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prcm_context.iva2_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
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prcm_context.mpu_cm_clkstctrl =
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cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
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prcm_context.core_cm_clkstctrl =
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cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
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prcm_context.sgx_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
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prcm_context.dss_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
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prcm_context.cam_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
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prcm_context.per_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
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prcm_context.neon_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
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prcm_context.usbhost_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
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prcm_context.core_cm_autoidle1 =
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cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
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prcm_context.core_cm_autoidle2 =
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cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
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prcm_context.core_cm_autoidle3 =
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cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
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prcm_context.wkup_cm_autoidle =
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cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
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prcm_context.dss_cm_autoidle =
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cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
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prcm_context.cam_cm_autoidle =
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cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
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prcm_context.per_cm_autoidle =
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cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
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prcm_context.usbhost_cm_autoidle =
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cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
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prcm_context.sgx_cm_sleepdep =
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cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
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prcm_context.dss_cm_sleepdep =
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cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
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prcm_context.cam_cm_sleepdep =
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cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
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prcm_context.per_cm_sleepdep =
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cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
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prcm_context.usbhost_cm_sleepdep =
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cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
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prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
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OMAP3_CM_CLKOUT_CTRL_OFFSET);
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prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
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OMAP3_PRM_CLKOUT_CTRL_OFFSET);
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prcm_context.sgx_pm_wkdep =
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prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
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prcm_context.dss_pm_wkdep =
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prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
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prcm_context.cam_pm_wkdep =
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prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
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prcm_context.per_pm_wkdep =
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prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
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prcm_context.neon_pm_wkdep =
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prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
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prcm_context.usbhost_pm_wkdep =
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prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
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prcm_context.core_pm_mpugrpsel1 =
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prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
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prcm_context.iva2_pm_ivagrpsel1 =
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prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
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prcm_context.core_pm_mpugrpsel3 =
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prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
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prcm_context.core_pm_ivagrpsel3 =
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prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
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prcm_context.wkup_pm_mpugrpsel =
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prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
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prcm_context.wkup_pm_ivagrpsel =
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prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
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prcm_context.per_pm_mpugrpsel =
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prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
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prcm_context.per_pm_ivagrpsel =
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prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
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prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
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return;
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}
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void omap3_prcm_restore_context(void)
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{
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omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
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OMAP343X_CONTROL_PADCONF_SYSNIRQ);
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cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
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CM_CLKSEL2);
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__raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
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cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
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CM_CLKSEL);
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cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
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cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
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CM_CLKSEL);
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cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
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CM_CLKSEL);
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cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
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CM_CLKSEL);
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cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
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CM_CLKSEL1);
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cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
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CM_CLKSTCTRL);
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cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
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CM_AUTOIDLE2);
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cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
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OMAP3430ES2_CM_CLKSEL4);
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cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
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OMAP3430ES2_CM_CLKSEL5);
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cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
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cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
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OMAP3430ES2_CM_CLKEN2);
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__raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
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cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
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CM_FCLKEN);
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cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
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OMAP3430_CM_CLKEN_PLL);
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cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
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cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
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OMAP3430ES2_CM_FCLKEN3);
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cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
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CM_FCLKEN);
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cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
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cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
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CM_FCLKEN);
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cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
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CM_FCLKEN);
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cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
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CM_FCLKEN);
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cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
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OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
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||||
cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
|
||||
cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
|
||||
cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
|
||||
cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
|
||||
CM_ICLKEN);
|
||||
cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
|
||||
cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
|
||||
CM_ICLKEN);
|
||||
cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
|
||||
CM_ICLKEN);
|
||||
cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
|
||||
CM_ICLKEN);
|
||||
cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
|
||||
OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
|
||||
cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
|
||||
CM_AUTOIDLE2);
|
||||
cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
|
||||
cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
|
||||
cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
|
||||
CM_CLKSTCTRL);
|
||||
cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
|
||||
cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
|
||||
CM_CLKSTCTRL);
|
||||
cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
|
||||
CM_CLKSTCTRL);
|
||||
cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
|
||||
CM_CLKSTCTRL);
|
||||
cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
|
||||
CM_CLKSTCTRL);
|
||||
cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
|
||||
CM_CLKSTCTRL);
|
||||
cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
|
||||
CM_CLKSTCTRL);
|
||||
cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
|
||||
OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
|
||||
cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
|
||||
CM_AUTOIDLE1);
|
||||
cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
|
||||
CM_AUTOIDLE2);
|
||||
cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
|
||||
CM_AUTOIDLE3);
|
||||
cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
|
||||
cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
|
||||
CM_AUTOIDLE);
|
||||
cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
|
||||
CM_AUTOIDLE);
|
||||
cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
|
||||
CM_AUTOIDLE);
|
||||
cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
|
||||
OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
|
||||
cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
|
||||
OMAP3430_CM_SLEEPDEP);
|
||||
cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
|
||||
OMAP3430_CM_SLEEPDEP);
|
||||
cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
|
||||
OMAP3430_CM_SLEEPDEP);
|
||||
cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
|
||||
OMAP3430_CM_SLEEPDEP);
|
||||
cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
|
||||
OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
|
||||
cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
|
||||
OMAP3_CM_CLKOUT_CTRL_OFFSET);
|
||||
prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
|
||||
OMAP3_PRM_CLKOUT_CTRL_OFFSET);
|
||||
prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
|
||||
PM_WKDEP);
|
||||
prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
|
||||
PM_WKDEP);
|
||||
prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
|
||||
PM_WKDEP);
|
||||
prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
|
||||
PM_WKDEP);
|
||||
prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
|
||||
PM_WKDEP);
|
||||
prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
|
||||
OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
|
||||
prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
|
||||
OMAP3430_PM_MPUGRPSEL1);
|
||||
prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
|
||||
OMAP3430_PM_IVAGRPSEL1);
|
||||
prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
|
||||
OMAP3430ES2_PM_MPUGRPSEL3);
|
||||
prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
|
||||
OMAP3430ES2_PM_IVAGRPSEL3);
|
||||
prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
|
||||
OMAP3430_PM_MPUGRPSEL);
|
||||
prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
|
||||
OMAP3430_PM_IVAGRPSEL);
|
||||
prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
|
||||
OMAP3430_PM_MPUGRPSEL);
|
||||
prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
|
||||
OMAP3430_PM_IVAGRPSEL);
|
||||
prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -112,6 +112,8 @@
|
|||
#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
|
||||
#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
|
||||
|
||||
#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
|
||||
|
||||
/* 34xx-only CONTROL_GENERAL register offsets */
|
||||
#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
|
||||
#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
|
||||
|
|
|
|||
|
|
@ -27,9 +27,13 @@ u32 omap_prcm_get_reset_sources(void);
|
|||
void omap_prcm_arch_reset(char mode);
|
||||
int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
|
||||
|
||||
#define START_PADCONF_SAVE 0x2
|
||||
#define PADCONF_SAVE_DONE 0x1
|
||||
|
||||
void omap3_prcm_save_context(void);
|
||||
void omap3_prcm_restore_context(void);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
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